113a114,118
>
> # default to 0 bank groups per rank, indicating bank group architecture
> # is not used
> # update per memory class when bank group architecture is supported
> bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
149a155,157
> # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
> # With bank group architectures, tBURST represents the CAS-to-CAS
> # delay for bursts to different bank groups (tCCD_S)
151a160,165
> # CAS-to-CAS delay for bursts to the same bank group
> # only utilized with bank group architectures; set to 0 for default case
> # tBURST is equivalent to tCCD_S; no explicit parameter required
> # for CAS-to-CAS delay for bursts to different bank groups
> tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
>
173a188,190
> # only utilized with bank group architectures; set to 0 for default case
> tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
>
276a294,297
> # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
> # Set to 4 for x4, x8 case
> bank_groups_per_rank = 4
>
285a307,309
> # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
> # With bank group architectures, tBURST represents the CAS-to-CAS
> # delay for bursts to different bank groups (tCCD_S)
287a312,317
> # @2400 data rate, tCCD_L is 6 CK
> # CAS-to-CAS delay for bursts to the same bank group
> # tBURST is equivalent to tCCD_S; no explicit parameter required
> # for CAS-to-CAS delay for bursts to different bank groups
> tCCD_L = '5ns';
>
294,295c324,329
< # Here using the average of RRD_S and RRD_L
< tRRD = '4.1ns'
---
> # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
> tRRD = '3.3ns'
>
> # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
> tRRD_L = '4.9ns';
>