159,160c159,160
< # write-to-read turn around penalty
< tWTR = Param.Latency("Write to read switching time")
---
> # write-to-read, same rank turnaround penalty
> tWTR = Param.Latency("Write to read, same rank switching time")
162,163c162,163
< # read-to-write turn around penalty, bus turnaround delay
< tRTW = Param.Latency("Read to write switching time")
---
> # read-to-write, same rank turnaround penalty
> tRTW = Param.Latency("Read to write, same rank switching time")
164a165,170
> # rank-to-rank bus delay penalty
> # this does not correlate to a memory timing parameter and encompasses:
> # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
> # different rank bus delay
> tCS = Param.Latency("Rank to rank switching time")
>
224c230
< # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
---
> # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
226a233,235
> # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
> tCS = '2.5ns'
>
299c308
< # Default read-to-write bus around to 2 CK, @1200 MHz = 1.666 ns
---
> # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
301a311,313
> # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
> tCS = '1.666ns'
>
356c368
< # Default read-to-write bus around to 2 CK, @666.66 MHz = 3 ns
---
> # Default same rank rd-to-wr bus turnaround to 2 CK, @666.66 MHz = 3 ns
358a371,373
> # Default different rank bus delay to 2 CK, @666.66 MHz = 3 ns
> tCS = '3ns'
>
419c434
< # Default read-to-write bus around to 2 CK, @533 MHz = 3.75 ns
---
> # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
421a437,439
> # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
> tCS = '3.75ns'
>
476c494
< # Default read-to-write bus around to 2 CK, @200 MHz = 10 ns
---
> # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
478a497,499
> # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
> tCS = '10ns'
>
539c560
< # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
---
> # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
541a563,565
> # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
> tCS = '2.5ns'
>
< # write-to-read turn around penalty
< tWTR = Param.Latency("Write to read switching time")
---
> # write-to-read, same rank turnaround penalty
> tWTR = Param.Latency("Write to read, same rank switching time")
162,163c162,163
< # read-to-write turn around penalty, bus turnaround delay
< tRTW = Param.Latency("Read to write switching time")
---
> # read-to-write, same rank turnaround penalty
> tRTW = Param.Latency("Read to write, same rank switching time")
164a165,170
> # rank-to-rank bus delay penalty
> # this does not correlate to a memory timing parameter and encompasses:
> # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
> # different rank bus delay
> tCS = Param.Latency("Rank to rank switching time")
>
224c230
< # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
---
> # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
226a233,235
> # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
> tCS = '2.5ns'
>
299c308
< # Default read-to-write bus around to 2 CK, @1200 MHz = 1.666 ns
---
> # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
301a311,313
> # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
> tCS = '1.666ns'
>
356c368
< # Default read-to-write bus around to 2 CK, @666.66 MHz = 3 ns
---
> # Default same rank rd-to-wr bus turnaround to 2 CK, @666.66 MHz = 3 ns
358a371,373
> # Default different rank bus delay to 2 CK, @666.66 MHz = 3 ns
> tCS = '3ns'
>
419c434
< # Default read-to-write bus around to 2 CK, @533 MHz = 3.75 ns
---
> # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
421a437,439
> # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
> tCS = '3.75ns'
>
476c494
< # Default read-to-write bus around to 2 CK, @200 MHz = 10 ns
---
> # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
478a497,499
> # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
> tCS = '10ns'
>
539c560
< # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
---
> # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
541a563,565
> # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
> tCS = '2.5ns'
>