1# Copyright (c) 2012-2018 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2013 Amin Farmahini-Farahani
14# Copyright (c) 2015 University of Kaiserslautern
15# Copyright (c) 2015 The University of Bologna
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Andreas Hansson
42# Ani Udipi
43# Omar Naji
44# Matthias Jung
45# Erfan Azarkhish
46
47from m5.params import *
48from m5.proxy import *
49from m5.objects.AbstractMemory import *
50from m5.objects.QoSMemCtrl import *
51
52# Enum for memory scheduling algorithms, currently First-Come
53# First-Served and a First-Row Hit then First-Come First-Served
54class MemSched(Enum): vals = ['fcfs', 'frfcfs']
55
56# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
57# channel, rank, bank, row and column, respectively, and going from
58# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
59# suitable for an open-page policy, optimising for sequential accesses
60# hitting in the open row. For a closed-page policy, RoCoRaBaCh
61# maximises parallelism.
62class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
63
64# Enum for the page policy, either open, open_adaptive, close, or
65# close_adaptive.
66class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
67 'close_adaptive']
68
69# DRAMCtrl is a single-channel single-ported DRAM controller model
70# that aims to model the most important system-level performance
71# effects of a DRAM without getting into too much detail of the DRAM
72# itself.
73class DRAMCtrl(QoSMemCtrl):
74 type = 'DRAMCtrl'
75 cxx_header = "mem/dram_ctrl.hh"
76
77 # single-ported on the system interface side, instantiate with a
78 # bus in front of the controller for multiple ports
79 port = SlavePort("Slave port")
80
81 # the basic configuration of the controller architecture, note
82 # that each entry corresponds to a burst for the specific DRAM
83 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
84 # the cacheline size or request/packet size
85 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
86 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
87
88 # threshold in percent for when to forcefully trigger writes and
89 # start emptying the write buffer
90 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
91
92 # threshold in percentage for when to start writes if the read
93 # queue is empty
94 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
95
96 # minimum write bursts to schedule before switching back to reads
97 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
98 "switching to reads")
99
100 # scheduler, address map and page policy
101 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
102 addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
103 page_policy = Param.PageManage('open_adaptive', "Page management policy")
104
105 # enforce a limit on the number of accesses per row
106 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
107 "closing");
108
109 # size of DRAM Chip in Bytes
110 device_size = Param.MemorySize("Size of DRAM chip")
111
112 # pipeline latency of the controller and PHY, split into a
113 # frontend part and a backend part, with reads and writes serviced
114 # by the queues only seeing the frontend contribution, and reads
115 # serviced by the memory seeing the sum of the two
116 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
117 static_backend_latency = Param.Latency("10ns", "Static backend latency")
118
119 # the physical organisation of the DRAM
120 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
121 "device/chip")
122 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
123 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
124 "device/chip")
125 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
126 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
127
128 # default to 0 bank groups per rank, indicating bank group architecture
129 # is not used
130 # update per memory class when bank group architecture is supported
131 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
132 banks_per_rank = Param.Unsigned("Number of banks per rank")
133 # only used for the address mapping as the controller by
134 # construction is a single channel and multiple controllers have
135 # to be instantiated for a multi-channel configuration
136 channels = Param.Unsigned(1, "Number of channels")
137
| 1# Copyright (c) 2012-2018 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2013 Amin Farmahini-Farahani
14# Copyright (c) 2015 University of Kaiserslautern
15# Copyright (c) 2015 The University of Bologna
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Andreas Hansson
42# Ani Udipi
43# Omar Naji
44# Matthias Jung
45# Erfan Azarkhish
46
47from m5.params import *
48from m5.proxy import *
49from m5.objects.AbstractMemory import *
50from m5.objects.QoSMemCtrl import *
51
52# Enum for memory scheduling algorithms, currently First-Come
53# First-Served and a First-Row Hit then First-Come First-Served
54class MemSched(Enum): vals = ['fcfs', 'frfcfs']
55
56# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
57# channel, rank, bank, row and column, respectively, and going from
58# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
59# suitable for an open-page policy, optimising for sequential accesses
60# hitting in the open row. For a closed-page policy, RoCoRaBaCh
61# maximises parallelism.
62class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
63
64# Enum for the page policy, either open, open_adaptive, close, or
65# close_adaptive.
66class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
67 'close_adaptive']
68
69# DRAMCtrl is a single-channel single-ported DRAM controller model
70# that aims to model the most important system-level performance
71# effects of a DRAM without getting into too much detail of the DRAM
72# itself.
73class DRAMCtrl(QoSMemCtrl):
74 type = 'DRAMCtrl'
75 cxx_header = "mem/dram_ctrl.hh"
76
77 # single-ported on the system interface side, instantiate with a
78 # bus in front of the controller for multiple ports
79 port = SlavePort("Slave port")
80
81 # the basic configuration of the controller architecture, note
82 # that each entry corresponds to a burst for the specific DRAM
83 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
84 # the cacheline size or request/packet size
85 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
86 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
87
88 # threshold in percent for when to forcefully trigger writes and
89 # start emptying the write buffer
90 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
91
92 # threshold in percentage for when to start writes if the read
93 # queue is empty
94 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
95
96 # minimum write bursts to schedule before switching back to reads
97 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
98 "switching to reads")
99
100 # scheduler, address map and page policy
101 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
102 addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
103 page_policy = Param.PageManage('open_adaptive', "Page management policy")
104
105 # enforce a limit on the number of accesses per row
106 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
107 "closing");
108
109 # size of DRAM Chip in Bytes
110 device_size = Param.MemorySize("Size of DRAM chip")
111
112 # pipeline latency of the controller and PHY, split into a
113 # frontend part and a backend part, with reads and writes serviced
114 # by the queues only seeing the frontend contribution, and reads
115 # serviced by the memory seeing the sum of the two
116 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
117 static_backend_latency = Param.Latency("10ns", "Static backend latency")
118
119 # the physical organisation of the DRAM
120 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
121 "device/chip")
122 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
123 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
124 "device/chip")
125 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
126 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
127
128 # default to 0 bank groups per rank, indicating bank group architecture
129 # is not used
130 # update per memory class when bank group architecture is supported
131 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
132 banks_per_rank = Param.Unsigned("Number of banks per rank")
133 # only used for the address mapping as the controller by
134 # construction is a single channel and multiple controllers have
135 # to be instantiated for a multi-channel configuration
136 channels = Param.Unsigned(1, "Number of channels")
137
|
138 # For power modelling we need to know if the DRAM has a DLL or not
139 dll = Param.Bool(True, "DRAM has DLL or not")
140
141 # DRAMPower provides in addition to the core power, the possibility to
142 # include RD/WR termination and IO power. This calculation assumes some
143 # default values. The integration of DRAMPower with gem5 does not include
144 # IO and RD/WR termination power by default. This might be added as an
145 # additional feature in the future.
146
147 # timing behaviour and constraints - all in nanoseconds
148
149 # the base clock period of the DRAM
150 tCK = Param.Latency("Clock period")
151
152 # the amount of time in nanoseconds from issuing an activate command
153 # to the data being available in the row buffer for a read/write
154 tRCD = Param.Latency("RAS to CAS delay")
155
156 # the time from issuing a read/write command to seeing the actual data
157 tCL = Param.Latency("CAS latency")
158
159 # minimum time between a precharge and subsequent activate
160 tRP = Param.Latency("Row precharge time")
161
162 # minimum time between an activate and a precharge to the same row
163 tRAS = Param.Latency("ACT to PRE delay")
164
165 # minimum time between a write data transfer and a precharge
166 tWR = Param.Latency("Write recovery time")
167
168 # minimum time between a read and precharge command
169 tRTP = Param.Latency("Read to precharge")
170
171 # time to complete a burst transfer, typically the burst length
172 # divided by two due to the DDR bus, but by making it a parameter
173 # it is easier to also evaluate SDR memories like WideIO.
174 # This parameter has to account for burst length.
175 # Read/Write requests with data size larger than one full burst are broken
176 # down into multiple requests in the controller
177 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
178 # With bank group architectures, tBURST represents the CAS-to-CAS
179 # delay for bursts to different bank groups (tCCD_S)
180 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
181
182 # CAS-to-CAS delay for bursts to the same bank group
183 # only utilized with bank group architectures; set to 0 for default case
184 # tBURST is equivalent to tCCD_S; no explicit parameter required
185 # for CAS-to-CAS delay for bursts to different bank groups
186 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
187
188 # Write-to-Write delay for bursts to the same bank group
189 # only utilized with bank group architectures; set to 0 for default case
190 # This will be used to enable different same bank group delays
191 # for writes versus reads
192 tCCD_L_WR = Param.Latency(Self.tCCD_L,
193 "Same bank group Write to Write delay")
194
195 # time taken to complete one refresh cycle (N rows in all banks)
196 tRFC = Param.Latency("Refresh cycle time")
197
198 # refresh command interval, how often a "ref" command needs
199 # to be sent. It is 7.8 us for a 64ms refresh requirement
200 tREFI = Param.Latency("Refresh command interval")
201
202 # write-to-read, same rank turnaround penalty
203 tWTR = Param.Latency("Write to read, same rank switching time")
204
205 # read-to-write, same rank turnaround penalty
206 tRTW = Param.Latency("Read to write, same rank switching time")
207
208 # rank-to-rank bus delay penalty
209 # this does not correlate to a memory timing parameter and encompasses:
210 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
211 # different rank bus delay
212 tCS = Param.Latency("Rank to rank switching time")
213
214 # minimum row activate to row activate delay time
215 tRRD = Param.Latency("ACT to ACT delay")
216
217 # only utilized with bank group architectures; set to 0 for default case
218 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
219
220 # time window in which a maximum number of activates are allowed
221 # to take place, set to 0 to disable
222 tXAW = Param.Latency("X activation window")
223 activation_limit = Param.Unsigned("Max number of activates in window")
224
225 # time to exit power-down mode
226 # Exit power-down to next valid command delay
227 tXP = Param.Latency("0ns", "Power-up Delay")
228
229 # Exit Powerdown to commands requiring a locked DLL
230 tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
231
232 # time to exit self-refresh mode
233 tXS = Param.Latency("0ns", "Self-refresh exit latency")
234
235 # time to exit self-refresh mode with locked DLL
236 tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
237
238 # Currently rolled into other params
239 ######################################################################
240
241 # tRC - assumed to be tRAS + tRP
242
243 # Power Behaviour and Constraints
244 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
245 # defined as VDD and VDD2. Each current is defined for each voltage domain
246 # separately. For example, current IDD0 is active-precharge current for
247 # voltage domain VDD and current IDD02 is active-precharge current for
248 # voltage domain VDD2.
249 # By default all currents are set to 0mA. Users who are only interested in
250 # the performance of DRAMs can leave them at 0.
251
252 # Operating 1 Bank Active-Precharge current
253 IDD0 = Param.Current("0mA", "Active precharge current")
254
255 # Operating 1 Bank Active-Precharge current multiple voltage Range
256 IDD02 = Param.Current("0mA", "Active precharge current VDD2")
257
258 # Precharge Power-down Current: Slow exit
259 IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
260
261 # Precharge Power-down Current: Slow exit multiple voltage Range
262 IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
263
264 # Precharge Power-down Current: Fast exit
265 IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
266
267 # Precharge Power-down Current: Fast exit multiple voltage Range
268 IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
269
270 # Precharge Standby current
271 IDD2N = Param.Current("0mA", "Precharge Standby current")
272
273 # Precharge Standby current multiple voltage range
274 IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
275
276 # Active Power-down current: slow exit
277 IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
278
279 # Active Power-down current: slow exit multiple voltage range
280 IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
281
282 # Active Power-down current : fast exit
283 IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
284
285 # Active Power-down current : fast exit multiple voltage range
286 IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
287
288 # Active Standby current
289 IDD3N = Param.Current("0mA", "Active Standby current")
290
291 # Active Standby current multiple voltage range
292 IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
293
294 # Burst Read Operating Current
295 IDD4R = Param.Current("0mA", "READ current")
296
297 # Burst Read Operating Current multiple voltage range
298 IDD4R2 = Param.Current("0mA", "READ current VDD2")
299
300 # Burst Write Operating Current
301 IDD4W = Param.Current("0mA", "WRITE current")
302
303 # Burst Write Operating Current multiple voltage range
304 IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
305
306 # Refresh Current
307 IDD5 = Param.Current("0mA", "Refresh current")
308
309 # Refresh Current multiple voltage range
310 IDD52 = Param.Current("0mA", "Refresh current VDD2")
311
312 # Self-Refresh Current
313 IDD6 = Param.Current("0mA", "Self-refresh Current")
314
315 # Self-Refresh Current multiple voltage range
316 IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
317
318 # Main voltage range of the DRAM
319 VDD = Param.Voltage("0V", "Main Voltage Range")
320
321 # Second voltage range defined by some DRAMs
322 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
323
324# A single DDR3-1600 x64 channel (one command and address bus), with
325# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
326# an 8x8 configuration.
327class DDR3_1600_8x8(DRAMCtrl):
328 # size of device in bytes
329 device_size = '512MB'
330
331 # 8x8 configuration, 8 devices each with an 8-bit interface
332 device_bus_width = 8
333
334 # DDR3 is a BL8 device
335 burst_length = 8
336
337 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
338 device_rowbuffer_size = '1kB'
339
340 # 8x8 configuration, so 8 devices
341 devices_per_rank = 8
342
343 # Use two ranks
344 ranks_per_channel = 2
345
346 # DDR3 has 8 banks in all configurations
347 banks_per_rank = 8
348
349 # 800 MHz
350 tCK = '1.25ns'
351
352 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
353 tBURST = '5ns'
354
355 # DDR3-1600 11-11-11
356 tRCD = '13.75ns'
357 tCL = '13.75ns'
358 tRP = '13.75ns'
359 tRAS = '35ns'
360 tRRD = '6ns'
361 tXAW = '30ns'
362 activation_limit = 4
363 tRFC = '260ns'
364
365 tWR = '15ns'
366
367 # Greater of 4 CK or 7.5 ns
368 tWTR = '7.5ns'
369
370 # Greater of 4 CK or 7.5 ns
371 tRTP = '7.5ns'
372
373 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
374 tRTW = '2.5ns'
375
376 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
377 tCS = '2.5ns'
378
379 # <=85C, half for >85C
380 tREFI = '7.8us'
381
382 # active powerdown and precharge powerdown exit time
383 tXP = '6ns'
384
385 # self refresh exit time
386 tXS = '270ns'
387
388 # Current values from datasheet Die Rev E,J
389 IDD0 = '55mA'
390 IDD2N = '32mA'
391 IDD3N = '38mA'
392 IDD4W = '125mA'
393 IDD4R = '157mA'
394 IDD5 = '235mA'
395 IDD3P1 = '38mA'
396 IDD2P1 = '32mA'
397 IDD6 = '20mA'
398 VDD = '1.5V'
399
400# A single HMC-2500 x32 model based on:
401# [1] DRAMSpec: a high-level DRAM bank modelling tool
402# developed at the University of Kaiserslautern. This high level tool
403# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
404# estimate the DRAM bank latency and power numbers.
405# [2] High performance AXI-4.0 based interconnect for extensible smart memory
406# cubes (E. Azarkhish et. al)
407# Assumed for the HMC model is a 30 nm technology node.
408# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
409# layers).
410# Each layer has 16 vaults and each vault consists of 2 banks per layer.
411# In order to be able to use the same controller used for 2D DRAM generations
412# for HMC, the following analogy is done:
413# Channel (DDR) => Vault (HMC)
414# device_size (DDR) => size of a single layer in a vault
415# ranks per channel (DDR) => number of layers
416# banks per rank (DDR) => banks per layer
417# devices per rank (DDR) => devices per layer ( 1 for HMC).
418# The parameters for which no input is available are inherited from the DDR3
419# configuration.
420# This configuration includes the latencies from the DRAM to the logic layer
421# of the HMC
422class HMC_2500_1x32(DDR3_1600_8x8):
423 # size of device
424 # two banks per device with each bank 4MB [2]
425 device_size = '8MB'
426
427 # 1x32 configuration, 1 device with 32 TSVs [2]
428 device_bus_width = 32
429
430 # HMC is a BL8 device [2]
431 burst_length = 8
432
433 # Each device has a page (row buffer) size of 256 bytes [2]
434 device_rowbuffer_size = '256B'
435
436 # 1x32 configuration, so 1 device [2]
437 devices_per_rank = 1
438
439 # 4 layers so 4 ranks [2]
440 ranks_per_channel = 4
441
442 # HMC has 2 banks per layer [2]
443 # Each layer represents a rank. With 4 layers and 8 banks in total, each
444 # layer has 2 banks; thus 2 banks per rank.
445 banks_per_rank = 2
446
447 # 1250 MHz [2]
448 tCK = '0.8ns'
449
450 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
451 tBURST = '3.2ns'
452
453 # Values using DRAMSpec HMC model [1]
454 tRCD = '10.2ns'
455 tCL = '9.9ns'
456 tRP = '7.7ns'
457 tRAS = '21.6ns'
458
459 # tRRD depends on the power supply network for each vendor.
460 # We assume a tRRD of a double bank approach to be equal to 4 clock
461 # cycles (Assumption)
462 tRRD = '3.2ns'
463
464 # activation limit is set to 0 since there are only 2 banks per vault
465 # layer.
466 activation_limit = 0
467
468 # Values using DRAMSpec HMC model [1]
469 tRFC = '59ns'
470 tWR = '8ns'
471 tRTP = '4.9ns'
472
473 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
474 # 0.8 ns (Assumption)
475 tCS = '0.8ns'
476
477 # Value using DRAMSpec HMC model [1]
478 tREFI = '3.9us'
479
480 # The default page policy in the vault controllers is simple closed page
481 # [2] nevertheless 'close' policy opens and closes the row multiple times
482 # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
483 page_policy = 'close_adaptive'
484
485 # RoCoRaBaCh resembles the default address mapping in HMC
486 addr_mapping = 'RoCoRaBaCh'
487 min_writes_per_switch = 8
488
489 # These parameters do not directly correlate with buffer_size in real
490 # hardware. Nevertheless, their value has been tuned to achieve a
491 # bandwidth similar to the cycle-accurate model in [2]
492 write_buffer_size = 32
493 read_buffer_size = 32
494
495 # The static latency of the vault controllers is estimated to be smaller
496 # than a full DRAM channel controller
497 static_backend_latency='4ns'
498 static_frontend_latency='4ns'
499
500# A single DDR3-2133 x64 channel refining a selected subset of the
501# options for the DDR-1600 configuration, based on the same DDR3-1600
502# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
503# consistent across the two configurations.
504class DDR3_2133_8x8(DDR3_1600_8x8):
505 # 1066 MHz
506 tCK = '0.938ns'
507
508 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
509 tBURST = '3.752ns'
510
511 # DDR3-2133 14-14-14
512 tRCD = '13.09ns'
513 tCL = '13.09ns'
514 tRP = '13.09ns'
515 tRAS = '33ns'
516 tRRD = '5ns'
517 tXAW = '25ns'
518
519 # Current values from datasheet
520 IDD0 = '70mA'
521 IDD2N = '37mA'
522 IDD3N = '44mA'
523 IDD4W = '157mA'
524 IDD4R = '191mA'
525 IDD5 = '250mA'
526 IDD3P1 = '44mA'
527 IDD2P1 = '43mA'
528 IDD6 ='20mA'
529 VDD = '1.5V'
530
531# A single DDR4-2400 x64 channel (one command and address bus), with
532# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
533# in an 16x4 configuration.
534# Total channel capacity is 32GB
535# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
536class DDR4_2400_16x4(DRAMCtrl):
537 # size of device
538 device_size = '1GB'
539
540 # 16x4 configuration, 16 devices each with a 4-bit interface
541 device_bus_width = 4
542
543 # DDR4 is a BL8 device
544 burst_length = 8
545
546 # Each device has a page (row buffer) size of 512 byte (1K columns x4)
547 device_rowbuffer_size = '512B'
548
549 # 16x4 configuration, so 16 devices
550 devices_per_rank = 16
551
552 # Match our DDR3 configurations which is dual rank
553 ranks_per_channel = 2
554
555 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
556 # Set to 4 for x4 case
557 bank_groups_per_rank = 4
558
559 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
560 # configurations). Currently we do not capture the additional
561 # constraints incurred by the bank groups
562 banks_per_rank = 16
563
564 # override the default buffer sizes and go for something larger to
565 # accommodate the larger bank count
566 write_buffer_size = 128
567 read_buffer_size = 64
568
569 # 1200 MHz
570 tCK = '0.833ns'
571
572 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
573 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
574 # With bank group architectures, tBURST represents the CAS-to-CAS
575 # delay for bursts to different bank groups (tCCD_S)
576 tBURST = '3.332ns'
577
578 # @2400 data rate, tCCD_L is 6 CK
579 # CAS-to-CAS delay for bursts to the same bank group
580 # tBURST is equivalent to tCCD_S; no explicit parameter required
581 # for CAS-to-CAS delay for bursts to different bank groups
582 tCCD_L = '5ns';
583
584 # DDR4-2400 17-17-17
585 tRCD = '14.16ns'
586 tCL = '14.16ns'
587 tRP = '14.16ns'
588 tRAS = '32ns'
589
590 # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
591 tRRD = '3.332ns'
592
593 # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
594 tRRD_L = '4.9ns';
595
596 # tFAW for 512B page is MAX(16 CK, 13ns)
597 tXAW = '13.328ns'
598 activation_limit = 4
599 # tRFC is 350ns
600 tRFC = '350ns'
601
602 tWR = '15ns'
603
604 # Here using the average of WTR_S and WTR_L
605 tWTR = '5ns'
606
607 # Greater of 4 CK or 7.5 ns
608 tRTP = '7.5ns'
609
610 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
611 tRTW = '1.666ns'
612
613 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
614 tCS = '1.666ns'
615
616 # <=85C, half for >85C
617 tREFI = '7.8us'
618
619 # active powerdown and precharge powerdown exit time
620 tXP = '6ns'
621
622 # self refresh exit time
623 # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
624 # tRFC + 10ns = 340ns
625 tXS = '340ns'
626
627 # Current values from datasheet
628 IDD0 = '43mA'
629 IDD02 = '3mA'
630 IDD2N = '34mA'
631 IDD3N = '38mA'
632 IDD3N2 = '3mA'
633 IDD4W = '103mA'
634 IDD4R = '110mA'
635 IDD5 = '250mA'
636 IDD3P1 = '32mA'
637 IDD2P1 = '25mA'
638 IDD6 = '30mA'
639 VDD = '1.2V'
640 VDD2 = '2.5V'
641
642# A single DDR4-2400 x64 channel (one command and address bus), with
643# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
644# in an 8x8 configuration.
645# Total channel capacity is 16GB
646# 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
647class DDR4_2400_8x8(DDR4_2400_16x4):
648 # 8x8 configuration, 8 devices each with an 8-bit interface
649 device_bus_width = 8
650
651 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
652 device_rowbuffer_size = '1kB'
653
654 # 8x8 configuration, so 8 devices
655 devices_per_rank = 8
656
657 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
658 tRRD_L = '4.9ns';
659
660 tXAW = '21ns'
661
662 # Current values from datasheet
663 IDD0 = '48mA'
664 IDD3N = '43mA'
665 IDD4W = '123mA'
666 IDD4R = '135mA'
667 IDD3P1 = '37mA'
668
669# A single DDR4-2400 x64 channel (one command and address bus), with
670# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
671# in an 4x16 configuration.
672# Total channel capacity is 4GB
673# 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
674class DDR4_2400_4x16(DDR4_2400_16x4):
675 # 4x16 configuration, 4 devices each with an 16-bit interface
676 device_bus_width = 16
677
678 # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
679 device_rowbuffer_size = '2kB'
680
681 # 4x16 configuration, so 4 devices
682 devices_per_rank = 4
683
684 # Single rank for x16
685 ranks_per_channel = 1
686
687 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
688 # Set to 2 for x16 case
689 bank_groups_per_rank = 2
690
691 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
692 # configurations). Currently we do not capture the additional
693 # constraints incurred by the bank groups
694 banks_per_rank = 8
695
696 # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
697 tRRD = '5.3ns'
698
699 # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
700 tRRD_L = '6.4ns';
701
702 tXAW = '30ns'
703
704 # Current values from datasheet
705 IDD0 = '80mA'
706 IDD02 = '4mA'
707 IDD2N = '34mA'
708 IDD3N = '47mA'
709 IDD4W = '228mA'
710 IDD4R = '243mA'
711 IDD5 = '280mA'
712 IDD3P1 = '41mA'
713
714# A single LPDDR2-S4 x32 interface (one command/address bus), with
715# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
716# in a 1x32 configuration.
717class LPDDR2_S4_1066_1x32(DRAMCtrl):
718 # No DLL in LPDDR2
719 dll = False
720
721 # size of device
722 device_size = '512MB'
723
724 # 1x32 configuration, 1 device with a 32-bit interface
725 device_bus_width = 32
726
727 # LPDDR2_S4 is a BL4 and BL8 device
728 burst_length = 8
729
730 # Each device has a page (row buffer) size of 1KB
731 # (this depends on the memory density)
732 device_rowbuffer_size = '1kB'
733
734 # 1x32 configuration, so 1 device
735 devices_per_rank = 1
736
737 # Use a single rank
738 ranks_per_channel = 1
739
740 # LPDDR2-S4 has 8 banks in all configurations
741 banks_per_rank = 8
742
743 # 533 MHz
744 tCK = '1.876ns'
745
746 # Fixed at 15 ns
747 tRCD = '15ns'
748
749 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
750 tCL = '15ns'
751
752 # Pre-charge one bank 15 ns (all banks 18 ns)
753 tRP = '15ns'
754
755 tRAS = '42ns'
756 tWR = '15ns'
757
758 tRTP = '7.5ns'
759
760 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
761 # Note this is a BL8 DDR device.
762 # Requests larger than 32 bytes are broken down into multiple requests
763 # in the controller
764 tBURST = '7.5ns'
765
766 # LPDDR2-S4, 4 Gbit
767 tRFC = '130ns'
768 tREFI = '3.9us'
769
770 # active powerdown and precharge powerdown exit time
771 tXP = '7.5ns'
772
773 # self refresh exit time
774 tXS = '140ns'
775
776 # Irrespective of speed grade, tWTR is 7.5 ns
777 tWTR = '7.5ns'
778
779 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
780 tRTW = '3.75ns'
781
782 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
783 tCS = '3.75ns'
784
785 # Activate to activate irrespective of density and speed grade
786 tRRD = '10.0ns'
787
788 # Irrespective of density, tFAW is 50 ns
789 tXAW = '50ns'
790 activation_limit = 4
791
792 # Current values from datasheet
793 IDD0 = '15mA'
794 IDD02 = '70mA'
795 IDD2N = '2mA'
796 IDD2N2 = '30mA'
797 IDD3N = '2.5mA'
798 IDD3N2 = '30mA'
799 IDD4W = '10mA'
800 IDD4W2 = '190mA'
801 IDD4R = '3mA'
802 IDD4R2 = '220mA'
803 IDD5 = '40mA'
804 IDD52 = '150mA'
805 IDD3P1 = '1.2mA'
806 IDD3P12 = '8mA'
807 IDD2P1 = '0.6mA'
808 IDD2P12 = '0.8mA'
809 IDD6 = '1mA'
810 IDD62 = '3.2mA'
811 VDD = '1.8V'
812 VDD2 = '1.2V'
813
814# A single WideIO x128 interface (one command and address bus), with
815# default timings based on an estimated WIO-200 8 Gbit part.
816class WideIO_200_1x128(DRAMCtrl):
817 # No DLL for WideIO
818 dll = False
819
820 # size of device
821 device_size = '1024MB'
822
823 # 1x128 configuration, 1 device with a 128-bit interface
824 device_bus_width = 128
825
826 # This is a BL4 device
827 burst_length = 4
828
829 # Each device has a page (row buffer) size of 4KB
830 # (this depends on the memory density)
831 device_rowbuffer_size = '4kB'
832
833 # 1x128 configuration, so 1 device
834 devices_per_rank = 1
835
836 # Use one rank for a one-high die stack
837 ranks_per_channel = 1
838
839 # WideIO has 4 banks in all configurations
840 banks_per_rank = 4
841
842 # 200 MHz
843 tCK = '5ns'
844
845 # WIO-200
846 tRCD = '18ns'
847 tCL = '18ns'
848 tRP = '18ns'
849 tRAS = '42ns'
850 tWR = '15ns'
851 # Read to precharge is same as the burst
852 tRTP = '20ns'
853
854 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
855 # Note this is a BL4 SDR device.
856 tBURST = '20ns'
857
858 # WIO 8 Gb
859 tRFC = '210ns'
860
861 # WIO 8 Gb, <=85C, half for >85C
862 tREFI = '3.9us'
863
864 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
865 tWTR = '15ns'
866
867 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
868 tRTW = '10ns'
869
870 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
871 tCS = '10ns'
872
873 # Activate to activate irrespective of density and speed grade
874 tRRD = '10.0ns'
875
876 # Two instead of four activation window
877 tXAW = '50ns'
878 activation_limit = 2
879
880 # The WideIO specification does not provide current information
881
882# A single LPDDR3 x32 interface (one command/address bus), with
883# default timings based on a LPDDR3-1600 4 Gbit part (Micron
884# EDF8132A1MC) in a 1x32 configuration.
885class LPDDR3_1600_1x32(DRAMCtrl):
886 # No DLL for LPDDR3
887 dll = False
888
889 # size of device
890 device_size = '512MB'
891
892 # 1x32 configuration, 1 device with a 32-bit interface
893 device_bus_width = 32
894
895 # LPDDR3 is a BL8 device
896 burst_length = 8
897
898 # Each device has a page (row buffer) size of 4KB
899 device_rowbuffer_size = '4kB'
900
901 # 1x32 configuration, so 1 device
902 devices_per_rank = 1
903
904 # Technically the datasheet is a dual-rank package, but for
905 # comparison with the LPDDR2 config we stick to a single rank
906 ranks_per_channel = 1
907
908 # LPDDR3 has 8 banks in all configurations
909 banks_per_rank = 8
910
911 # 800 MHz
912 tCK = '1.25ns'
913
914 tRCD = '18ns'
915
916 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
917 tCL = '15ns'
918
919 tRAS = '42ns'
920 tWR = '15ns'
921
922 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
923 tRTP = '7.5ns'
924
925 # Pre-charge one bank 18 ns (all banks 21 ns)
926 tRP = '18ns'
927
928 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
929 # Note this is a BL8 DDR device.
930 # Requests larger than 32 bytes are broken down into multiple requests
931 # in the controller
932 tBURST = '5ns'
933
934 # LPDDR3, 4 Gb
935 tRFC = '130ns'
936 tREFI = '3.9us'
937
938 # active powerdown and precharge powerdown exit time
939 tXP = '7.5ns'
940
941 # self refresh exit time
942 tXS = '140ns'
943
944 # Irrespective of speed grade, tWTR is 7.5 ns
945 tWTR = '7.5ns'
946
947 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
948 tRTW = '2.5ns'
949
950 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
951 tCS = '2.5ns'
952
953 # Activate to activate irrespective of density and speed grade
954 tRRD = '10.0ns'
955
956 # Irrespective of size, tFAW is 50 ns
957 tXAW = '50ns'
958 activation_limit = 4
959
960 # Current values from datasheet
961 IDD0 = '8mA'
962 IDD02 = '60mA'
963 IDD2N = '0.8mA'
964 IDD2N2 = '26mA'
965 IDD3N = '2mA'
966 IDD3N2 = '34mA'
967 IDD4W = '2mA'
968 IDD4W2 = '190mA'
969 IDD4R = '2mA'
970 IDD4R2 = '230mA'
971 IDD5 = '28mA'
972 IDD52 = '150mA'
973 IDD3P1 = '1.4mA'
974 IDD3P12 = '11mA'
975 IDD2P1 = '0.8mA'
976 IDD2P12 = '1.8mA'
977 IDD6 = '0.5mA'
978 IDD62 = '1.8mA'
979 VDD = '1.8V'
980 VDD2 = '1.2V'
981
982# A single GDDR5 x64 interface, with
983# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
984# H5GQ1H24AFR) in a 2x32 configuration.
985class GDDR5_4000_2x32(DRAMCtrl):
986 # size of device
987 device_size = '128MB'
988
989 # 2x32 configuration, 1 device with a 32-bit interface
990 device_bus_width = 32
991
992 # GDDR5 is a BL8 device
993 burst_length = 8
994
995 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
996 device_rowbuffer_size = '256B'
997
998 # 2x32 configuration, so 2 devices
999 devices_per_rank = 2
1000
1001 # assume single rank
1002 ranks_per_channel = 1
1003
1004 # GDDR5 has 4 bank groups
1005 bank_groups_per_rank = 4
1006
1007 # GDDR5 has 16 banks with 4 bank groups
1008 banks_per_rank = 16
1009
1010 # 1000 MHz
1011 tCK = '1ns'
1012
1013 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
1014 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
1015 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
1016 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
1017 # With bank group architectures, tBURST represents the CAS-to-CAS
1018 # delay for bursts to different bank groups (tCCD_S)
1019 tBURST = '2ns'
1020
1021 # @1000MHz data rate, tCCD_L is 3 CK
1022 # CAS-to-CAS delay for bursts to the same bank group
1023 # tBURST is equivalent to tCCD_S; no explicit parameter required
1024 # for CAS-to-CAS delay for bursts to different bank groups
1025 tCCD_L = '3ns';
1026
1027 tRCD = '12ns'
1028
1029 # tCL is not directly found in datasheet and assumed equal tRCD
1030 tCL = '12ns'
1031
1032 tRP = '12ns'
1033 tRAS = '28ns'
1034
1035 # RRD_S (different bank group)
1036 # RRD_S is 5.5 ns in datasheet.
1037 # rounded to the next multiple of tCK
1038 tRRD = '6ns'
1039
1040 # RRD_L (same bank group)
1041 # RRD_L is 5.5 ns in datasheet.
1042 # rounded to the next multiple of tCK
1043 tRRD_L = '6ns'
1044
1045 tXAW = '23ns'
1046
1047 # tXAW < 4 x tRRD.
1048 # Therefore, activation limit is set to 0
1049 activation_limit = 0
1050
1051 tRFC = '65ns'
1052 tWR = '12ns'
1053
1054 # Here using the average of WTR_S and WTR_L
1055 tWTR = '5ns'
1056
1057 # Read-to-Precharge 2 CK
1058 tRTP = '2ns'
1059
1060 # Assume 2 cycles
1061 tRTW = '2ns'
1062
1063# A single HBM x128 interface (one command and address bus), with
1064# default timings based on data publically released
1065# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
1066# IDD measurement values, and by extrapolating data from other classes.
1067# Architecture values based on published HBM spec
1068# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
1069class HBM_1000_4H_1x128(DRAMCtrl):
1070 # HBM gen1 supports up to 8 128-bit physical channels
1071 # Configuration defines a single channel, with the capacity
1072 # set to (full_ stack_capacity / 8) based on 2Gb dies
1073 # To use all 8 channels, set 'channels' parameter to 8 in
1074 # system configuration
1075
1076 # 128-bit interface legacy mode
1077 device_bus_width = 128
1078
1079 # HBM supports BL4 and BL2 (legacy mode only)
1080 burst_length = 4
1081
1082 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
1083 # with 8 channels, 128MB per channel
1084 device_size = '128MB'
1085
1086 device_rowbuffer_size = '2kB'
1087
1088 # 1x128 configuration
1089 devices_per_rank = 1
1090
1091 # HBM does not have a CS pin; set rank to 1
1092 ranks_per_channel = 1
1093
1094 # HBM has 8 or 16 banks depending on capacity
1095 # 2Gb dies have 8 banks
1096 banks_per_rank = 8
1097
1098 # depending on frequency, bank groups may be required
1099 # will always have 4 bank groups when enabled
1100 # current specifications do not define the minimum frequency for
1101 # bank group architecture
1102 # setting bank_groups_per_rank to 0 to disable until range is defined
1103 bank_groups_per_rank = 0
1104
1105 # 500 MHz for 1Gbps DDR data rate
1106 tCK = '2ns'
1107
1108 # use values from IDD measurement in JEDEC spec
1109 # use tRP value for tRCD and tCL similar to other classes
1110 tRP = '15ns'
1111 tRCD = '15ns'
1112 tCL = '15ns'
1113 tRAS = '33ns'
1114
1115 # BL2 and BL4 supported, default to BL4
1116 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
1117 tBURST = '4ns'
1118
1119 # value for 2Gb device from JEDEC spec
1120 tRFC = '160ns'
1121
1122 # value for 2Gb device from JEDEC spec
1123 tREFI = '3.9us'
1124
1125 # extrapolate the following from LPDDR configs, using ns values
1126 # to minimize burst length, prefetch differences
1127 tWR = '18ns'
1128 tRTP = '7.5ns'
1129 tWTR = '10ns'
1130
1131 # start with 2 cycles turnaround, similar to other memory classes
1132 # could be more with variations across the stack
1133 tRTW = '4ns'
1134
1135 # single rank device, set to 0
1136 tCS = '0ns'
1137
1138 # from MemCon example, tRRD is 4ns with 2ns tCK
1139 tRRD = '4ns'
1140
1141 # from MemCon example, tFAW is 30ns with 2ns tCK
1142 tXAW = '30ns'
1143 activation_limit = 4
1144
1145 # 4tCK
1146 tXP = '8ns'
1147
1148 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1149 tXS = '168ns'
1150
1151# A single HBM x64 interface (one command and address bus), with
1152# default timings based on HBM gen1 and data publically released
1153# A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1154# Note: This defines a pseudo-channel with a unique controller
1155# instantiated per pseudo-channel
1156# Stay at same IO rate (1Gbps) to maintain timing relationship with
1157# HBM gen1 class (HBM_1000_4H_x128) where possible
1158class HBM_1000_4H_1x64(HBM_1000_4H_1x128):
1159 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1160 # Configuration defines a single pseudo channel, with the capacity
1161 # set to (full_ stack_capacity / 16) based on 8Gb dies
1162 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1163 # system configuration
1164
1165 # 64-bit pseudo-channle interface
1166 device_bus_width = 64
1167
1168 # HBM pseudo-channel only supports BL4
1169 burst_length = 4
1170
1171 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1172 # with 16 channels, 256MB per channel
1173 device_size = '256MB'
1174
1175 # page size is halved with pseudo-channel; maintaining the same same number
1176 # of rows per pseudo-channel with 2X banks across 2 channels
1177 device_rowbuffer_size = '1kB'
1178
1179 # HBM has 8 or 16 banks depending on capacity
1180 # Starting with 4Gb dies, 16 banks are defined
1181 banks_per_rank = 16
1182
1183 # reset tRFC for larger, 8Gb device
1184 # use HBM1 4Gb value as a starting point
1185 tRFC = '260ns'
1186
1187 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1188 tXS = '268ns'
1189 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1190 tCS = '2ns'
1191 tREFI = '3.9us'
1192
1193 # active powerdown and precharge powerdown exit time
1194 tXP = '10ns'
1195
1196 # self refresh exit time
1197 tXS = '65ns'
| 142 # For power modelling we need to know if the DRAM has a DLL or not
143 dll = Param.Bool(True, "DRAM has DLL or not")
144
145 # DRAMPower provides in addition to the core power, the possibility to
146 # include RD/WR termination and IO power. This calculation assumes some
147 # default values. The integration of DRAMPower with gem5 does not include
148 # IO and RD/WR termination power by default. This might be added as an
149 # additional feature in the future.
150
151 # timing behaviour and constraints - all in nanoseconds
152
153 # the base clock period of the DRAM
154 tCK = Param.Latency("Clock period")
155
156 # the amount of time in nanoseconds from issuing an activate command
157 # to the data being available in the row buffer for a read/write
158 tRCD = Param.Latency("RAS to CAS delay")
159
160 # the time from issuing a read/write command to seeing the actual data
161 tCL = Param.Latency("CAS latency")
162
163 # minimum time between a precharge and subsequent activate
164 tRP = Param.Latency("Row precharge time")
165
166 # minimum time between an activate and a precharge to the same row
167 tRAS = Param.Latency("ACT to PRE delay")
168
169 # minimum time between a write data transfer and a precharge
170 tWR = Param.Latency("Write recovery time")
171
172 # minimum time between a read and precharge command
173 tRTP = Param.Latency("Read to precharge")
174
175 # time to complete a burst transfer, typically the burst length
176 # divided by two due to the DDR bus, but by making it a parameter
177 # it is easier to also evaluate SDR memories like WideIO.
178 # This parameter has to account for burst length.
179 # Read/Write requests with data size larger than one full burst are broken
180 # down into multiple requests in the controller
181 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
182 # With bank group architectures, tBURST represents the CAS-to-CAS
183 # delay for bursts to different bank groups (tCCD_S)
184 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
185
186 # CAS-to-CAS delay for bursts to the same bank group
187 # only utilized with bank group architectures; set to 0 for default case
188 # tBURST is equivalent to tCCD_S; no explicit parameter required
189 # for CAS-to-CAS delay for bursts to different bank groups
190 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
191
192 # Write-to-Write delay for bursts to the same bank group
193 # only utilized with bank group architectures; set to 0 for default case
194 # This will be used to enable different same bank group delays
195 # for writes versus reads
196 tCCD_L_WR = Param.Latency(Self.tCCD_L,
197 "Same bank group Write to Write delay")
198
199 # time taken to complete one refresh cycle (N rows in all banks)
200 tRFC = Param.Latency("Refresh cycle time")
201
202 # refresh command interval, how often a "ref" command needs
203 # to be sent. It is 7.8 us for a 64ms refresh requirement
204 tREFI = Param.Latency("Refresh command interval")
205
206 # write-to-read, same rank turnaround penalty
207 tWTR = Param.Latency("Write to read, same rank switching time")
208
209 # read-to-write, same rank turnaround penalty
210 tRTW = Param.Latency("Read to write, same rank switching time")
211
212 # rank-to-rank bus delay penalty
213 # this does not correlate to a memory timing parameter and encompasses:
214 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
215 # different rank bus delay
216 tCS = Param.Latency("Rank to rank switching time")
217
218 # minimum row activate to row activate delay time
219 tRRD = Param.Latency("ACT to ACT delay")
220
221 # only utilized with bank group architectures; set to 0 for default case
222 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
223
224 # time window in which a maximum number of activates are allowed
225 # to take place, set to 0 to disable
226 tXAW = Param.Latency("X activation window")
227 activation_limit = Param.Unsigned("Max number of activates in window")
228
229 # time to exit power-down mode
230 # Exit power-down to next valid command delay
231 tXP = Param.Latency("0ns", "Power-up Delay")
232
233 # Exit Powerdown to commands requiring a locked DLL
234 tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
235
236 # time to exit self-refresh mode
237 tXS = Param.Latency("0ns", "Self-refresh exit latency")
238
239 # time to exit self-refresh mode with locked DLL
240 tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
241
242 # Currently rolled into other params
243 ######################################################################
244
245 # tRC - assumed to be tRAS + tRP
246
247 # Power Behaviour and Constraints
248 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
249 # defined as VDD and VDD2. Each current is defined for each voltage domain
250 # separately. For example, current IDD0 is active-precharge current for
251 # voltage domain VDD and current IDD02 is active-precharge current for
252 # voltage domain VDD2.
253 # By default all currents are set to 0mA. Users who are only interested in
254 # the performance of DRAMs can leave them at 0.
255
256 # Operating 1 Bank Active-Precharge current
257 IDD0 = Param.Current("0mA", "Active precharge current")
258
259 # Operating 1 Bank Active-Precharge current multiple voltage Range
260 IDD02 = Param.Current("0mA", "Active precharge current VDD2")
261
262 # Precharge Power-down Current: Slow exit
263 IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
264
265 # Precharge Power-down Current: Slow exit multiple voltage Range
266 IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
267
268 # Precharge Power-down Current: Fast exit
269 IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
270
271 # Precharge Power-down Current: Fast exit multiple voltage Range
272 IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
273
274 # Precharge Standby current
275 IDD2N = Param.Current("0mA", "Precharge Standby current")
276
277 # Precharge Standby current multiple voltage range
278 IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
279
280 # Active Power-down current: slow exit
281 IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
282
283 # Active Power-down current: slow exit multiple voltage range
284 IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
285
286 # Active Power-down current : fast exit
287 IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
288
289 # Active Power-down current : fast exit multiple voltage range
290 IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
291
292 # Active Standby current
293 IDD3N = Param.Current("0mA", "Active Standby current")
294
295 # Active Standby current multiple voltage range
296 IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
297
298 # Burst Read Operating Current
299 IDD4R = Param.Current("0mA", "READ current")
300
301 # Burst Read Operating Current multiple voltage range
302 IDD4R2 = Param.Current("0mA", "READ current VDD2")
303
304 # Burst Write Operating Current
305 IDD4W = Param.Current("0mA", "WRITE current")
306
307 # Burst Write Operating Current multiple voltage range
308 IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
309
310 # Refresh Current
311 IDD5 = Param.Current("0mA", "Refresh current")
312
313 # Refresh Current multiple voltage range
314 IDD52 = Param.Current("0mA", "Refresh current VDD2")
315
316 # Self-Refresh Current
317 IDD6 = Param.Current("0mA", "Self-refresh Current")
318
319 # Self-Refresh Current multiple voltage range
320 IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
321
322 # Main voltage range of the DRAM
323 VDD = Param.Voltage("0V", "Main Voltage Range")
324
325 # Second voltage range defined by some DRAMs
326 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
327
328# A single DDR3-1600 x64 channel (one command and address bus), with
329# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
330# an 8x8 configuration.
331class DDR3_1600_8x8(DRAMCtrl):
332 # size of device in bytes
333 device_size = '512MB'
334
335 # 8x8 configuration, 8 devices each with an 8-bit interface
336 device_bus_width = 8
337
338 # DDR3 is a BL8 device
339 burst_length = 8
340
341 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
342 device_rowbuffer_size = '1kB'
343
344 # 8x8 configuration, so 8 devices
345 devices_per_rank = 8
346
347 # Use two ranks
348 ranks_per_channel = 2
349
350 # DDR3 has 8 banks in all configurations
351 banks_per_rank = 8
352
353 # 800 MHz
354 tCK = '1.25ns'
355
356 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
357 tBURST = '5ns'
358
359 # DDR3-1600 11-11-11
360 tRCD = '13.75ns'
361 tCL = '13.75ns'
362 tRP = '13.75ns'
363 tRAS = '35ns'
364 tRRD = '6ns'
365 tXAW = '30ns'
366 activation_limit = 4
367 tRFC = '260ns'
368
369 tWR = '15ns'
370
371 # Greater of 4 CK or 7.5 ns
372 tWTR = '7.5ns'
373
374 # Greater of 4 CK or 7.5 ns
375 tRTP = '7.5ns'
376
377 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
378 tRTW = '2.5ns'
379
380 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
381 tCS = '2.5ns'
382
383 # <=85C, half for >85C
384 tREFI = '7.8us'
385
386 # active powerdown and precharge powerdown exit time
387 tXP = '6ns'
388
389 # self refresh exit time
390 tXS = '270ns'
391
392 # Current values from datasheet Die Rev E,J
393 IDD0 = '55mA'
394 IDD2N = '32mA'
395 IDD3N = '38mA'
396 IDD4W = '125mA'
397 IDD4R = '157mA'
398 IDD5 = '235mA'
399 IDD3P1 = '38mA'
400 IDD2P1 = '32mA'
401 IDD6 = '20mA'
402 VDD = '1.5V'
403
404# A single HMC-2500 x32 model based on:
405# [1] DRAMSpec: a high-level DRAM bank modelling tool
406# developed at the University of Kaiserslautern. This high level tool
407# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
408# estimate the DRAM bank latency and power numbers.
409# [2] High performance AXI-4.0 based interconnect for extensible smart memory
410# cubes (E. Azarkhish et. al)
411# Assumed for the HMC model is a 30 nm technology node.
412# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
413# layers).
414# Each layer has 16 vaults and each vault consists of 2 banks per layer.
415# In order to be able to use the same controller used for 2D DRAM generations
416# for HMC, the following analogy is done:
417# Channel (DDR) => Vault (HMC)
418# device_size (DDR) => size of a single layer in a vault
419# ranks per channel (DDR) => number of layers
420# banks per rank (DDR) => banks per layer
421# devices per rank (DDR) => devices per layer ( 1 for HMC).
422# The parameters for which no input is available are inherited from the DDR3
423# configuration.
424# This configuration includes the latencies from the DRAM to the logic layer
425# of the HMC
426class HMC_2500_1x32(DDR3_1600_8x8):
427 # size of device
428 # two banks per device with each bank 4MB [2]
429 device_size = '8MB'
430
431 # 1x32 configuration, 1 device with 32 TSVs [2]
432 device_bus_width = 32
433
434 # HMC is a BL8 device [2]
435 burst_length = 8
436
437 # Each device has a page (row buffer) size of 256 bytes [2]
438 device_rowbuffer_size = '256B'
439
440 # 1x32 configuration, so 1 device [2]
441 devices_per_rank = 1
442
443 # 4 layers so 4 ranks [2]
444 ranks_per_channel = 4
445
446 # HMC has 2 banks per layer [2]
447 # Each layer represents a rank. With 4 layers and 8 banks in total, each
448 # layer has 2 banks; thus 2 banks per rank.
449 banks_per_rank = 2
450
451 # 1250 MHz [2]
452 tCK = '0.8ns'
453
454 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
455 tBURST = '3.2ns'
456
457 # Values using DRAMSpec HMC model [1]
458 tRCD = '10.2ns'
459 tCL = '9.9ns'
460 tRP = '7.7ns'
461 tRAS = '21.6ns'
462
463 # tRRD depends on the power supply network for each vendor.
464 # We assume a tRRD of a double bank approach to be equal to 4 clock
465 # cycles (Assumption)
466 tRRD = '3.2ns'
467
468 # activation limit is set to 0 since there are only 2 banks per vault
469 # layer.
470 activation_limit = 0
471
472 # Values using DRAMSpec HMC model [1]
473 tRFC = '59ns'
474 tWR = '8ns'
475 tRTP = '4.9ns'
476
477 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
478 # 0.8 ns (Assumption)
479 tCS = '0.8ns'
480
481 # Value using DRAMSpec HMC model [1]
482 tREFI = '3.9us'
483
484 # The default page policy in the vault controllers is simple closed page
485 # [2] nevertheless 'close' policy opens and closes the row multiple times
486 # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
487 page_policy = 'close_adaptive'
488
489 # RoCoRaBaCh resembles the default address mapping in HMC
490 addr_mapping = 'RoCoRaBaCh'
491 min_writes_per_switch = 8
492
493 # These parameters do not directly correlate with buffer_size in real
494 # hardware. Nevertheless, their value has been tuned to achieve a
495 # bandwidth similar to the cycle-accurate model in [2]
496 write_buffer_size = 32
497 read_buffer_size = 32
498
499 # The static latency of the vault controllers is estimated to be smaller
500 # than a full DRAM channel controller
501 static_backend_latency='4ns'
502 static_frontend_latency='4ns'
503
504# A single DDR3-2133 x64 channel refining a selected subset of the
505# options for the DDR-1600 configuration, based on the same DDR3-1600
506# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
507# consistent across the two configurations.
508class DDR3_2133_8x8(DDR3_1600_8x8):
509 # 1066 MHz
510 tCK = '0.938ns'
511
512 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
513 tBURST = '3.752ns'
514
515 # DDR3-2133 14-14-14
516 tRCD = '13.09ns'
517 tCL = '13.09ns'
518 tRP = '13.09ns'
519 tRAS = '33ns'
520 tRRD = '5ns'
521 tXAW = '25ns'
522
523 # Current values from datasheet
524 IDD0 = '70mA'
525 IDD2N = '37mA'
526 IDD3N = '44mA'
527 IDD4W = '157mA'
528 IDD4R = '191mA'
529 IDD5 = '250mA'
530 IDD3P1 = '44mA'
531 IDD2P1 = '43mA'
532 IDD6 ='20mA'
533 VDD = '1.5V'
534
535# A single DDR4-2400 x64 channel (one command and address bus), with
536# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
537# in an 16x4 configuration.
538# Total channel capacity is 32GB
539# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
540class DDR4_2400_16x4(DRAMCtrl):
541 # size of device
542 device_size = '1GB'
543
544 # 16x4 configuration, 16 devices each with a 4-bit interface
545 device_bus_width = 4
546
547 # DDR4 is a BL8 device
548 burst_length = 8
549
550 # Each device has a page (row buffer) size of 512 byte (1K columns x4)
551 device_rowbuffer_size = '512B'
552
553 # 16x4 configuration, so 16 devices
554 devices_per_rank = 16
555
556 # Match our DDR3 configurations which is dual rank
557 ranks_per_channel = 2
558
559 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
560 # Set to 4 for x4 case
561 bank_groups_per_rank = 4
562
563 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
564 # configurations). Currently we do not capture the additional
565 # constraints incurred by the bank groups
566 banks_per_rank = 16
567
568 # override the default buffer sizes and go for something larger to
569 # accommodate the larger bank count
570 write_buffer_size = 128
571 read_buffer_size = 64
572
573 # 1200 MHz
574 tCK = '0.833ns'
575
576 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
577 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
578 # With bank group architectures, tBURST represents the CAS-to-CAS
579 # delay for bursts to different bank groups (tCCD_S)
580 tBURST = '3.332ns'
581
582 # @2400 data rate, tCCD_L is 6 CK
583 # CAS-to-CAS delay for bursts to the same bank group
584 # tBURST is equivalent to tCCD_S; no explicit parameter required
585 # for CAS-to-CAS delay for bursts to different bank groups
586 tCCD_L = '5ns';
587
588 # DDR4-2400 17-17-17
589 tRCD = '14.16ns'
590 tCL = '14.16ns'
591 tRP = '14.16ns'
592 tRAS = '32ns'
593
594 # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
595 tRRD = '3.332ns'
596
597 # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
598 tRRD_L = '4.9ns';
599
600 # tFAW for 512B page is MAX(16 CK, 13ns)
601 tXAW = '13.328ns'
602 activation_limit = 4
603 # tRFC is 350ns
604 tRFC = '350ns'
605
606 tWR = '15ns'
607
608 # Here using the average of WTR_S and WTR_L
609 tWTR = '5ns'
610
611 # Greater of 4 CK or 7.5 ns
612 tRTP = '7.5ns'
613
614 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
615 tRTW = '1.666ns'
616
617 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
618 tCS = '1.666ns'
619
620 # <=85C, half for >85C
621 tREFI = '7.8us'
622
623 # active powerdown and precharge powerdown exit time
624 tXP = '6ns'
625
626 # self refresh exit time
627 # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
628 # tRFC + 10ns = 340ns
629 tXS = '340ns'
630
631 # Current values from datasheet
632 IDD0 = '43mA'
633 IDD02 = '3mA'
634 IDD2N = '34mA'
635 IDD3N = '38mA'
636 IDD3N2 = '3mA'
637 IDD4W = '103mA'
638 IDD4R = '110mA'
639 IDD5 = '250mA'
640 IDD3P1 = '32mA'
641 IDD2P1 = '25mA'
642 IDD6 = '30mA'
643 VDD = '1.2V'
644 VDD2 = '2.5V'
645
646# A single DDR4-2400 x64 channel (one command and address bus), with
647# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
648# in an 8x8 configuration.
649# Total channel capacity is 16GB
650# 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
651class DDR4_2400_8x8(DDR4_2400_16x4):
652 # 8x8 configuration, 8 devices each with an 8-bit interface
653 device_bus_width = 8
654
655 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
656 device_rowbuffer_size = '1kB'
657
658 # 8x8 configuration, so 8 devices
659 devices_per_rank = 8
660
661 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
662 tRRD_L = '4.9ns';
663
664 tXAW = '21ns'
665
666 # Current values from datasheet
667 IDD0 = '48mA'
668 IDD3N = '43mA'
669 IDD4W = '123mA'
670 IDD4R = '135mA'
671 IDD3P1 = '37mA'
672
673# A single DDR4-2400 x64 channel (one command and address bus), with
674# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
675# in an 4x16 configuration.
676# Total channel capacity is 4GB
677# 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
678class DDR4_2400_4x16(DDR4_2400_16x4):
679 # 4x16 configuration, 4 devices each with an 16-bit interface
680 device_bus_width = 16
681
682 # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
683 device_rowbuffer_size = '2kB'
684
685 # 4x16 configuration, so 4 devices
686 devices_per_rank = 4
687
688 # Single rank for x16
689 ranks_per_channel = 1
690
691 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
692 # Set to 2 for x16 case
693 bank_groups_per_rank = 2
694
695 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
696 # configurations). Currently we do not capture the additional
697 # constraints incurred by the bank groups
698 banks_per_rank = 8
699
700 # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
701 tRRD = '5.3ns'
702
703 # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
704 tRRD_L = '6.4ns';
705
706 tXAW = '30ns'
707
708 # Current values from datasheet
709 IDD0 = '80mA'
710 IDD02 = '4mA'
711 IDD2N = '34mA'
712 IDD3N = '47mA'
713 IDD4W = '228mA'
714 IDD4R = '243mA'
715 IDD5 = '280mA'
716 IDD3P1 = '41mA'
717
718# A single LPDDR2-S4 x32 interface (one command/address bus), with
719# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
720# in a 1x32 configuration.
721class LPDDR2_S4_1066_1x32(DRAMCtrl):
722 # No DLL in LPDDR2
723 dll = False
724
725 # size of device
726 device_size = '512MB'
727
728 # 1x32 configuration, 1 device with a 32-bit interface
729 device_bus_width = 32
730
731 # LPDDR2_S4 is a BL4 and BL8 device
732 burst_length = 8
733
734 # Each device has a page (row buffer) size of 1KB
735 # (this depends on the memory density)
736 device_rowbuffer_size = '1kB'
737
738 # 1x32 configuration, so 1 device
739 devices_per_rank = 1
740
741 # Use a single rank
742 ranks_per_channel = 1
743
744 # LPDDR2-S4 has 8 banks in all configurations
745 banks_per_rank = 8
746
747 # 533 MHz
748 tCK = '1.876ns'
749
750 # Fixed at 15 ns
751 tRCD = '15ns'
752
753 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
754 tCL = '15ns'
755
756 # Pre-charge one bank 15 ns (all banks 18 ns)
757 tRP = '15ns'
758
759 tRAS = '42ns'
760 tWR = '15ns'
761
762 tRTP = '7.5ns'
763
764 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
765 # Note this is a BL8 DDR device.
766 # Requests larger than 32 bytes are broken down into multiple requests
767 # in the controller
768 tBURST = '7.5ns'
769
770 # LPDDR2-S4, 4 Gbit
771 tRFC = '130ns'
772 tREFI = '3.9us'
773
774 # active powerdown and precharge powerdown exit time
775 tXP = '7.5ns'
776
777 # self refresh exit time
778 tXS = '140ns'
779
780 # Irrespective of speed grade, tWTR is 7.5 ns
781 tWTR = '7.5ns'
782
783 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
784 tRTW = '3.75ns'
785
786 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
787 tCS = '3.75ns'
788
789 # Activate to activate irrespective of density and speed grade
790 tRRD = '10.0ns'
791
792 # Irrespective of density, tFAW is 50 ns
793 tXAW = '50ns'
794 activation_limit = 4
795
796 # Current values from datasheet
797 IDD0 = '15mA'
798 IDD02 = '70mA'
799 IDD2N = '2mA'
800 IDD2N2 = '30mA'
801 IDD3N = '2.5mA'
802 IDD3N2 = '30mA'
803 IDD4W = '10mA'
804 IDD4W2 = '190mA'
805 IDD4R = '3mA'
806 IDD4R2 = '220mA'
807 IDD5 = '40mA'
808 IDD52 = '150mA'
809 IDD3P1 = '1.2mA'
810 IDD3P12 = '8mA'
811 IDD2P1 = '0.6mA'
812 IDD2P12 = '0.8mA'
813 IDD6 = '1mA'
814 IDD62 = '3.2mA'
815 VDD = '1.8V'
816 VDD2 = '1.2V'
817
818# A single WideIO x128 interface (one command and address bus), with
819# default timings based on an estimated WIO-200 8 Gbit part.
820class WideIO_200_1x128(DRAMCtrl):
821 # No DLL for WideIO
822 dll = False
823
824 # size of device
825 device_size = '1024MB'
826
827 # 1x128 configuration, 1 device with a 128-bit interface
828 device_bus_width = 128
829
830 # This is a BL4 device
831 burst_length = 4
832
833 # Each device has a page (row buffer) size of 4KB
834 # (this depends on the memory density)
835 device_rowbuffer_size = '4kB'
836
837 # 1x128 configuration, so 1 device
838 devices_per_rank = 1
839
840 # Use one rank for a one-high die stack
841 ranks_per_channel = 1
842
843 # WideIO has 4 banks in all configurations
844 banks_per_rank = 4
845
846 # 200 MHz
847 tCK = '5ns'
848
849 # WIO-200
850 tRCD = '18ns'
851 tCL = '18ns'
852 tRP = '18ns'
853 tRAS = '42ns'
854 tWR = '15ns'
855 # Read to precharge is same as the burst
856 tRTP = '20ns'
857
858 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
859 # Note this is a BL4 SDR device.
860 tBURST = '20ns'
861
862 # WIO 8 Gb
863 tRFC = '210ns'
864
865 # WIO 8 Gb, <=85C, half for >85C
866 tREFI = '3.9us'
867
868 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
869 tWTR = '15ns'
870
871 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
872 tRTW = '10ns'
873
874 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
875 tCS = '10ns'
876
877 # Activate to activate irrespective of density and speed grade
878 tRRD = '10.0ns'
879
880 # Two instead of four activation window
881 tXAW = '50ns'
882 activation_limit = 2
883
884 # The WideIO specification does not provide current information
885
886# A single LPDDR3 x32 interface (one command/address bus), with
887# default timings based on a LPDDR3-1600 4 Gbit part (Micron
888# EDF8132A1MC) in a 1x32 configuration.
889class LPDDR3_1600_1x32(DRAMCtrl):
890 # No DLL for LPDDR3
891 dll = False
892
893 # size of device
894 device_size = '512MB'
895
896 # 1x32 configuration, 1 device with a 32-bit interface
897 device_bus_width = 32
898
899 # LPDDR3 is a BL8 device
900 burst_length = 8
901
902 # Each device has a page (row buffer) size of 4KB
903 device_rowbuffer_size = '4kB'
904
905 # 1x32 configuration, so 1 device
906 devices_per_rank = 1
907
908 # Technically the datasheet is a dual-rank package, but for
909 # comparison with the LPDDR2 config we stick to a single rank
910 ranks_per_channel = 1
911
912 # LPDDR3 has 8 banks in all configurations
913 banks_per_rank = 8
914
915 # 800 MHz
916 tCK = '1.25ns'
917
918 tRCD = '18ns'
919
920 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
921 tCL = '15ns'
922
923 tRAS = '42ns'
924 tWR = '15ns'
925
926 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
927 tRTP = '7.5ns'
928
929 # Pre-charge one bank 18 ns (all banks 21 ns)
930 tRP = '18ns'
931
932 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
933 # Note this is a BL8 DDR device.
934 # Requests larger than 32 bytes are broken down into multiple requests
935 # in the controller
936 tBURST = '5ns'
937
938 # LPDDR3, 4 Gb
939 tRFC = '130ns'
940 tREFI = '3.9us'
941
942 # active powerdown and precharge powerdown exit time
943 tXP = '7.5ns'
944
945 # self refresh exit time
946 tXS = '140ns'
947
948 # Irrespective of speed grade, tWTR is 7.5 ns
949 tWTR = '7.5ns'
950
951 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
952 tRTW = '2.5ns'
953
954 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
955 tCS = '2.5ns'
956
957 # Activate to activate irrespective of density and speed grade
958 tRRD = '10.0ns'
959
960 # Irrespective of size, tFAW is 50 ns
961 tXAW = '50ns'
962 activation_limit = 4
963
964 # Current values from datasheet
965 IDD0 = '8mA'
966 IDD02 = '60mA'
967 IDD2N = '0.8mA'
968 IDD2N2 = '26mA'
969 IDD3N = '2mA'
970 IDD3N2 = '34mA'
971 IDD4W = '2mA'
972 IDD4W2 = '190mA'
973 IDD4R = '2mA'
974 IDD4R2 = '230mA'
975 IDD5 = '28mA'
976 IDD52 = '150mA'
977 IDD3P1 = '1.4mA'
978 IDD3P12 = '11mA'
979 IDD2P1 = '0.8mA'
980 IDD2P12 = '1.8mA'
981 IDD6 = '0.5mA'
982 IDD62 = '1.8mA'
983 VDD = '1.8V'
984 VDD2 = '1.2V'
985
986# A single GDDR5 x64 interface, with
987# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
988# H5GQ1H24AFR) in a 2x32 configuration.
989class GDDR5_4000_2x32(DRAMCtrl):
990 # size of device
991 device_size = '128MB'
992
993 # 2x32 configuration, 1 device with a 32-bit interface
994 device_bus_width = 32
995
996 # GDDR5 is a BL8 device
997 burst_length = 8
998
999 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
1000 device_rowbuffer_size = '256B'
1001
1002 # 2x32 configuration, so 2 devices
1003 devices_per_rank = 2
1004
1005 # assume single rank
1006 ranks_per_channel = 1
1007
1008 # GDDR5 has 4 bank groups
1009 bank_groups_per_rank = 4
1010
1011 # GDDR5 has 16 banks with 4 bank groups
1012 banks_per_rank = 16
1013
1014 # 1000 MHz
1015 tCK = '1ns'
1016
1017 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
1018 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
1019 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
1020 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
1021 # With bank group architectures, tBURST represents the CAS-to-CAS
1022 # delay for bursts to different bank groups (tCCD_S)
1023 tBURST = '2ns'
1024
1025 # @1000MHz data rate, tCCD_L is 3 CK
1026 # CAS-to-CAS delay for bursts to the same bank group
1027 # tBURST is equivalent to tCCD_S; no explicit parameter required
1028 # for CAS-to-CAS delay for bursts to different bank groups
1029 tCCD_L = '3ns';
1030
1031 tRCD = '12ns'
1032
1033 # tCL is not directly found in datasheet and assumed equal tRCD
1034 tCL = '12ns'
1035
1036 tRP = '12ns'
1037 tRAS = '28ns'
1038
1039 # RRD_S (different bank group)
1040 # RRD_S is 5.5 ns in datasheet.
1041 # rounded to the next multiple of tCK
1042 tRRD = '6ns'
1043
1044 # RRD_L (same bank group)
1045 # RRD_L is 5.5 ns in datasheet.
1046 # rounded to the next multiple of tCK
1047 tRRD_L = '6ns'
1048
1049 tXAW = '23ns'
1050
1051 # tXAW < 4 x tRRD.
1052 # Therefore, activation limit is set to 0
1053 activation_limit = 0
1054
1055 tRFC = '65ns'
1056 tWR = '12ns'
1057
1058 # Here using the average of WTR_S and WTR_L
1059 tWTR = '5ns'
1060
1061 # Read-to-Precharge 2 CK
1062 tRTP = '2ns'
1063
1064 # Assume 2 cycles
1065 tRTW = '2ns'
1066
1067# A single HBM x128 interface (one command and address bus), with
1068# default timings based on data publically released
1069# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
1070# IDD measurement values, and by extrapolating data from other classes.
1071# Architecture values based on published HBM spec
1072# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
1073class HBM_1000_4H_1x128(DRAMCtrl):
1074 # HBM gen1 supports up to 8 128-bit physical channels
1075 # Configuration defines a single channel, with the capacity
1076 # set to (full_ stack_capacity / 8) based on 2Gb dies
1077 # To use all 8 channels, set 'channels' parameter to 8 in
1078 # system configuration
1079
1080 # 128-bit interface legacy mode
1081 device_bus_width = 128
1082
1083 # HBM supports BL4 and BL2 (legacy mode only)
1084 burst_length = 4
1085
1086 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
1087 # with 8 channels, 128MB per channel
1088 device_size = '128MB'
1089
1090 device_rowbuffer_size = '2kB'
1091
1092 # 1x128 configuration
1093 devices_per_rank = 1
1094
1095 # HBM does not have a CS pin; set rank to 1
1096 ranks_per_channel = 1
1097
1098 # HBM has 8 or 16 banks depending on capacity
1099 # 2Gb dies have 8 banks
1100 banks_per_rank = 8
1101
1102 # depending on frequency, bank groups may be required
1103 # will always have 4 bank groups when enabled
1104 # current specifications do not define the minimum frequency for
1105 # bank group architecture
1106 # setting bank_groups_per_rank to 0 to disable until range is defined
1107 bank_groups_per_rank = 0
1108
1109 # 500 MHz for 1Gbps DDR data rate
1110 tCK = '2ns'
1111
1112 # use values from IDD measurement in JEDEC spec
1113 # use tRP value for tRCD and tCL similar to other classes
1114 tRP = '15ns'
1115 tRCD = '15ns'
1116 tCL = '15ns'
1117 tRAS = '33ns'
1118
1119 # BL2 and BL4 supported, default to BL4
1120 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
1121 tBURST = '4ns'
1122
1123 # value for 2Gb device from JEDEC spec
1124 tRFC = '160ns'
1125
1126 # value for 2Gb device from JEDEC spec
1127 tREFI = '3.9us'
1128
1129 # extrapolate the following from LPDDR configs, using ns values
1130 # to minimize burst length, prefetch differences
1131 tWR = '18ns'
1132 tRTP = '7.5ns'
1133 tWTR = '10ns'
1134
1135 # start with 2 cycles turnaround, similar to other memory classes
1136 # could be more with variations across the stack
1137 tRTW = '4ns'
1138
1139 # single rank device, set to 0
1140 tCS = '0ns'
1141
1142 # from MemCon example, tRRD is 4ns with 2ns tCK
1143 tRRD = '4ns'
1144
1145 # from MemCon example, tFAW is 30ns with 2ns tCK
1146 tXAW = '30ns'
1147 activation_limit = 4
1148
1149 # 4tCK
1150 tXP = '8ns'
1151
1152 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1153 tXS = '168ns'
1154
1155# A single HBM x64 interface (one command and address bus), with
1156# default timings based on HBM gen1 and data publically released
1157# A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1158# Note: This defines a pseudo-channel with a unique controller
1159# instantiated per pseudo-channel
1160# Stay at same IO rate (1Gbps) to maintain timing relationship with
1161# HBM gen1 class (HBM_1000_4H_x128) where possible
1162class HBM_1000_4H_1x64(HBM_1000_4H_1x128):
1163 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1164 # Configuration defines a single pseudo channel, with the capacity
1165 # set to (full_ stack_capacity / 16) based on 8Gb dies
1166 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1167 # system configuration
1168
1169 # 64-bit pseudo-channle interface
1170 device_bus_width = 64
1171
1172 # HBM pseudo-channel only supports BL4
1173 burst_length = 4
1174
1175 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1176 # with 16 channels, 256MB per channel
1177 device_size = '256MB'
1178
1179 # page size is halved with pseudo-channel; maintaining the same same number
1180 # of rows per pseudo-channel with 2X banks across 2 channels
1181 device_rowbuffer_size = '1kB'
1182
1183 # HBM has 8 or 16 banks depending on capacity
1184 # Starting with 4Gb dies, 16 banks are defined
1185 banks_per_rank = 16
1186
1187 # reset tRFC for larger, 8Gb device
1188 # use HBM1 4Gb value as a starting point
1189 tRFC = '260ns'
1190
1191 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1192 tXS = '268ns'
1193 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1194 tCS = '2ns'
1195 tREFI = '3.9us'
1196
1197 # active powerdown and precharge powerdown exit time
1198 tXP = '10ns'
1199
1200 # self refresh exit time
1201 tXS = '65ns'
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