73 type = 'DRAMCtrl'
74 cxx_header = "mem/dram_ctrl.hh"
75
76 # single-ported on the system interface side, instantiate with a
77 # bus in front of the controller for multiple ports
78 port = SlavePort("Slave port")
79
80 # the basic configuration of the controller architecture, note
81 # that each entry corresponds to a burst for the specific DRAM
82 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
83 # the cacheline size or request/packet size
84 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
85 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
86
87 # threshold in percent for when to forcefully trigger writes and
88 # start emptying the write buffer
89 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
90
91 # threshold in percentage for when to start writes if the read
92 # queue is empty
93 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
94
95 # minimum write bursts to schedule before switching back to reads
96 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
97 "switching to reads")
98
99 # scheduler, address map and page policy
100 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
101 addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
102 page_policy = Param.PageManage('open_adaptive', "Page management policy")
103
104 # enforce a limit on the number of accesses per row
105 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
106 "closing");
107
108 # size of DRAM Chip in Bytes
109 device_size = Param.MemorySize("Size of DRAM chip")
110
111 # pipeline latency of the controller and PHY, split into a
112 # frontend part and a backend part, with reads and writes serviced
113 # by the queues only seeing the frontend contribution, and reads
114 # serviced by the memory seeing the sum of the two
115 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
116 static_backend_latency = Param.Latency("10ns", "Static backend latency")
117
118 # the physical organisation of the DRAM
119 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
120 "device/chip")
121 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
122 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
123 "device/chip")
124 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
125 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
126
127 # default to 0 bank groups per rank, indicating bank group architecture
128 # is not used
129 # update per memory class when bank group architecture is supported
130 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
131 banks_per_rank = Param.Unsigned("Number of banks per rank")
132 # only used for the address mapping as the controller by
133 # construction is a single channel and multiple controllers have
134 # to be instantiated for a multi-channel configuration
135 channels = Param.Unsigned(1, "Number of channels")
136
137 # For power modelling we need to know if the DRAM has a DLL or not
138 dll = Param.Bool(True, "DRAM has DLL or not")
139
140 # DRAMPower provides in addition to the core power, the possibility to
141 # include RD/WR termination and IO power. This calculation assumes some
142 # default values. The integration of DRAMPower with gem5 does not include
143 # IO and RD/WR termination power by default. This might be added as an
144 # additional feature in the future.
145
146 # timing behaviour and constraints - all in nanoseconds
147
148 # the base clock period of the DRAM
149 tCK = Param.Latency("Clock period")
150
151 # the amount of time in nanoseconds from issuing an activate command
152 # to the data being available in the row buffer for a read/write
153 tRCD = Param.Latency("RAS to CAS delay")
154
155 # the time from issuing a read/write command to seeing the actual data
156 tCL = Param.Latency("CAS latency")
157
158 # minimum time between a precharge and subsequent activate
159 tRP = Param.Latency("Row precharge time")
160
161 # minimum time between an activate and a precharge to the same row
162 tRAS = Param.Latency("ACT to PRE delay")
163
164 # minimum time between a write data transfer and a precharge
165 tWR = Param.Latency("Write recovery time")
166
167 # minimum time between a read and precharge command
168 tRTP = Param.Latency("Read to precharge")
169
170 # time to complete a burst transfer, typically the burst length
171 # divided by two due to the DDR bus, but by making it a parameter
172 # it is easier to also evaluate SDR memories like WideIO.
173 # This parameter has to account for burst length.
174 # Read/Write requests with data size larger than one full burst are broken
175 # down into multiple requests in the controller
176 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
177 # With bank group architectures, tBURST represents the CAS-to-CAS
178 # delay for bursts to different bank groups (tCCD_S)
179 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
180
181 # CAS-to-CAS delay for bursts to the same bank group
182 # only utilized with bank group architectures; set to 0 for default case
183 # tBURST is equivalent to tCCD_S; no explicit parameter required
184 # for CAS-to-CAS delay for bursts to different bank groups
185 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
186
187 # Write-to-Write delay for bursts to the same bank group
188 # only utilized with bank group architectures; set to 0 for default case
189 # This will be used to enable different same bank group delays
190 # for writes versus reads
191 tCCD_L_WR = Param.Latency(Self.tCCD_L,
192 "Same bank group Write to Write delay")
193
194 # time taken to complete one refresh cycle (N rows in all banks)
195 tRFC = Param.Latency("Refresh cycle time")
196
197 # refresh command interval, how often a "ref" command needs
198 # to be sent. It is 7.8 us for a 64ms refresh requirement
199 tREFI = Param.Latency("Refresh command interval")
200
201 # write-to-read, same rank turnaround penalty
202 tWTR = Param.Latency("Write to read, same rank switching time")
203
204 # read-to-write, same rank turnaround penalty
205 tRTW = Param.Latency("Read to write, same rank switching time")
206
207 # rank-to-rank bus delay penalty
208 # this does not correlate to a memory timing parameter and encompasses:
209 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
210 # different rank bus delay
211 tCS = Param.Latency("Rank to rank switching time")
212
213 # minimum row activate to row activate delay time
214 tRRD = Param.Latency("ACT to ACT delay")
215
216 # only utilized with bank group architectures; set to 0 for default case
217 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
218
219 # time window in which a maximum number of activates are allowed
220 # to take place, set to 0 to disable
221 tXAW = Param.Latency("X activation window")
222 activation_limit = Param.Unsigned("Max number of activates in window")
223
224 # time to exit power-down mode
225 # Exit power-down to next valid command delay
226 tXP = Param.Latency("0ns", "Power-up Delay")
227
228 # Exit Powerdown to commands requiring a locked DLL
229 tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
230
231 # time to exit self-refresh mode
232 tXS = Param.Latency("0ns", "Self-refresh exit latency")
233
234 # time to exit self-refresh mode with locked DLL
235 tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
236
237 # Currently rolled into other params
238 ######################################################################
239
240 # tRC - assumed to be tRAS + tRP
241
242 # Power Behaviour and Constraints
243 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
244 # defined as VDD and VDD2. Each current is defined for each voltage domain
245 # separately. For example, current IDD0 is active-precharge current for
246 # voltage domain VDD and current IDD02 is active-precharge current for
247 # voltage domain VDD2.
248 # By default all currents are set to 0mA. Users who are only interested in
249 # the performance of DRAMs can leave them at 0.
250
251 # Operating 1 Bank Active-Precharge current
252 IDD0 = Param.Current("0mA", "Active precharge current")
253
254 # Operating 1 Bank Active-Precharge current multiple voltage Range
255 IDD02 = Param.Current("0mA", "Active precharge current VDD2")
256
257 # Precharge Power-down Current: Slow exit
258 IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
259
260 # Precharge Power-down Current: Slow exit multiple voltage Range
261 IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
262
263 # Precharge Power-down Current: Fast exit
264 IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
265
266 # Precharge Power-down Current: Fast exit multiple voltage Range
267 IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
268
269 # Precharge Standby current
270 IDD2N = Param.Current("0mA", "Precharge Standby current")
271
272 # Precharge Standby current multiple voltage range
273 IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
274
275 # Active Power-down current: slow exit
276 IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
277
278 # Active Power-down current: slow exit multiple voltage range
279 IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
280
281 # Active Power-down current : fast exit
282 IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
283
284 # Active Power-down current : fast exit multiple voltage range
285 IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
286
287 # Active Standby current
288 IDD3N = Param.Current("0mA", "Active Standby current")
289
290 # Active Standby current multiple voltage range
291 IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
292
293 # Burst Read Operating Current
294 IDD4R = Param.Current("0mA", "READ current")
295
296 # Burst Read Operating Current multiple voltage range
297 IDD4R2 = Param.Current("0mA", "READ current VDD2")
298
299 # Burst Write Operating Current
300 IDD4W = Param.Current("0mA", "WRITE current")
301
302 # Burst Write Operating Current multiple voltage range
303 IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
304
305 # Refresh Current
306 IDD5 = Param.Current("0mA", "Refresh current")
307
308 # Refresh Current multiple voltage range
309 IDD52 = Param.Current("0mA", "Refresh current VDD2")
310
311 # Self-Refresh Current
312 IDD6 = Param.Current("0mA", "Self-refresh Current")
313
314 # Self-Refresh Current multiple voltage range
315 IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
316
317 # Main voltage range of the DRAM
318 VDD = Param.Voltage("0V", "Main Voltage Range")
319
320 # Second voltage range defined by some DRAMs
321 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
322
323# A single DDR3-1600 x64 channel (one command and address bus), with
324# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
325# an 8x8 configuration.
326class DDR3_1600_8x8(DRAMCtrl):
327 # size of device in bytes
328 device_size = '512MB'
329
330 # 8x8 configuration, 8 devices each with an 8-bit interface
331 device_bus_width = 8
332
333 # DDR3 is a BL8 device
334 burst_length = 8
335
336 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
337 device_rowbuffer_size = '1kB'
338
339 # 8x8 configuration, so 8 devices
340 devices_per_rank = 8
341
342 # Use two ranks
343 ranks_per_channel = 2
344
345 # DDR3 has 8 banks in all configurations
346 banks_per_rank = 8
347
348 # 800 MHz
349 tCK = '1.25ns'
350
351 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
352 tBURST = '5ns'
353
354 # DDR3-1600 11-11-11
355 tRCD = '13.75ns'
356 tCL = '13.75ns'
357 tRP = '13.75ns'
358 tRAS = '35ns'
359 tRRD = '6ns'
360 tXAW = '30ns'
361 activation_limit = 4
362 tRFC = '260ns'
363
364 tWR = '15ns'
365
366 # Greater of 4 CK or 7.5 ns
367 tWTR = '7.5ns'
368
369 # Greater of 4 CK or 7.5 ns
370 tRTP = '7.5ns'
371
372 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
373 tRTW = '2.5ns'
374
375 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
376 tCS = '2.5ns'
377
378 # <=85C, half for >85C
379 tREFI = '7.8us'
380
381 # active powerdown and precharge powerdown exit time
382 tXP = '6ns'
383
384 # self refresh exit time
385 tXS = '270ns'
386
387 # Current values from datasheet Die Rev E,J
388 IDD0 = '55mA'
389 IDD2N = '32mA'
390 IDD3N = '38mA'
391 IDD4W = '125mA'
392 IDD4R = '157mA'
393 IDD5 = '235mA'
394 IDD3P1 = '38mA'
395 IDD2P1 = '32mA'
396 IDD6 = '20mA'
397 VDD = '1.5V'
398
399# A single HMC-2500 x32 model based on:
400# [1] DRAMSpec: a high-level DRAM bank modelling tool
401# developed at the University of Kaiserslautern. This high level tool
402# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
403# estimate the DRAM bank latency and power numbers.
404# [2] High performance AXI-4.0 based interconnect for extensible smart memory
405# cubes (E. Azarkhish et. al)
406# Assumed for the HMC model is a 30 nm technology node.
407# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
408# layers).
409# Each layer has 16 vaults and each vault consists of 2 banks per layer.
410# In order to be able to use the same controller used for 2D DRAM generations
411# for HMC, the following analogy is done:
412# Channel (DDR) => Vault (HMC)
413# device_size (DDR) => size of a single layer in a vault
414# ranks per channel (DDR) => number of layers
415# banks per rank (DDR) => banks per layer
416# devices per rank (DDR) => devices per layer ( 1 for HMC).
417# The parameters for which no input is available are inherited from the DDR3
418# configuration.
419# This configuration includes the latencies from the DRAM to the logic layer
420# of the HMC
421class HMC_2500_1x32(DDR3_1600_8x8):
422 # size of device
423 # two banks per device with each bank 4MB [2]
424 device_size = '8MB'
425
426 # 1x32 configuration, 1 device with 32 TSVs [2]
427 device_bus_width = 32
428
429 # HMC is a BL8 device [2]
430 burst_length = 8
431
432 # Each device has a page (row buffer) size of 256 bytes [2]
433 device_rowbuffer_size = '256B'
434
435 # 1x32 configuration, so 1 device [2]
436 devices_per_rank = 1
437
438 # 4 layers so 4 ranks [2]
439 ranks_per_channel = 4
440
441 # HMC has 2 banks per layer [2]
442 # Each layer represents a rank. With 4 layers and 8 banks in total, each
443 # layer has 2 banks; thus 2 banks per rank.
444 banks_per_rank = 2
445
446 # 1250 MHz [2]
447 tCK = '0.8ns'
448
449 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
450 tBURST = '3.2ns'
451
452 # Values using DRAMSpec HMC model [1]
453 tRCD = '10.2ns'
454 tCL = '9.9ns'
455 tRP = '7.7ns'
456 tRAS = '21.6ns'
457
458 # tRRD depends on the power supply network for each vendor.
459 # We assume a tRRD of a double bank approach to be equal to 4 clock
460 # cycles (Assumption)
461 tRRD = '3.2ns'
462
463 # activation limit is set to 0 since there are only 2 banks per vault
464 # layer.
465 activation_limit = 0
466
467 # Values using DRAMSpec HMC model [1]
468 tRFC = '59ns'
469 tWR = '8ns'
470 tRTP = '4.9ns'
471
472 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
473 # 0.8 ns (Assumption)
474 tCS = '0.8ns'
475
476 # Value using DRAMSpec HMC model [1]
477 tREFI = '3.9us'
478
479 # The default page policy in the vault controllers is simple closed page
480 # [2] nevertheless 'close' policy opens and closes the row multiple times
481 # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
482 page_policy = 'close_adaptive'
483
484 # RoCoRaBaCh resembles the default address mapping in HMC
485 addr_mapping = 'RoCoRaBaCh'
486 min_writes_per_switch = 8
487
488 # These parameters do not directly correlate with buffer_size in real
489 # hardware. Nevertheless, their value has been tuned to achieve a
490 # bandwidth similar to the cycle-accurate model in [2]
491 write_buffer_size = 32
492 read_buffer_size = 32
493
494 # The static latency of the vault controllers is estimated to be smaller
495 # than a full DRAM channel controller
496 static_backend_latency='4ns'
497 static_frontend_latency='4ns'
498
499# A single DDR3-2133 x64 channel refining a selected subset of the
500# options for the DDR-1600 configuration, based on the same DDR3-1600
501# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
502# consistent across the two configurations.
503class DDR3_2133_8x8(DDR3_1600_8x8):
504 # 1066 MHz
505 tCK = '0.938ns'
506
507 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
508 tBURST = '3.752ns'
509
510 # DDR3-2133 14-14-14
511 tRCD = '13.09ns'
512 tCL = '13.09ns'
513 tRP = '13.09ns'
514 tRAS = '33ns'
515 tRRD = '5ns'
516 tXAW = '25ns'
517
518 # Current values from datasheet
519 IDD0 = '70mA'
520 IDD2N = '37mA'
521 IDD3N = '44mA'
522 IDD4W = '157mA'
523 IDD4R = '191mA'
524 IDD5 = '250mA'
525 IDD3P1 = '44mA'
526 IDD2P1 = '43mA'
527 IDD6 ='20mA'
528 VDD = '1.5V'
529
530# A single DDR4-2400 x64 channel (one command and address bus), with
531# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
532# in an 16x4 configuration.
533# Total channel capacity is 32GB
534# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
535class DDR4_2400_16x4(DRAMCtrl):
536 # size of device
537 device_size = '1GB'
538
539 # 16x4 configuration, 16 devices each with a 4-bit interface
540 device_bus_width = 4
541
542 # DDR4 is a BL8 device
543 burst_length = 8
544
545 # Each device has a page (row buffer) size of 512 byte (1K columns x4)
546 device_rowbuffer_size = '512B'
547
548 # 16x4 configuration, so 16 devices
549 devices_per_rank = 16
550
551 # Match our DDR3 configurations which is dual rank
552 ranks_per_channel = 2
553
554 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
555 # Set to 4 for x4 case
556 bank_groups_per_rank = 4
557
558 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
559 # configurations). Currently we do not capture the additional
560 # constraints incurred by the bank groups
561 banks_per_rank = 16
562
563 # override the default buffer sizes and go for something larger to
564 # accommodate the larger bank count
565 write_buffer_size = 128
566 read_buffer_size = 64
567
568 # 1200 MHz
569 tCK = '0.833ns'
570
571 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
572 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
573 # With bank group architectures, tBURST represents the CAS-to-CAS
574 # delay for bursts to different bank groups (tCCD_S)
575 tBURST = '3.332ns'
576
577 # @2400 data rate, tCCD_L is 6 CK
578 # CAS-to-CAS delay for bursts to the same bank group
579 # tBURST is equivalent to tCCD_S; no explicit parameter required
580 # for CAS-to-CAS delay for bursts to different bank groups
581 tCCD_L = '5ns';
582
583 # DDR4-2400 17-17-17
584 tRCD = '14.16ns'
585 tCL = '14.16ns'
586 tRP = '14.16ns'
587 tRAS = '32ns'
588
589 # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
590 tRRD = '3.332ns'
591
592 # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
593 tRRD_L = '4.9ns';
594
595 # tFAW for 512B page is MAX(16 CK, 13ns)
596 tXAW = '13.328ns'
597 activation_limit = 4
598 # tRFC is 350ns
599 tRFC = '350ns'
600
601 tWR = '15ns'
602
603 # Here using the average of WTR_S and WTR_L
604 tWTR = '5ns'
605
606 # Greater of 4 CK or 7.5 ns
607 tRTP = '7.5ns'
608
609 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
610 tRTW = '1.666ns'
611
612 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
613 tCS = '1.666ns'
614
615 # <=85C, half for >85C
616 tREFI = '7.8us'
617
618 # active powerdown and precharge powerdown exit time
619 tXP = '6ns'
620
621 # self refresh exit time
622 # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
623 # tRFC + 10ns = 340ns
624 tXS = '340ns'
625
626 # Current values from datasheet
627 IDD0 = '43mA'
628 IDD02 = '3mA'
629 IDD2N = '34mA'
630 IDD3N = '38mA'
631 IDD3N2 = '3mA'
632 IDD4W = '103mA'
633 IDD4R = '110mA'
634 IDD5 = '250mA'
635 IDD3P1 = '32mA'
636 IDD2P1 = '25mA'
637 IDD6 = '30mA'
638 VDD = '1.2V'
639 VDD2 = '2.5V'
640
641# A single DDR4-2400 x64 channel (one command and address bus), with
642# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
643# in an 8x8 configuration.
644# Total channel capacity is 16GB
645# 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
646class DDR4_2400_8x8(DDR4_2400_16x4):
647 # 8x8 configuration, 8 devices each with an 8-bit interface
648 device_bus_width = 8
649
650 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
651 device_rowbuffer_size = '1kB'
652
653 # 8x8 configuration, so 8 devices
654 devices_per_rank = 8
655
656 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
657 tRRD_L = '4.9ns';
658
659 tXAW = '21ns'
660
661 # Current values from datasheet
662 IDD0 = '48mA'
663 IDD3N = '43mA'
664 IDD4W = '123mA'
665 IDD4R = '135mA'
666 IDD3P1 = '37mA'
667
668# A single DDR4-2400 x64 channel (one command and address bus), with
669# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
670# in an 4x16 configuration.
671# Total channel capacity is 4GB
672# 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
673class DDR4_2400_4x16(DDR4_2400_16x4):
674 # 4x16 configuration, 4 devices each with an 16-bit interface
675 device_bus_width = 16
676
677 # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
678 device_rowbuffer_size = '2kB'
679
680 # 4x16 configuration, so 4 devices
681 devices_per_rank = 4
682
683 # Single rank for x16
684 ranks_per_channel = 1
685
686 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
687 # Set to 2 for x16 case
688 bank_groups_per_rank = 2
689
690 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
691 # configurations). Currently we do not capture the additional
692 # constraints incurred by the bank groups
693 banks_per_rank = 8
694
695 # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
696 tRRD = '5.3ns'
697
698 # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
699 tRRD_L = '6.4ns';
700
701 tXAW = '30ns'
702
703 # Current values from datasheet
704 IDD0 = '80mA'
705 IDD02 = '4mA'
706 IDD2N = '34mA'
707 IDD3N = '47mA'
708 IDD4W = '228mA'
709 IDD4R = '243mA'
710 IDD5 = '280mA'
711 IDD3P1 = '41mA'
712
713# A single LPDDR2-S4 x32 interface (one command/address bus), with
714# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
715# in a 1x32 configuration.
716class LPDDR2_S4_1066_1x32(DRAMCtrl):
717 # No DLL in LPDDR2
718 dll = False
719
720 # size of device
721 device_size = '512MB'
722
723 # 1x32 configuration, 1 device with a 32-bit interface
724 device_bus_width = 32
725
726 # LPDDR2_S4 is a BL4 and BL8 device
727 burst_length = 8
728
729 # Each device has a page (row buffer) size of 1KB
730 # (this depends on the memory density)
731 device_rowbuffer_size = '1kB'
732
733 # 1x32 configuration, so 1 device
734 devices_per_rank = 1
735
736 # Use a single rank
737 ranks_per_channel = 1
738
739 # LPDDR2-S4 has 8 banks in all configurations
740 banks_per_rank = 8
741
742 # 533 MHz
743 tCK = '1.876ns'
744
745 # Fixed at 15 ns
746 tRCD = '15ns'
747
748 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
749 tCL = '15ns'
750
751 # Pre-charge one bank 15 ns (all banks 18 ns)
752 tRP = '15ns'
753
754 tRAS = '42ns'
755 tWR = '15ns'
756
757 tRTP = '7.5ns'
758
759 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
760 # Note this is a BL8 DDR device.
761 # Requests larger than 32 bytes are broken down into multiple requests
762 # in the controller
763 tBURST = '7.5ns'
764
765 # LPDDR2-S4, 4 Gbit
766 tRFC = '130ns'
767 tREFI = '3.9us'
768
769 # active powerdown and precharge powerdown exit time
770 tXP = '7.5ns'
771
772 # self refresh exit time
773 tXS = '140ns'
774
775 # Irrespective of speed grade, tWTR is 7.5 ns
776 tWTR = '7.5ns'
777
778 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
779 tRTW = '3.75ns'
780
781 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
782 tCS = '3.75ns'
783
784 # Activate to activate irrespective of density and speed grade
785 tRRD = '10.0ns'
786
787 # Irrespective of density, tFAW is 50 ns
788 tXAW = '50ns'
789 activation_limit = 4
790
791 # Current values from datasheet
792 IDD0 = '15mA'
793 IDD02 = '70mA'
794 IDD2N = '2mA'
795 IDD2N2 = '30mA'
796 IDD3N = '2.5mA'
797 IDD3N2 = '30mA'
798 IDD4W = '10mA'
799 IDD4W2 = '190mA'
800 IDD4R = '3mA'
801 IDD4R2 = '220mA'
802 IDD5 = '40mA'
803 IDD52 = '150mA'
804 IDD3P1 = '1.2mA'
805 IDD3P12 = '8mA'
806 IDD2P1 = '0.6mA'
807 IDD2P12 = '0.8mA'
808 IDD6 = '1mA'
809 IDD62 = '3.2mA'
810 VDD = '1.8V'
811 VDD2 = '1.2V'
812
813# A single WideIO x128 interface (one command and address bus), with
814# default timings based on an estimated WIO-200 8 Gbit part.
815class WideIO_200_1x128(DRAMCtrl):
816 # No DLL for WideIO
817 dll = False
818
819 # size of device
820 device_size = '1024MB'
821
822 # 1x128 configuration, 1 device with a 128-bit interface
823 device_bus_width = 128
824
825 # This is a BL4 device
826 burst_length = 4
827
828 # Each device has a page (row buffer) size of 4KB
829 # (this depends on the memory density)
830 device_rowbuffer_size = '4kB'
831
832 # 1x128 configuration, so 1 device
833 devices_per_rank = 1
834
835 # Use one rank for a one-high die stack
836 ranks_per_channel = 1
837
838 # WideIO has 4 banks in all configurations
839 banks_per_rank = 4
840
841 # 200 MHz
842 tCK = '5ns'
843
844 # WIO-200
845 tRCD = '18ns'
846 tCL = '18ns'
847 tRP = '18ns'
848 tRAS = '42ns'
849 tWR = '15ns'
850 # Read to precharge is same as the burst
851 tRTP = '20ns'
852
853 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
854 # Note this is a BL4 SDR device.
855 tBURST = '20ns'
856
857 # WIO 8 Gb
858 tRFC = '210ns'
859
860 # WIO 8 Gb, <=85C, half for >85C
861 tREFI = '3.9us'
862
863 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
864 tWTR = '15ns'
865
866 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
867 tRTW = '10ns'
868
869 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
870 tCS = '10ns'
871
872 # Activate to activate irrespective of density and speed grade
873 tRRD = '10.0ns'
874
875 # Two instead of four activation window
876 tXAW = '50ns'
877 activation_limit = 2
878
879 # The WideIO specification does not provide current information
880
881# A single LPDDR3 x32 interface (one command/address bus), with
882# default timings based on a LPDDR3-1600 4 Gbit part (Micron
883# EDF8132A1MC) in a 1x32 configuration.
884class LPDDR3_1600_1x32(DRAMCtrl):
885 # No DLL for LPDDR3
886 dll = False
887
888 # size of device
889 device_size = '512MB'
890
891 # 1x32 configuration, 1 device with a 32-bit interface
892 device_bus_width = 32
893
894 # LPDDR3 is a BL8 device
895 burst_length = 8
896
897 # Each device has a page (row buffer) size of 4KB
898 device_rowbuffer_size = '4kB'
899
900 # 1x32 configuration, so 1 device
901 devices_per_rank = 1
902
903 # Technically the datasheet is a dual-rank package, but for
904 # comparison with the LPDDR2 config we stick to a single rank
905 ranks_per_channel = 1
906
907 # LPDDR3 has 8 banks in all configurations
908 banks_per_rank = 8
909
910 # 800 MHz
911 tCK = '1.25ns'
912
913 tRCD = '18ns'
914
915 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
916 tCL = '15ns'
917
918 tRAS = '42ns'
919 tWR = '15ns'
920
921 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
922 tRTP = '7.5ns'
923
924 # Pre-charge one bank 18 ns (all banks 21 ns)
925 tRP = '18ns'
926
927 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
928 # Note this is a BL8 DDR device.
929 # Requests larger than 32 bytes are broken down into multiple requests
930 # in the controller
931 tBURST = '5ns'
932
933 # LPDDR3, 4 Gb
934 tRFC = '130ns'
935 tREFI = '3.9us'
936
937 # active powerdown and precharge powerdown exit time
938 tXP = '7.5ns'
939
940 # self refresh exit time
941 tXS = '140ns'
942
943 # Irrespective of speed grade, tWTR is 7.5 ns
944 tWTR = '7.5ns'
945
946 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
947 tRTW = '2.5ns'
948
949 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
950 tCS = '2.5ns'
951
952 # Activate to activate irrespective of density and speed grade
953 tRRD = '10.0ns'
954
955 # Irrespective of size, tFAW is 50 ns
956 tXAW = '50ns'
957 activation_limit = 4
958
959 # Current values from datasheet
960 IDD0 = '8mA'
961 IDD02 = '60mA'
962 IDD2N = '0.8mA'
963 IDD2N2 = '26mA'
964 IDD3N = '2mA'
965 IDD3N2 = '34mA'
966 IDD4W = '2mA'
967 IDD4W2 = '190mA'
968 IDD4R = '2mA'
969 IDD4R2 = '230mA'
970 IDD5 = '28mA'
971 IDD52 = '150mA'
972 IDD3P1 = '1.4mA'
973 IDD3P12 = '11mA'
974 IDD2P1 = '0.8mA'
975 IDD2P12 = '1.8mA'
976 IDD6 = '0.5mA'
977 IDD62 = '1.8mA'
978 VDD = '1.8V'
979 VDD2 = '1.2V'
980
981# A single GDDR5 x64 interface, with
982# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
983# H5GQ1H24AFR) in a 2x32 configuration.
984class GDDR5_4000_2x32(DRAMCtrl):
985 # size of device
986 device_size = '128MB'
987
988 # 2x32 configuration, 1 device with a 32-bit interface
989 device_bus_width = 32
990
991 # GDDR5 is a BL8 device
992 burst_length = 8
993
994 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
995 device_rowbuffer_size = '256B'
996
997 # 2x32 configuration, so 2 devices
998 devices_per_rank = 2
999
1000 # assume single rank
1001 ranks_per_channel = 1
1002
1003 # GDDR5 has 4 bank groups
1004 bank_groups_per_rank = 4
1005
1006 # GDDR5 has 16 banks with 4 bank groups
1007 banks_per_rank = 16
1008
1009 # 1000 MHz
1010 tCK = '1ns'
1011
1012 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
1013 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
1014 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
1015 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
1016 # With bank group architectures, tBURST represents the CAS-to-CAS
1017 # delay for bursts to different bank groups (tCCD_S)
1018 tBURST = '2ns'
1019
1020 # @1000MHz data rate, tCCD_L is 3 CK
1021 # CAS-to-CAS delay for bursts to the same bank group
1022 # tBURST is equivalent to tCCD_S; no explicit parameter required
1023 # for CAS-to-CAS delay for bursts to different bank groups
1024 tCCD_L = '3ns';
1025
1026 tRCD = '12ns'
1027
1028 # tCL is not directly found in datasheet and assumed equal tRCD
1029 tCL = '12ns'
1030
1031 tRP = '12ns'
1032 tRAS = '28ns'
1033
1034 # RRD_S (different bank group)
1035 # RRD_S is 5.5 ns in datasheet.
1036 # rounded to the next multiple of tCK
1037 tRRD = '6ns'
1038
1039 # RRD_L (same bank group)
1040 # RRD_L is 5.5 ns in datasheet.
1041 # rounded to the next multiple of tCK
1042 tRRD_L = '6ns'
1043
1044 tXAW = '23ns'
1045
1046 # tXAW < 4 x tRRD.
1047 # Therefore, activation limit is set to 0
1048 activation_limit = 0
1049
1050 tRFC = '65ns'
1051 tWR = '12ns'
1052
1053 # Here using the average of WTR_S and WTR_L
1054 tWTR = '5ns'
1055
1056 # Read-to-Precharge 2 CK
1057 tRTP = '2ns'
1058
1059 # Assume 2 cycles
1060 tRTW = '2ns'
1061
1062# A single HBM x128 interface (one command and address bus), with
1063# default timings based on data publically released
1064# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
1065# IDD measurement values, and by extrapolating data from other classes.
1066# Architecture values based on published HBM spec
1067# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
1068class HBM_1000_4H_1x128(DRAMCtrl):
1069 # HBM gen1 supports up to 8 128-bit physical channels
1070 # Configuration defines a single channel, with the capacity
1071 # set to (full_ stack_capacity / 8) based on 2Gb dies
1072 # To use all 8 channels, set 'channels' parameter to 8 in
1073 # system configuration
1074
1075 # 128-bit interface legacy mode
1076 device_bus_width = 128
1077
1078 # HBM supports BL4 and BL2 (legacy mode only)
1079 burst_length = 4
1080
1081 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
1082 # with 8 channels, 128MB per channel
1083 device_size = '128MB'
1084
1085 device_rowbuffer_size = '2kB'
1086
1087 # 1x128 configuration
1088 devices_per_rank = 1
1089
1090 # HBM does not have a CS pin; set rank to 1
1091 ranks_per_channel = 1
1092
1093 # HBM has 8 or 16 banks depending on capacity
1094 # 2Gb dies have 8 banks
1095 banks_per_rank = 8
1096
1097 # depending on frequency, bank groups may be required
1098 # will always have 4 bank groups when enabled
1099 # current specifications do not define the minimum frequency for
1100 # bank group architecture
1101 # setting bank_groups_per_rank to 0 to disable until range is defined
1102 bank_groups_per_rank = 0
1103
1104 # 500 MHz for 1Gbps DDR data rate
1105 tCK = '2ns'
1106
1107 # use values from IDD measurement in JEDEC spec
1108 # use tRP value for tRCD and tCL similar to other classes
1109 tRP = '15ns'
1110 tRCD = '15ns'
1111 tCL = '15ns'
1112 tRAS = '33ns'
1113
1114 # BL2 and BL4 supported, default to BL4
1115 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
1116 tBURST = '4ns'
1117
1118 # value for 2Gb device from JEDEC spec
1119 tRFC = '160ns'
1120
1121 # value for 2Gb device from JEDEC spec
1122 tREFI = '3.9us'
1123
1124 # extrapolate the following from LPDDR configs, using ns values
1125 # to minimize burst length, prefetch differences
1126 tWR = '18ns'
1127 tRTP = '7.5ns'
1128 tWTR = '10ns'
1129
1130 # start with 2 cycles turnaround, similar to other memory classes
1131 # could be more with variations across the stack
1132 tRTW = '4ns'
1133
1134 # single rank device, set to 0
1135 tCS = '0ns'
1136
1137 # from MemCon example, tRRD is 4ns with 2ns tCK
1138 tRRD = '4ns'
1139
1140 # from MemCon example, tFAW is 30ns with 2ns tCK
1141 tXAW = '30ns'
1142 activation_limit = 4
1143
1144 # 4tCK
1145 tXP = '8ns'
1146
1147 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1148 tXS = '168ns'
1149
1150# A single HBM x64 interface (one command and address bus), with
1151# default timings based on HBM gen1 and data publically released
1152# A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1153# Note: This defines a pseudo-channel with a unique controller
1154# instantiated per pseudo-channel
1155# Stay at same IO rate (1Gbps) to maintain timing relationship with
1156# HBM gen1 class (HBM_1000_4H_x128) where possible
1157class HBM_1000_4H_1x64(HBM_1000_4H_1x128):
1158 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1159 # Configuration defines a single pseudo channel, with the capacity
1160 # set to (full_ stack_capacity / 16) based on 8Gb dies
1161 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1162 # system configuration
1163
1164 # 64-bit pseudo-channle interface
1165 device_bus_width = 64
1166
1167 # HBM pseudo-channel only supports BL4
1168 burst_length = 4
1169
1170 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1171 # with 16 channels, 256MB per channel
1172 device_size = '256MB'
1173
1174 # page size is halved with pseudo-channel; maintaining the same same number
1175 # of rows per pseudo-channel with 2X banks across 2 channels
1176 device_rowbuffer_size = '1kB'
1177
1178 # HBM has 8 or 16 banks depending on capacity
1179 # Starting with 4Gb dies, 16 banks are defined
1180 banks_per_rank = 16
1181
1182 # reset tRFC for larger, 8Gb device
1183 # use HBM1 4Gb value as a starting point
1184 tRFC = '260ns'
1185
1186 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1187 tXS = '268ns'
1188 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1189 tCS = '2ns'
1190 tREFI = '3.9us'
1191
1192 # active powerdown and precharge powerdown exit time
1193 tXP = '10ns'
1194
1195 # self refresh exit time
1196 tXS = '65ns'
| 74 type = 'DRAMCtrl'
75 cxx_header = "mem/dram_ctrl.hh"
76
77 # single-ported on the system interface side, instantiate with a
78 # bus in front of the controller for multiple ports
79 port = SlavePort("Slave port")
80
81 # the basic configuration of the controller architecture, note
82 # that each entry corresponds to a burst for the specific DRAM
83 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
84 # the cacheline size or request/packet size
85 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
86 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
87
88 # threshold in percent for when to forcefully trigger writes and
89 # start emptying the write buffer
90 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
91
92 # threshold in percentage for when to start writes if the read
93 # queue is empty
94 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
95
96 # minimum write bursts to schedule before switching back to reads
97 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
98 "switching to reads")
99
100 # scheduler, address map and page policy
101 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
102 addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
103 page_policy = Param.PageManage('open_adaptive', "Page management policy")
104
105 # enforce a limit on the number of accesses per row
106 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
107 "closing");
108
109 # size of DRAM Chip in Bytes
110 device_size = Param.MemorySize("Size of DRAM chip")
111
112 # pipeline latency of the controller and PHY, split into a
113 # frontend part and a backend part, with reads and writes serviced
114 # by the queues only seeing the frontend contribution, and reads
115 # serviced by the memory seeing the sum of the two
116 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
117 static_backend_latency = Param.Latency("10ns", "Static backend latency")
118
119 # the physical organisation of the DRAM
120 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
121 "device/chip")
122 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
123 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
124 "device/chip")
125 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
126 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
127
128 # default to 0 bank groups per rank, indicating bank group architecture
129 # is not used
130 # update per memory class when bank group architecture is supported
131 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
132 banks_per_rank = Param.Unsigned("Number of banks per rank")
133 # only used for the address mapping as the controller by
134 # construction is a single channel and multiple controllers have
135 # to be instantiated for a multi-channel configuration
136 channels = Param.Unsigned(1, "Number of channels")
137
138 # For power modelling we need to know if the DRAM has a DLL or not
139 dll = Param.Bool(True, "DRAM has DLL or not")
140
141 # DRAMPower provides in addition to the core power, the possibility to
142 # include RD/WR termination and IO power. This calculation assumes some
143 # default values. The integration of DRAMPower with gem5 does not include
144 # IO and RD/WR termination power by default. This might be added as an
145 # additional feature in the future.
146
147 # timing behaviour and constraints - all in nanoseconds
148
149 # the base clock period of the DRAM
150 tCK = Param.Latency("Clock period")
151
152 # the amount of time in nanoseconds from issuing an activate command
153 # to the data being available in the row buffer for a read/write
154 tRCD = Param.Latency("RAS to CAS delay")
155
156 # the time from issuing a read/write command to seeing the actual data
157 tCL = Param.Latency("CAS latency")
158
159 # minimum time between a precharge and subsequent activate
160 tRP = Param.Latency("Row precharge time")
161
162 # minimum time between an activate and a precharge to the same row
163 tRAS = Param.Latency("ACT to PRE delay")
164
165 # minimum time between a write data transfer and a precharge
166 tWR = Param.Latency("Write recovery time")
167
168 # minimum time between a read and precharge command
169 tRTP = Param.Latency("Read to precharge")
170
171 # time to complete a burst transfer, typically the burst length
172 # divided by two due to the DDR bus, but by making it a parameter
173 # it is easier to also evaluate SDR memories like WideIO.
174 # This parameter has to account for burst length.
175 # Read/Write requests with data size larger than one full burst are broken
176 # down into multiple requests in the controller
177 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
178 # With bank group architectures, tBURST represents the CAS-to-CAS
179 # delay for bursts to different bank groups (tCCD_S)
180 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
181
182 # CAS-to-CAS delay for bursts to the same bank group
183 # only utilized with bank group architectures; set to 0 for default case
184 # tBURST is equivalent to tCCD_S; no explicit parameter required
185 # for CAS-to-CAS delay for bursts to different bank groups
186 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
187
188 # Write-to-Write delay for bursts to the same bank group
189 # only utilized with bank group architectures; set to 0 for default case
190 # This will be used to enable different same bank group delays
191 # for writes versus reads
192 tCCD_L_WR = Param.Latency(Self.tCCD_L,
193 "Same bank group Write to Write delay")
194
195 # time taken to complete one refresh cycle (N rows in all banks)
196 tRFC = Param.Latency("Refresh cycle time")
197
198 # refresh command interval, how often a "ref" command needs
199 # to be sent. It is 7.8 us for a 64ms refresh requirement
200 tREFI = Param.Latency("Refresh command interval")
201
202 # write-to-read, same rank turnaround penalty
203 tWTR = Param.Latency("Write to read, same rank switching time")
204
205 # read-to-write, same rank turnaround penalty
206 tRTW = Param.Latency("Read to write, same rank switching time")
207
208 # rank-to-rank bus delay penalty
209 # this does not correlate to a memory timing parameter and encompasses:
210 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
211 # different rank bus delay
212 tCS = Param.Latency("Rank to rank switching time")
213
214 # minimum row activate to row activate delay time
215 tRRD = Param.Latency("ACT to ACT delay")
216
217 # only utilized with bank group architectures; set to 0 for default case
218 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
219
220 # time window in which a maximum number of activates are allowed
221 # to take place, set to 0 to disable
222 tXAW = Param.Latency("X activation window")
223 activation_limit = Param.Unsigned("Max number of activates in window")
224
225 # time to exit power-down mode
226 # Exit power-down to next valid command delay
227 tXP = Param.Latency("0ns", "Power-up Delay")
228
229 # Exit Powerdown to commands requiring a locked DLL
230 tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
231
232 # time to exit self-refresh mode
233 tXS = Param.Latency("0ns", "Self-refresh exit latency")
234
235 # time to exit self-refresh mode with locked DLL
236 tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
237
238 # Currently rolled into other params
239 ######################################################################
240
241 # tRC - assumed to be tRAS + tRP
242
243 # Power Behaviour and Constraints
244 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
245 # defined as VDD and VDD2. Each current is defined for each voltage domain
246 # separately. For example, current IDD0 is active-precharge current for
247 # voltage domain VDD and current IDD02 is active-precharge current for
248 # voltage domain VDD2.
249 # By default all currents are set to 0mA. Users who are only interested in
250 # the performance of DRAMs can leave them at 0.
251
252 # Operating 1 Bank Active-Precharge current
253 IDD0 = Param.Current("0mA", "Active precharge current")
254
255 # Operating 1 Bank Active-Precharge current multiple voltage Range
256 IDD02 = Param.Current("0mA", "Active precharge current VDD2")
257
258 # Precharge Power-down Current: Slow exit
259 IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
260
261 # Precharge Power-down Current: Slow exit multiple voltage Range
262 IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
263
264 # Precharge Power-down Current: Fast exit
265 IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
266
267 # Precharge Power-down Current: Fast exit multiple voltage Range
268 IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
269
270 # Precharge Standby current
271 IDD2N = Param.Current("0mA", "Precharge Standby current")
272
273 # Precharge Standby current multiple voltage range
274 IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
275
276 # Active Power-down current: slow exit
277 IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
278
279 # Active Power-down current: slow exit multiple voltage range
280 IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
281
282 # Active Power-down current : fast exit
283 IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
284
285 # Active Power-down current : fast exit multiple voltage range
286 IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
287
288 # Active Standby current
289 IDD3N = Param.Current("0mA", "Active Standby current")
290
291 # Active Standby current multiple voltage range
292 IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
293
294 # Burst Read Operating Current
295 IDD4R = Param.Current("0mA", "READ current")
296
297 # Burst Read Operating Current multiple voltage range
298 IDD4R2 = Param.Current("0mA", "READ current VDD2")
299
300 # Burst Write Operating Current
301 IDD4W = Param.Current("0mA", "WRITE current")
302
303 # Burst Write Operating Current multiple voltage range
304 IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
305
306 # Refresh Current
307 IDD5 = Param.Current("0mA", "Refresh current")
308
309 # Refresh Current multiple voltage range
310 IDD52 = Param.Current("0mA", "Refresh current VDD2")
311
312 # Self-Refresh Current
313 IDD6 = Param.Current("0mA", "Self-refresh Current")
314
315 # Self-Refresh Current multiple voltage range
316 IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
317
318 # Main voltage range of the DRAM
319 VDD = Param.Voltage("0V", "Main Voltage Range")
320
321 # Second voltage range defined by some DRAMs
322 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
323
324# A single DDR3-1600 x64 channel (one command and address bus), with
325# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
326# an 8x8 configuration.
327class DDR3_1600_8x8(DRAMCtrl):
328 # size of device in bytes
329 device_size = '512MB'
330
331 # 8x8 configuration, 8 devices each with an 8-bit interface
332 device_bus_width = 8
333
334 # DDR3 is a BL8 device
335 burst_length = 8
336
337 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
338 device_rowbuffer_size = '1kB'
339
340 # 8x8 configuration, so 8 devices
341 devices_per_rank = 8
342
343 # Use two ranks
344 ranks_per_channel = 2
345
346 # DDR3 has 8 banks in all configurations
347 banks_per_rank = 8
348
349 # 800 MHz
350 tCK = '1.25ns'
351
352 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
353 tBURST = '5ns'
354
355 # DDR3-1600 11-11-11
356 tRCD = '13.75ns'
357 tCL = '13.75ns'
358 tRP = '13.75ns'
359 tRAS = '35ns'
360 tRRD = '6ns'
361 tXAW = '30ns'
362 activation_limit = 4
363 tRFC = '260ns'
364
365 tWR = '15ns'
366
367 # Greater of 4 CK or 7.5 ns
368 tWTR = '7.5ns'
369
370 # Greater of 4 CK or 7.5 ns
371 tRTP = '7.5ns'
372
373 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
374 tRTW = '2.5ns'
375
376 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
377 tCS = '2.5ns'
378
379 # <=85C, half for >85C
380 tREFI = '7.8us'
381
382 # active powerdown and precharge powerdown exit time
383 tXP = '6ns'
384
385 # self refresh exit time
386 tXS = '270ns'
387
388 # Current values from datasheet Die Rev E,J
389 IDD0 = '55mA'
390 IDD2N = '32mA'
391 IDD3N = '38mA'
392 IDD4W = '125mA'
393 IDD4R = '157mA'
394 IDD5 = '235mA'
395 IDD3P1 = '38mA'
396 IDD2P1 = '32mA'
397 IDD6 = '20mA'
398 VDD = '1.5V'
399
400# A single HMC-2500 x32 model based on:
401# [1] DRAMSpec: a high-level DRAM bank modelling tool
402# developed at the University of Kaiserslautern. This high level tool
403# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
404# estimate the DRAM bank latency and power numbers.
405# [2] High performance AXI-4.0 based interconnect for extensible smart memory
406# cubes (E. Azarkhish et. al)
407# Assumed for the HMC model is a 30 nm technology node.
408# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
409# layers).
410# Each layer has 16 vaults and each vault consists of 2 banks per layer.
411# In order to be able to use the same controller used for 2D DRAM generations
412# for HMC, the following analogy is done:
413# Channel (DDR) => Vault (HMC)
414# device_size (DDR) => size of a single layer in a vault
415# ranks per channel (DDR) => number of layers
416# banks per rank (DDR) => banks per layer
417# devices per rank (DDR) => devices per layer ( 1 for HMC).
418# The parameters for which no input is available are inherited from the DDR3
419# configuration.
420# This configuration includes the latencies from the DRAM to the logic layer
421# of the HMC
422class HMC_2500_1x32(DDR3_1600_8x8):
423 # size of device
424 # two banks per device with each bank 4MB [2]
425 device_size = '8MB'
426
427 # 1x32 configuration, 1 device with 32 TSVs [2]
428 device_bus_width = 32
429
430 # HMC is a BL8 device [2]
431 burst_length = 8
432
433 # Each device has a page (row buffer) size of 256 bytes [2]
434 device_rowbuffer_size = '256B'
435
436 # 1x32 configuration, so 1 device [2]
437 devices_per_rank = 1
438
439 # 4 layers so 4 ranks [2]
440 ranks_per_channel = 4
441
442 # HMC has 2 banks per layer [2]
443 # Each layer represents a rank. With 4 layers and 8 banks in total, each
444 # layer has 2 banks; thus 2 banks per rank.
445 banks_per_rank = 2
446
447 # 1250 MHz [2]
448 tCK = '0.8ns'
449
450 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
451 tBURST = '3.2ns'
452
453 # Values using DRAMSpec HMC model [1]
454 tRCD = '10.2ns'
455 tCL = '9.9ns'
456 tRP = '7.7ns'
457 tRAS = '21.6ns'
458
459 # tRRD depends on the power supply network for each vendor.
460 # We assume a tRRD of a double bank approach to be equal to 4 clock
461 # cycles (Assumption)
462 tRRD = '3.2ns'
463
464 # activation limit is set to 0 since there are only 2 banks per vault
465 # layer.
466 activation_limit = 0
467
468 # Values using DRAMSpec HMC model [1]
469 tRFC = '59ns'
470 tWR = '8ns'
471 tRTP = '4.9ns'
472
473 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
474 # 0.8 ns (Assumption)
475 tCS = '0.8ns'
476
477 # Value using DRAMSpec HMC model [1]
478 tREFI = '3.9us'
479
480 # The default page policy in the vault controllers is simple closed page
481 # [2] nevertheless 'close' policy opens and closes the row multiple times
482 # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
483 page_policy = 'close_adaptive'
484
485 # RoCoRaBaCh resembles the default address mapping in HMC
486 addr_mapping = 'RoCoRaBaCh'
487 min_writes_per_switch = 8
488
489 # These parameters do not directly correlate with buffer_size in real
490 # hardware. Nevertheless, their value has been tuned to achieve a
491 # bandwidth similar to the cycle-accurate model in [2]
492 write_buffer_size = 32
493 read_buffer_size = 32
494
495 # The static latency of the vault controllers is estimated to be smaller
496 # than a full DRAM channel controller
497 static_backend_latency='4ns'
498 static_frontend_latency='4ns'
499
500# A single DDR3-2133 x64 channel refining a selected subset of the
501# options for the DDR-1600 configuration, based on the same DDR3-1600
502# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
503# consistent across the two configurations.
504class DDR3_2133_8x8(DDR3_1600_8x8):
505 # 1066 MHz
506 tCK = '0.938ns'
507
508 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
509 tBURST = '3.752ns'
510
511 # DDR3-2133 14-14-14
512 tRCD = '13.09ns'
513 tCL = '13.09ns'
514 tRP = '13.09ns'
515 tRAS = '33ns'
516 tRRD = '5ns'
517 tXAW = '25ns'
518
519 # Current values from datasheet
520 IDD0 = '70mA'
521 IDD2N = '37mA'
522 IDD3N = '44mA'
523 IDD4W = '157mA'
524 IDD4R = '191mA'
525 IDD5 = '250mA'
526 IDD3P1 = '44mA'
527 IDD2P1 = '43mA'
528 IDD6 ='20mA'
529 VDD = '1.5V'
530
531# A single DDR4-2400 x64 channel (one command and address bus), with
532# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
533# in an 16x4 configuration.
534# Total channel capacity is 32GB
535# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
536class DDR4_2400_16x4(DRAMCtrl):
537 # size of device
538 device_size = '1GB'
539
540 # 16x4 configuration, 16 devices each with a 4-bit interface
541 device_bus_width = 4
542
543 # DDR4 is a BL8 device
544 burst_length = 8
545
546 # Each device has a page (row buffer) size of 512 byte (1K columns x4)
547 device_rowbuffer_size = '512B'
548
549 # 16x4 configuration, so 16 devices
550 devices_per_rank = 16
551
552 # Match our DDR3 configurations which is dual rank
553 ranks_per_channel = 2
554
555 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
556 # Set to 4 for x4 case
557 bank_groups_per_rank = 4
558
559 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
560 # configurations). Currently we do not capture the additional
561 # constraints incurred by the bank groups
562 banks_per_rank = 16
563
564 # override the default buffer sizes and go for something larger to
565 # accommodate the larger bank count
566 write_buffer_size = 128
567 read_buffer_size = 64
568
569 # 1200 MHz
570 tCK = '0.833ns'
571
572 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
573 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
574 # With bank group architectures, tBURST represents the CAS-to-CAS
575 # delay for bursts to different bank groups (tCCD_S)
576 tBURST = '3.332ns'
577
578 # @2400 data rate, tCCD_L is 6 CK
579 # CAS-to-CAS delay for bursts to the same bank group
580 # tBURST is equivalent to tCCD_S; no explicit parameter required
581 # for CAS-to-CAS delay for bursts to different bank groups
582 tCCD_L = '5ns';
583
584 # DDR4-2400 17-17-17
585 tRCD = '14.16ns'
586 tCL = '14.16ns'
587 tRP = '14.16ns'
588 tRAS = '32ns'
589
590 # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
591 tRRD = '3.332ns'
592
593 # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
594 tRRD_L = '4.9ns';
595
596 # tFAW for 512B page is MAX(16 CK, 13ns)
597 tXAW = '13.328ns'
598 activation_limit = 4
599 # tRFC is 350ns
600 tRFC = '350ns'
601
602 tWR = '15ns'
603
604 # Here using the average of WTR_S and WTR_L
605 tWTR = '5ns'
606
607 # Greater of 4 CK or 7.5 ns
608 tRTP = '7.5ns'
609
610 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
611 tRTW = '1.666ns'
612
613 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
614 tCS = '1.666ns'
615
616 # <=85C, half for >85C
617 tREFI = '7.8us'
618
619 # active powerdown and precharge powerdown exit time
620 tXP = '6ns'
621
622 # self refresh exit time
623 # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
624 # tRFC + 10ns = 340ns
625 tXS = '340ns'
626
627 # Current values from datasheet
628 IDD0 = '43mA'
629 IDD02 = '3mA'
630 IDD2N = '34mA'
631 IDD3N = '38mA'
632 IDD3N2 = '3mA'
633 IDD4W = '103mA'
634 IDD4R = '110mA'
635 IDD5 = '250mA'
636 IDD3P1 = '32mA'
637 IDD2P1 = '25mA'
638 IDD6 = '30mA'
639 VDD = '1.2V'
640 VDD2 = '2.5V'
641
642# A single DDR4-2400 x64 channel (one command and address bus), with
643# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
644# in an 8x8 configuration.
645# Total channel capacity is 16GB
646# 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
647class DDR4_2400_8x8(DDR4_2400_16x4):
648 # 8x8 configuration, 8 devices each with an 8-bit interface
649 device_bus_width = 8
650
651 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
652 device_rowbuffer_size = '1kB'
653
654 # 8x8 configuration, so 8 devices
655 devices_per_rank = 8
656
657 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
658 tRRD_L = '4.9ns';
659
660 tXAW = '21ns'
661
662 # Current values from datasheet
663 IDD0 = '48mA'
664 IDD3N = '43mA'
665 IDD4W = '123mA'
666 IDD4R = '135mA'
667 IDD3P1 = '37mA'
668
669# A single DDR4-2400 x64 channel (one command and address bus), with
670# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
671# in an 4x16 configuration.
672# Total channel capacity is 4GB
673# 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
674class DDR4_2400_4x16(DDR4_2400_16x4):
675 # 4x16 configuration, 4 devices each with an 16-bit interface
676 device_bus_width = 16
677
678 # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
679 device_rowbuffer_size = '2kB'
680
681 # 4x16 configuration, so 4 devices
682 devices_per_rank = 4
683
684 # Single rank for x16
685 ranks_per_channel = 1
686
687 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
688 # Set to 2 for x16 case
689 bank_groups_per_rank = 2
690
691 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
692 # configurations). Currently we do not capture the additional
693 # constraints incurred by the bank groups
694 banks_per_rank = 8
695
696 # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
697 tRRD = '5.3ns'
698
699 # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
700 tRRD_L = '6.4ns';
701
702 tXAW = '30ns'
703
704 # Current values from datasheet
705 IDD0 = '80mA'
706 IDD02 = '4mA'
707 IDD2N = '34mA'
708 IDD3N = '47mA'
709 IDD4W = '228mA'
710 IDD4R = '243mA'
711 IDD5 = '280mA'
712 IDD3P1 = '41mA'
713
714# A single LPDDR2-S4 x32 interface (one command/address bus), with
715# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
716# in a 1x32 configuration.
717class LPDDR2_S4_1066_1x32(DRAMCtrl):
718 # No DLL in LPDDR2
719 dll = False
720
721 # size of device
722 device_size = '512MB'
723
724 # 1x32 configuration, 1 device with a 32-bit interface
725 device_bus_width = 32
726
727 # LPDDR2_S4 is a BL4 and BL8 device
728 burst_length = 8
729
730 # Each device has a page (row buffer) size of 1KB
731 # (this depends on the memory density)
732 device_rowbuffer_size = '1kB'
733
734 # 1x32 configuration, so 1 device
735 devices_per_rank = 1
736
737 # Use a single rank
738 ranks_per_channel = 1
739
740 # LPDDR2-S4 has 8 banks in all configurations
741 banks_per_rank = 8
742
743 # 533 MHz
744 tCK = '1.876ns'
745
746 # Fixed at 15 ns
747 tRCD = '15ns'
748
749 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
750 tCL = '15ns'
751
752 # Pre-charge one bank 15 ns (all banks 18 ns)
753 tRP = '15ns'
754
755 tRAS = '42ns'
756 tWR = '15ns'
757
758 tRTP = '7.5ns'
759
760 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
761 # Note this is a BL8 DDR device.
762 # Requests larger than 32 bytes are broken down into multiple requests
763 # in the controller
764 tBURST = '7.5ns'
765
766 # LPDDR2-S4, 4 Gbit
767 tRFC = '130ns'
768 tREFI = '3.9us'
769
770 # active powerdown and precharge powerdown exit time
771 tXP = '7.5ns'
772
773 # self refresh exit time
774 tXS = '140ns'
775
776 # Irrespective of speed grade, tWTR is 7.5 ns
777 tWTR = '7.5ns'
778
779 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
780 tRTW = '3.75ns'
781
782 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
783 tCS = '3.75ns'
784
785 # Activate to activate irrespective of density and speed grade
786 tRRD = '10.0ns'
787
788 # Irrespective of density, tFAW is 50 ns
789 tXAW = '50ns'
790 activation_limit = 4
791
792 # Current values from datasheet
793 IDD0 = '15mA'
794 IDD02 = '70mA'
795 IDD2N = '2mA'
796 IDD2N2 = '30mA'
797 IDD3N = '2.5mA'
798 IDD3N2 = '30mA'
799 IDD4W = '10mA'
800 IDD4W2 = '190mA'
801 IDD4R = '3mA'
802 IDD4R2 = '220mA'
803 IDD5 = '40mA'
804 IDD52 = '150mA'
805 IDD3P1 = '1.2mA'
806 IDD3P12 = '8mA'
807 IDD2P1 = '0.6mA'
808 IDD2P12 = '0.8mA'
809 IDD6 = '1mA'
810 IDD62 = '3.2mA'
811 VDD = '1.8V'
812 VDD2 = '1.2V'
813
814# A single WideIO x128 interface (one command and address bus), with
815# default timings based on an estimated WIO-200 8 Gbit part.
816class WideIO_200_1x128(DRAMCtrl):
817 # No DLL for WideIO
818 dll = False
819
820 # size of device
821 device_size = '1024MB'
822
823 # 1x128 configuration, 1 device with a 128-bit interface
824 device_bus_width = 128
825
826 # This is a BL4 device
827 burst_length = 4
828
829 # Each device has a page (row buffer) size of 4KB
830 # (this depends on the memory density)
831 device_rowbuffer_size = '4kB'
832
833 # 1x128 configuration, so 1 device
834 devices_per_rank = 1
835
836 # Use one rank for a one-high die stack
837 ranks_per_channel = 1
838
839 # WideIO has 4 banks in all configurations
840 banks_per_rank = 4
841
842 # 200 MHz
843 tCK = '5ns'
844
845 # WIO-200
846 tRCD = '18ns'
847 tCL = '18ns'
848 tRP = '18ns'
849 tRAS = '42ns'
850 tWR = '15ns'
851 # Read to precharge is same as the burst
852 tRTP = '20ns'
853
854 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
855 # Note this is a BL4 SDR device.
856 tBURST = '20ns'
857
858 # WIO 8 Gb
859 tRFC = '210ns'
860
861 # WIO 8 Gb, <=85C, half for >85C
862 tREFI = '3.9us'
863
864 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
865 tWTR = '15ns'
866
867 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
868 tRTW = '10ns'
869
870 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
871 tCS = '10ns'
872
873 # Activate to activate irrespective of density and speed grade
874 tRRD = '10.0ns'
875
876 # Two instead of four activation window
877 tXAW = '50ns'
878 activation_limit = 2
879
880 # The WideIO specification does not provide current information
881
882# A single LPDDR3 x32 interface (one command/address bus), with
883# default timings based on a LPDDR3-1600 4 Gbit part (Micron
884# EDF8132A1MC) in a 1x32 configuration.
885class LPDDR3_1600_1x32(DRAMCtrl):
886 # No DLL for LPDDR3
887 dll = False
888
889 # size of device
890 device_size = '512MB'
891
892 # 1x32 configuration, 1 device with a 32-bit interface
893 device_bus_width = 32
894
895 # LPDDR3 is a BL8 device
896 burst_length = 8
897
898 # Each device has a page (row buffer) size of 4KB
899 device_rowbuffer_size = '4kB'
900
901 # 1x32 configuration, so 1 device
902 devices_per_rank = 1
903
904 # Technically the datasheet is a dual-rank package, but for
905 # comparison with the LPDDR2 config we stick to a single rank
906 ranks_per_channel = 1
907
908 # LPDDR3 has 8 banks in all configurations
909 banks_per_rank = 8
910
911 # 800 MHz
912 tCK = '1.25ns'
913
914 tRCD = '18ns'
915
916 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
917 tCL = '15ns'
918
919 tRAS = '42ns'
920 tWR = '15ns'
921
922 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
923 tRTP = '7.5ns'
924
925 # Pre-charge one bank 18 ns (all banks 21 ns)
926 tRP = '18ns'
927
928 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
929 # Note this is a BL8 DDR device.
930 # Requests larger than 32 bytes are broken down into multiple requests
931 # in the controller
932 tBURST = '5ns'
933
934 # LPDDR3, 4 Gb
935 tRFC = '130ns'
936 tREFI = '3.9us'
937
938 # active powerdown and precharge powerdown exit time
939 tXP = '7.5ns'
940
941 # self refresh exit time
942 tXS = '140ns'
943
944 # Irrespective of speed grade, tWTR is 7.5 ns
945 tWTR = '7.5ns'
946
947 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
948 tRTW = '2.5ns'
949
950 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
951 tCS = '2.5ns'
952
953 # Activate to activate irrespective of density and speed grade
954 tRRD = '10.0ns'
955
956 # Irrespective of size, tFAW is 50 ns
957 tXAW = '50ns'
958 activation_limit = 4
959
960 # Current values from datasheet
961 IDD0 = '8mA'
962 IDD02 = '60mA'
963 IDD2N = '0.8mA'
964 IDD2N2 = '26mA'
965 IDD3N = '2mA'
966 IDD3N2 = '34mA'
967 IDD4W = '2mA'
968 IDD4W2 = '190mA'
969 IDD4R = '2mA'
970 IDD4R2 = '230mA'
971 IDD5 = '28mA'
972 IDD52 = '150mA'
973 IDD3P1 = '1.4mA'
974 IDD3P12 = '11mA'
975 IDD2P1 = '0.8mA'
976 IDD2P12 = '1.8mA'
977 IDD6 = '0.5mA'
978 IDD62 = '1.8mA'
979 VDD = '1.8V'
980 VDD2 = '1.2V'
981
982# A single GDDR5 x64 interface, with
983# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
984# H5GQ1H24AFR) in a 2x32 configuration.
985class GDDR5_4000_2x32(DRAMCtrl):
986 # size of device
987 device_size = '128MB'
988
989 # 2x32 configuration, 1 device with a 32-bit interface
990 device_bus_width = 32
991
992 # GDDR5 is a BL8 device
993 burst_length = 8
994
995 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
996 device_rowbuffer_size = '256B'
997
998 # 2x32 configuration, so 2 devices
999 devices_per_rank = 2
1000
1001 # assume single rank
1002 ranks_per_channel = 1
1003
1004 # GDDR5 has 4 bank groups
1005 bank_groups_per_rank = 4
1006
1007 # GDDR5 has 16 banks with 4 bank groups
1008 banks_per_rank = 16
1009
1010 # 1000 MHz
1011 tCK = '1ns'
1012
1013 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
1014 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
1015 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
1016 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
1017 # With bank group architectures, tBURST represents the CAS-to-CAS
1018 # delay for bursts to different bank groups (tCCD_S)
1019 tBURST = '2ns'
1020
1021 # @1000MHz data rate, tCCD_L is 3 CK
1022 # CAS-to-CAS delay for bursts to the same bank group
1023 # tBURST is equivalent to tCCD_S; no explicit parameter required
1024 # for CAS-to-CAS delay for bursts to different bank groups
1025 tCCD_L = '3ns';
1026
1027 tRCD = '12ns'
1028
1029 # tCL is not directly found in datasheet and assumed equal tRCD
1030 tCL = '12ns'
1031
1032 tRP = '12ns'
1033 tRAS = '28ns'
1034
1035 # RRD_S (different bank group)
1036 # RRD_S is 5.5 ns in datasheet.
1037 # rounded to the next multiple of tCK
1038 tRRD = '6ns'
1039
1040 # RRD_L (same bank group)
1041 # RRD_L is 5.5 ns in datasheet.
1042 # rounded to the next multiple of tCK
1043 tRRD_L = '6ns'
1044
1045 tXAW = '23ns'
1046
1047 # tXAW < 4 x tRRD.
1048 # Therefore, activation limit is set to 0
1049 activation_limit = 0
1050
1051 tRFC = '65ns'
1052 tWR = '12ns'
1053
1054 # Here using the average of WTR_S and WTR_L
1055 tWTR = '5ns'
1056
1057 # Read-to-Precharge 2 CK
1058 tRTP = '2ns'
1059
1060 # Assume 2 cycles
1061 tRTW = '2ns'
1062
1063# A single HBM x128 interface (one command and address bus), with
1064# default timings based on data publically released
1065# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
1066# IDD measurement values, and by extrapolating data from other classes.
1067# Architecture values based on published HBM spec
1068# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
1069class HBM_1000_4H_1x128(DRAMCtrl):
1070 # HBM gen1 supports up to 8 128-bit physical channels
1071 # Configuration defines a single channel, with the capacity
1072 # set to (full_ stack_capacity / 8) based on 2Gb dies
1073 # To use all 8 channels, set 'channels' parameter to 8 in
1074 # system configuration
1075
1076 # 128-bit interface legacy mode
1077 device_bus_width = 128
1078
1079 # HBM supports BL4 and BL2 (legacy mode only)
1080 burst_length = 4
1081
1082 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
1083 # with 8 channels, 128MB per channel
1084 device_size = '128MB'
1085
1086 device_rowbuffer_size = '2kB'
1087
1088 # 1x128 configuration
1089 devices_per_rank = 1
1090
1091 # HBM does not have a CS pin; set rank to 1
1092 ranks_per_channel = 1
1093
1094 # HBM has 8 or 16 banks depending on capacity
1095 # 2Gb dies have 8 banks
1096 banks_per_rank = 8
1097
1098 # depending on frequency, bank groups may be required
1099 # will always have 4 bank groups when enabled
1100 # current specifications do not define the minimum frequency for
1101 # bank group architecture
1102 # setting bank_groups_per_rank to 0 to disable until range is defined
1103 bank_groups_per_rank = 0
1104
1105 # 500 MHz for 1Gbps DDR data rate
1106 tCK = '2ns'
1107
1108 # use values from IDD measurement in JEDEC spec
1109 # use tRP value for tRCD and tCL similar to other classes
1110 tRP = '15ns'
1111 tRCD = '15ns'
1112 tCL = '15ns'
1113 tRAS = '33ns'
1114
1115 # BL2 and BL4 supported, default to BL4
1116 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
1117 tBURST = '4ns'
1118
1119 # value for 2Gb device from JEDEC spec
1120 tRFC = '160ns'
1121
1122 # value for 2Gb device from JEDEC spec
1123 tREFI = '3.9us'
1124
1125 # extrapolate the following from LPDDR configs, using ns values
1126 # to minimize burst length, prefetch differences
1127 tWR = '18ns'
1128 tRTP = '7.5ns'
1129 tWTR = '10ns'
1130
1131 # start with 2 cycles turnaround, similar to other memory classes
1132 # could be more with variations across the stack
1133 tRTW = '4ns'
1134
1135 # single rank device, set to 0
1136 tCS = '0ns'
1137
1138 # from MemCon example, tRRD is 4ns with 2ns tCK
1139 tRRD = '4ns'
1140
1141 # from MemCon example, tFAW is 30ns with 2ns tCK
1142 tXAW = '30ns'
1143 activation_limit = 4
1144
1145 # 4tCK
1146 tXP = '8ns'
1147
1148 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1149 tXS = '168ns'
1150
1151# A single HBM x64 interface (one command and address bus), with
1152# default timings based on HBM gen1 and data publically released
1153# A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1154# Note: This defines a pseudo-channel with a unique controller
1155# instantiated per pseudo-channel
1156# Stay at same IO rate (1Gbps) to maintain timing relationship with
1157# HBM gen1 class (HBM_1000_4H_x128) where possible
1158class HBM_1000_4H_1x64(HBM_1000_4H_1x128):
1159 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1160 # Configuration defines a single pseudo channel, with the capacity
1161 # set to (full_ stack_capacity / 16) based on 8Gb dies
1162 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1163 # system configuration
1164
1165 # 64-bit pseudo-channle interface
1166 device_bus_width = 64
1167
1168 # HBM pseudo-channel only supports BL4
1169 burst_length = 4
1170
1171 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1172 # with 16 channels, 256MB per channel
1173 device_size = '256MB'
1174
1175 # page size is halved with pseudo-channel; maintaining the same same number
1176 # of rows per pseudo-channel with 2X banks across 2 channels
1177 device_rowbuffer_size = '1kB'
1178
1179 # HBM has 8 or 16 banks depending on capacity
1180 # Starting with 4Gb dies, 16 banks are defined
1181 banks_per_rank = 16
1182
1183 # reset tRFC for larger, 8Gb device
1184 # use HBM1 4Gb value as a starting point
1185 tRFC = '260ns'
1186
1187 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1188 tXS = '268ns'
1189 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1190 tCS = '2ns'
1191 tREFI = '3.9us'
1192
1193 # active powerdown and precharge powerdown exit time
1194 tXP = '10ns'
1195
1196 # self refresh exit time
1197 tXS = '65ns'
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