1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2013 Amin Farmahini-Farahani
14# Copyright (c) 2015 University of Kaiserslautern
15# Copyright (c) 2015 The University of Bologna
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Andreas Hansson
42# Ani Udipi
43# Omar Naji
44# Matthias Jung
45# Erfan Azarkhish
46
47from m5.params import *
48from AbstractMemory import *
49
50# Enum for memory scheduling algorithms, currently First-Come
51# First-Served and a First-Row Hit then First-Come First-Served
52class MemSched(Enum): vals = ['fcfs', 'frfcfs']
53
54# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
55# channel, rank, bank, row and column, respectively, and going from
56# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
57# suitable for an open-page policy, optimising for sequential accesses
58# hitting in the open row. For a closed-page policy, RoCoRaBaCh
59# maximises parallelism.
60class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
61
62# Enum for the page policy, either open, open_adaptive, close, or
63# close_adaptive.
64class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
65 'close_adaptive']
66
67# DRAMCtrl is a single-channel single-ported DRAM controller model
68# that aims to model the most important system-level performance
69# effects of a DRAM without getting into too much detail of the DRAM
70# itself.
71class DRAMCtrl(AbstractMemory):
72 type = 'DRAMCtrl'
73 cxx_header = "mem/dram_ctrl.hh"
74
75 # single-ported on the system interface side, instantiate with a
76 # bus in front of the controller for multiple ports
77 port = SlavePort("Slave port")
78
79 # the basic configuration of the controller architecture, note
80 # that each entry corresponds to a burst for the specific DRAM
81 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
82 # the cacheline size or request/packet size
83 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
84 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
85
86 # threshold in percent for when to forcefully trigger writes and
87 # start emptying the write buffer
88 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
89
90 # threshold in percentage for when to start writes if the read
91 # queue is empty
92 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
93
94 # minimum write bursts to schedule before switching back to reads
95 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
96 "switching to reads")
97
98 # scheduler, address map and page policy
99 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
100 addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
101 page_policy = Param.PageManage('open_adaptive', "Page management policy")
102
103 # enforce a limit on the number of accesses per row
104 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
105 "closing");
106
107 # size of DRAM Chip in Bytes
108 device_size = Param.MemorySize("Size of DRAM chip")
109
110 # pipeline latency of the controller and PHY, split into a
111 # frontend part and a backend part, with reads and writes serviced
112 # by the queues only seeing the frontend contribution, and reads
113 # serviced by the memory seeing the sum of the two
114 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
115 static_backend_latency = Param.Latency("10ns", "Static backend latency")
116
117 # the physical organisation of the DRAM
118 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
119 "device/chip")
120 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
121 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
122 "device/chip")
123 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
124 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
125
126 # default to 0 bank groups per rank, indicating bank group architecture
127 # is not used
128 # update per memory class when bank group architecture is supported
129 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
130 banks_per_rank = Param.Unsigned("Number of banks per rank")
131 # only used for the address mapping as the controller by
132 # construction is a single channel and multiple controllers have
133 # to be instantiated for a multi-channel configuration
134 channels = Param.Unsigned(1, "Number of channels")
135
136 # For power modelling we need to know if the DRAM has a DLL or not
137 dll = Param.Bool(True, "DRAM has DLL or not")
138
139 # DRAMPower provides in addition to the core power, the possibility to
140 # include RD/WR termination and IO power. This calculation assumes some
141 # default values. The integration of DRAMPower with gem5 does not include
142 # IO and RD/WR termination power by default. This might be added as an
143 # additional feature in the future.
144
145 # timing behaviour and constraints - all in nanoseconds
146
147 # the base clock period of the DRAM
148 tCK = Param.Latency("Clock period")
149
150 # the amount of time in nanoseconds from issuing an activate command
151 # to the data being available in the row buffer for a read/write
152 tRCD = Param.Latency("RAS to CAS delay")
153
154 # the time from issuing a read/write command to seeing the actual data
155 tCL = Param.Latency("CAS latency")
156
157 # minimum time between a precharge and subsequent activate
158 tRP = Param.Latency("Row precharge time")
159
160 # minimum time between an activate and a precharge to the same row
161 tRAS = Param.Latency("ACT to PRE delay")
162
163 # minimum time between a write data transfer and a precharge
164 tWR = Param.Latency("Write recovery time")
165
166 # minimum time between a read and precharge command
167 tRTP = Param.Latency("Read to precharge")
168
169 # time to complete a burst transfer, typically the burst length
170 # divided by two due to the DDR bus, but by making it a parameter
171 # it is easier to also evaluate SDR memories like WideIO.
172 # This parameter has to account for burst length.
173 # Read/Write requests with data size larger than one full burst are broken
174 # down into multiple requests in the controller
175 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
176 # With bank group architectures, tBURST represents the CAS-to-CAS
177 # delay for bursts to different bank groups (tCCD_S)
178 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
179
180 # CAS-to-CAS delay for bursts to the same bank group
181 # only utilized with bank group architectures; set to 0 for default case
182 # tBURST is equivalent to tCCD_S; no explicit parameter required
183 # for CAS-to-CAS delay for bursts to different bank groups
184 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
185
186 # time taken to complete one refresh cycle (N rows in all banks)
187 tRFC = Param.Latency("Refresh cycle time")
188
189 # refresh command interval, how often a "ref" command needs
190 # to be sent. It is 7.8 us for a 64ms refresh requirement
191 tREFI = Param.Latency("Refresh command interval")
192
193 # write-to-read, same rank turnaround penalty
194 tWTR = Param.Latency("Write to read, same rank switching time")
195
196 # read-to-write, same rank turnaround penalty
197 tRTW = Param.Latency("Read to write, same rank switching time")
198
199 # rank-to-rank bus delay penalty
200 # this does not correlate to a memory timing parameter and encompasses:
201 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
202 # different rank bus delay
203 tCS = Param.Latency("Rank to rank switching time")
204
205 # minimum row activate to row activate delay time
206 tRRD = Param.Latency("ACT to ACT delay")
207
208 # only utilized with bank group architectures; set to 0 for default case
209 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
210
211 # time window in which a maximum number of activates are allowed
212 # to take place, set to 0 to disable
213 tXAW = Param.Latency("X activation window")
214 activation_limit = Param.Unsigned("Max number of activates in window")
215
216 # time to exit power-down mode
217 # Exit power-down to next valid command delay
218 tXP = Param.Latency("0ns", "Power-up Delay")
219
220 # Exit Powerdown to commands requiring a locked DLL
221 tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
222
223 # time to exit self-refresh mode
224 tXS = Param.Latency("0ns", "Self-refresh exit latency")
225
226 # time to exit self-refresh mode with locked DLL
227 tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
228
229 # Currently rolled into other params
230 ######################################################################
231
232 # tRC - assumed to be tRAS + tRP
233
234 # Power Behaviour and Constraints
235 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
236 # defined as VDD and VDD2. Each current is defined for each voltage domain
237 # separately. For example, current IDD0 is active-precharge current for
238 # voltage domain VDD and current IDD02 is active-precharge current for
239 # voltage domain VDD2.
240 # By default all currents are set to 0mA. Users who are only interested in
241 # the performance of DRAMs can leave them at 0.
242
243 # Operating 1 Bank Active-Precharge current
244 IDD0 = Param.Current("0mA", "Active precharge current")
245
246 # Operating 1 Bank Active-Precharge current multiple voltage Range
247 IDD02 = Param.Current("0mA", "Active precharge current VDD2")
248
249 # Precharge Power-down Current: Slow exit
250 IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
251
252 # Precharge Power-down Current: Slow exit multiple voltage Range
253 IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
254
255 # Precharge Power-down Current: Fast exit
256 IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
257
258 # Precharge Power-down Current: Fast exit multiple voltage Range
259 IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
260
261 # Precharge Standby current
262 IDD2N = Param.Current("0mA", "Precharge Standby current")
263
264 # Precharge Standby current multiple voltage range
265 IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
266
267 # Active Power-down current: slow exit
268 IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
269
270 # Active Power-down current: slow exit multiple voltage range
271 IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
272
273 # Active Power-down current : fast exit
274 IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
275
276 # Active Power-down current : fast exit multiple voltage range
277 IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
278
279 # Active Standby current
280 IDD3N = Param.Current("0mA", "Active Standby current")
281
282 # Active Standby current multiple voltage range
283 IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
284
285 # Burst Read Operating Current
286 IDD4R = Param.Current("0mA", "READ current")
287
288 # Burst Read Operating Current multiple voltage range
289 IDD4R2 = Param.Current("0mA", "READ current VDD2")
290
291 # Burst Write Operating Current
292 IDD4W = Param.Current("0mA", "WRITE current")
293
294 # Burst Write Operating Current multiple voltage range
295 IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
296
297 # Refresh Current
298 IDD5 = Param.Current("0mA", "Refresh current")
299
300 # Refresh Current multiple voltage range
301 IDD52 = Param.Current("0mA", "Refresh current VDD2")
302
303 # Self-Refresh Current
304 IDD6 = Param.Current("0mA", "Self-refresh Current")
305
306 # Self-Refresh Current multiple voltage range
307 IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
308
309 # Main voltage range of the DRAM
310 VDD = Param.Voltage("0V", "Main Voltage Range")
311
312 # Second voltage range defined by some DRAMs
313 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
314
315# A single DDR3-1600 x64 channel (one command and address bus), with
316# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
317# an 8x8 configuration.
318class DDR3_1600_x64(DRAMCtrl):
319 # size of device in bytes
320 device_size = '512MB'
321
322 # 8x8 configuration, 8 devices each with an 8-bit interface
323 device_bus_width = 8
324
325 # DDR3 is a BL8 device
326 burst_length = 8
327
328 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
329 device_rowbuffer_size = '1kB'
330
331 # 8x8 configuration, so 8 devices
332 devices_per_rank = 8
333
334 # Use two ranks
335 ranks_per_channel = 2
336
337 # DDR3 has 8 banks in all configurations
338 banks_per_rank = 8
339
340 # 800 MHz
341 tCK = '1.25ns'
342
343 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
344 tBURST = '5ns'
345
346 # DDR3-1600 11-11-11
347 tRCD = '13.75ns'
348 tCL = '13.75ns'
349 tRP = '13.75ns'
350 tRAS = '35ns'
351 tRRD = '6ns'
352 tXAW = '30ns'
353 activation_limit = 4
354 tRFC = '260ns'
355
356 tWR = '15ns'
357
358 # Greater of 4 CK or 7.5 ns
359 tWTR = '7.5ns'
360
361 # Greater of 4 CK or 7.5 ns
362 tRTP = '7.5ns'
363
364 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
365 tRTW = '2.5ns'
366
367 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
368 tCS = '2.5ns'
369
370 # <=85C, half for >85C
371 tREFI = '7.8us'
372
| 1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2013 Amin Farmahini-Farahani
14# Copyright (c) 2015 University of Kaiserslautern
15# Copyright (c) 2015 The University of Bologna
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Andreas Hansson
42# Ani Udipi
43# Omar Naji
44# Matthias Jung
45# Erfan Azarkhish
46
47from m5.params import *
48from AbstractMemory import *
49
50# Enum for memory scheduling algorithms, currently First-Come
51# First-Served and a First-Row Hit then First-Come First-Served
52class MemSched(Enum): vals = ['fcfs', 'frfcfs']
53
54# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
55# channel, rank, bank, row and column, respectively, and going from
56# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
57# suitable for an open-page policy, optimising for sequential accesses
58# hitting in the open row. For a closed-page policy, RoCoRaBaCh
59# maximises parallelism.
60class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
61
62# Enum for the page policy, either open, open_adaptive, close, or
63# close_adaptive.
64class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
65 'close_adaptive']
66
67# DRAMCtrl is a single-channel single-ported DRAM controller model
68# that aims to model the most important system-level performance
69# effects of a DRAM without getting into too much detail of the DRAM
70# itself.
71class DRAMCtrl(AbstractMemory):
72 type = 'DRAMCtrl'
73 cxx_header = "mem/dram_ctrl.hh"
74
75 # single-ported on the system interface side, instantiate with a
76 # bus in front of the controller for multiple ports
77 port = SlavePort("Slave port")
78
79 # the basic configuration of the controller architecture, note
80 # that each entry corresponds to a burst for the specific DRAM
81 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
82 # the cacheline size or request/packet size
83 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
84 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
85
86 # threshold in percent for when to forcefully trigger writes and
87 # start emptying the write buffer
88 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
89
90 # threshold in percentage for when to start writes if the read
91 # queue is empty
92 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
93
94 # minimum write bursts to schedule before switching back to reads
95 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
96 "switching to reads")
97
98 # scheduler, address map and page policy
99 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
100 addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
101 page_policy = Param.PageManage('open_adaptive', "Page management policy")
102
103 # enforce a limit on the number of accesses per row
104 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
105 "closing");
106
107 # size of DRAM Chip in Bytes
108 device_size = Param.MemorySize("Size of DRAM chip")
109
110 # pipeline latency of the controller and PHY, split into a
111 # frontend part and a backend part, with reads and writes serviced
112 # by the queues only seeing the frontend contribution, and reads
113 # serviced by the memory seeing the sum of the two
114 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
115 static_backend_latency = Param.Latency("10ns", "Static backend latency")
116
117 # the physical organisation of the DRAM
118 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
119 "device/chip")
120 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
121 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
122 "device/chip")
123 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
124 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
125
126 # default to 0 bank groups per rank, indicating bank group architecture
127 # is not used
128 # update per memory class when bank group architecture is supported
129 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
130 banks_per_rank = Param.Unsigned("Number of banks per rank")
131 # only used for the address mapping as the controller by
132 # construction is a single channel and multiple controllers have
133 # to be instantiated for a multi-channel configuration
134 channels = Param.Unsigned(1, "Number of channels")
135
136 # For power modelling we need to know if the DRAM has a DLL or not
137 dll = Param.Bool(True, "DRAM has DLL or not")
138
139 # DRAMPower provides in addition to the core power, the possibility to
140 # include RD/WR termination and IO power. This calculation assumes some
141 # default values. The integration of DRAMPower with gem5 does not include
142 # IO and RD/WR termination power by default. This might be added as an
143 # additional feature in the future.
144
145 # timing behaviour and constraints - all in nanoseconds
146
147 # the base clock period of the DRAM
148 tCK = Param.Latency("Clock period")
149
150 # the amount of time in nanoseconds from issuing an activate command
151 # to the data being available in the row buffer for a read/write
152 tRCD = Param.Latency("RAS to CAS delay")
153
154 # the time from issuing a read/write command to seeing the actual data
155 tCL = Param.Latency("CAS latency")
156
157 # minimum time between a precharge and subsequent activate
158 tRP = Param.Latency("Row precharge time")
159
160 # minimum time between an activate and a precharge to the same row
161 tRAS = Param.Latency("ACT to PRE delay")
162
163 # minimum time between a write data transfer and a precharge
164 tWR = Param.Latency("Write recovery time")
165
166 # minimum time between a read and precharge command
167 tRTP = Param.Latency("Read to precharge")
168
169 # time to complete a burst transfer, typically the burst length
170 # divided by two due to the DDR bus, but by making it a parameter
171 # it is easier to also evaluate SDR memories like WideIO.
172 # This parameter has to account for burst length.
173 # Read/Write requests with data size larger than one full burst are broken
174 # down into multiple requests in the controller
175 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
176 # With bank group architectures, tBURST represents the CAS-to-CAS
177 # delay for bursts to different bank groups (tCCD_S)
178 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
179
180 # CAS-to-CAS delay for bursts to the same bank group
181 # only utilized with bank group architectures; set to 0 for default case
182 # tBURST is equivalent to tCCD_S; no explicit parameter required
183 # for CAS-to-CAS delay for bursts to different bank groups
184 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
185
186 # time taken to complete one refresh cycle (N rows in all banks)
187 tRFC = Param.Latency("Refresh cycle time")
188
189 # refresh command interval, how often a "ref" command needs
190 # to be sent. It is 7.8 us for a 64ms refresh requirement
191 tREFI = Param.Latency("Refresh command interval")
192
193 # write-to-read, same rank turnaround penalty
194 tWTR = Param.Latency("Write to read, same rank switching time")
195
196 # read-to-write, same rank turnaround penalty
197 tRTW = Param.Latency("Read to write, same rank switching time")
198
199 # rank-to-rank bus delay penalty
200 # this does not correlate to a memory timing parameter and encompasses:
201 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
202 # different rank bus delay
203 tCS = Param.Latency("Rank to rank switching time")
204
205 # minimum row activate to row activate delay time
206 tRRD = Param.Latency("ACT to ACT delay")
207
208 # only utilized with bank group architectures; set to 0 for default case
209 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
210
211 # time window in which a maximum number of activates are allowed
212 # to take place, set to 0 to disable
213 tXAW = Param.Latency("X activation window")
214 activation_limit = Param.Unsigned("Max number of activates in window")
215
216 # time to exit power-down mode
217 # Exit power-down to next valid command delay
218 tXP = Param.Latency("0ns", "Power-up Delay")
219
220 # Exit Powerdown to commands requiring a locked DLL
221 tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
222
223 # time to exit self-refresh mode
224 tXS = Param.Latency("0ns", "Self-refresh exit latency")
225
226 # time to exit self-refresh mode with locked DLL
227 tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
228
229 # Currently rolled into other params
230 ######################################################################
231
232 # tRC - assumed to be tRAS + tRP
233
234 # Power Behaviour and Constraints
235 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
236 # defined as VDD and VDD2. Each current is defined for each voltage domain
237 # separately. For example, current IDD0 is active-precharge current for
238 # voltage domain VDD and current IDD02 is active-precharge current for
239 # voltage domain VDD2.
240 # By default all currents are set to 0mA. Users who are only interested in
241 # the performance of DRAMs can leave them at 0.
242
243 # Operating 1 Bank Active-Precharge current
244 IDD0 = Param.Current("0mA", "Active precharge current")
245
246 # Operating 1 Bank Active-Precharge current multiple voltage Range
247 IDD02 = Param.Current("0mA", "Active precharge current VDD2")
248
249 # Precharge Power-down Current: Slow exit
250 IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
251
252 # Precharge Power-down Current: Slow exit multiple voltage Range
253 IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
254
255 # Precharge Power-down Current: Fast exit
256 IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
257
258 # Precharge Power-down Current: Fast exit multiple voltage Range
259 IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
260
261 # Precharge Standby current
262 IDD2N = Param.Current("0mA", "Precharge Standby current")
263
264 # Precharge Standby current multiple voltage range
265 IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
266
267 # Active Power-down current: slow exit
268 IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
269
270 # Active Power-down current: slow exit multiple voltage range
271 IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
272
273 # Active Power-down current : fast exit
274 IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
275
276 # Active Power-down current : fast exit multiple voltage range
277 IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
278
279 # Active Standby current
280 IDD3N = Param.Current("0mA", "Active Standby current")
281
282 # Active Standby current multiple voltage range
283 IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
284
285 # Burst Read Operating Current
286 IDD4R = Param.Current("0mA", "READ current")
287
288 # Burst Read Operating Current multiple voltage range
289 IDD4R2 = Param.Current("0mA", "READ current VDD2")
290
291 # Burst Write Operating Current
292 IDD4W = Param.Current("0mA", "WRITE current")
293
294 # Burst Write Operating Current multiple voltage range
295 IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
296
297 # Refresh Current
298 IDD5 = Param.Current("0mA", "Refresh current")
299
300 # Refresh Current multiple voltage range
301 IDD52 = Param.Current("0mA", "Refresh current VDD2")
302
303 # Self-Refresh Current
304 IDD6 = Param.Current("0mA", "Self-refresh Current")
305
306 # Self-Refresh Current multiple voltage range
307 IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
308
309 # Main voltage range of the DRAM
310 VDD = Param.Voltage("0V", "Main Voltage Range")
311
312 # Second voltage range defined by some DRAMs
313 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
314
315# A single DDR3-1600 x64 channel (one command and address bus), with
316# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
317# an 8x8 configuration.
318class DDR3_1600_x64(DRAMCtrl):
319 # size of device in bytes
320 device_size = '512MB'
321
322 # 8x8 configuration, 8 devices each with an 8-bit interface
323 device_bus_width = 8
324
325 # DDR3 is a BL8 device
326 burst_length = 8
327
328 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
329 device_rowbuffer_size = '1kB'
330
331 # 8x8 configuration, so 8 devices
332 devices_per_rank = 8
333
334 # Use two ranks
335 ranks_per_channel = 2
336
337 # DDR3 has 8 banks in all configurations
338 banks_per_rank = 8
339
340 # 800 MHz
341 tCK = '1.25ns'
342
343 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
344 tBURST = '5ns'
345
346 # DDR3-1600 11-11-11
347 tRCD = '13.75ns'
348 tCL = '13.75ns'
349 tRP = '13.75ns'
350 tRAS = '35ns'
351 tRRD = '6ns'
352 tXAW = '30ns'
353 activation_limit = 4
354 tRFC = '260ns'
355
356 tWR = '15ns'
357
358 # Greater of 4 CK or 7.5 ns
359 tWTR = '7.5ns'
360
361 # Greater of 4 CK or 7.5 ns
362 tRTP = '7.5ns'
363
364 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
365 tRTW = '2.5ns'
366
367 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
368 tCS = '2.5ns'
369
370 # <=85C, half for >85C
371 tREFI = '7.8us'
372
|
662 # Irrespective of speed grade, tWTR is 7.5 ns
663 tWTR = '7.5ns'
664
665 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
666 tRTW = '3.75ns'
667
668 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
669 tCS = '3.75ns'
670
671 # Activate to activate irrespective of density and speed grade
672 tRRD = '10.0ns'
673
674 # Irrespective of density, tFAW is 50 ns
675 tXAW = '50ns'
676 activation_limit = 4
677
678 # Current values from datasheet
679 IDD0 = '15mA'
680 IDD02 = '70mA'
681 IDD2N = '2mA'
682 IDD2N2 = '30mA'
683 IDD3N = '2.5mA'
684 IDD3N2 = '30mA'
685 IDD4W = '10mA'
686 IDD4W2 = '190mA'
687 IDD4R = '3mA'
688 IDD4R2 = '220mA'
689 IDD5 = '40mA'
690 IDD52 = '150mA'
691 VDD = '1.8V'
692 VDD2 = '1.2V'
693
694# A single WideIO x128 interface (one command and address bus), with
695# default timings based on an estimated WIO-200 8 Gbit part.
696class WideIO_200_x128(DRAMCtrl):
697 # No DLL for WideIO
698 dll = False
699
700 # size of device
701 device_size = '1024MB'
702
703 # 1x128 configuration, 1 device with a 128-bit interface
704 device_bus_width = 128
705
706 # This is a BL4 device
707 burst_length = 4
708
709 # Each device has a page (row buffer) size of 4KB
710 # (this depends on the memory density)
711 device_rowbuffer_size = '4kB'
712
713 # 1x128 configuration, so 1 device
714 devices_per_rank = 1
715
716 # Use one rank for a one-high die stack
717 ranks_per_channel = 1
718
719 # WideIO has 4 banks in all configurations
720 banks_per_rank = 4
721
722 # 200 MHz
723 tCK = '5ns'
724
725 # WIO-200
726 tRCD = '18ns'
727 tCL = '18ns'
728 tRP = '18ns'
729 tRAS = '42ns'
730 tWR = '15ns'
731 # Read to precharge is same as the burst
732 tRTP = '20ns'
733
734 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
735 # Note this is a BL4 SDR device.
736 tBURST = '20ns'
737
738 # WIO 8 Gb
739 tRFC = '210ns'
740
741 # WIO 8 Gb, <=85C, half for >85C
742 tREFI = '3.9us'
743
744 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
745 tWTR = '15ns'
746
747 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
748 tRTW = '10ns'
749
750 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
751 tCS = '10ns'
752
753 # Activate to activate irrespective of density and speed grade
754 tRRD = '10.0ns'
755
756 # Two instead of four activation window
757 tXAW = '50ns'
758 activation_limit = 2
759
760 # The WideIO specification does not provide current information
761
762# A single LPDDR3 x32 interface (one command/address bus), with
763# default timings based on a LPDDR3-1600 4 Gbit part (Micron
764# EDF8132A1MC) in a 1x32 configuration.
765class LPDDR3_1600_x32(DRAMCtrl):
766 # No DLL for LPDDR3
767 dll = False
768
769 # size of device
770 device_size = '512MB'
771
772 # 1x32 configuration, 1 device with a 32-bit interface
773 device_bus_width = 32
774
775 # LPDDR3 is a BL8 device
776 burst_length = 8
777
778 # Each device has a page (row buffer) size of 4KB
779 device_rowbuffer_size = '4kB'
780
781 # 1x32 configuration, so 1 device
782 devices_per_rank = 1
783
784 # Technically the datasheet is a dual-rank package, but for
785 # comparison with the LPDDR2 config we stick to a single rank
786 ranks_per_channel = 1
787
788 # LPDDR3 has 8 banks in all configurations
789 banks_per_rank = 8
790
791 # 800 MHz
792 tCK = '1.25ns'
793
794 tRCD = '18ns'
795
796 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
797 tCL = '15ns'
798
799 tRAS = '42ns'
800 tWR = '15ns'
801
802 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
803 tRTP = '7.5ns'
804
805 # Pre-charge one bank 18 ns (all banks 21 ns)
806 tRP = '18ns'
807
808 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
809 # Note this is a BL8 DDR device.
810 # Requests larger than 32 bytes are broken down into multiple requests
811 # in the controller
812 tBURST = '5ns'
813
814 # LPDDR3, 4 Gb
815 tRFC = '130ns'
816 tREFI = '3.9us'
817
| 680 # Irrespective of speed grade, tWTR is 7.5 ns
681 tWTR = '7.5ns'
682
683 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
684 tRTW = '3.75ns'
685
686 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
687 tCS = '3.75ns'
688
689 # Activate to activate irrespective of density and speed grade
690 tRRD = '10.0ns'
691
692 # Irrespective of density, tFAW is 50 ns
693 tXAW = '50ns'
694 activation_limit = 4
695
696 # Current values from datasheet
697 IDD0 = '15mA'
698 IDD02 = '70mA'
699 IDD2N = '2mA'
700 IDD2N2 = '30mA'
701 IDD3N = '2.5mA'
702 IDD3N2 = '30mA'
703 IDD4W = '10mA'
704 IDD4W2 = '190mA'
705 IDD4R = '3mA'
706 IDD4R2 = '220mA'
707 IDD5 = '40mA'
708 IDD52 = '150mA'
709 VDD = '1.8V'
710 VDD2 = '1.2V'
711
712# A single WideIO x128 interface (one command and address bus), with
713# default timings based on an estimated WIO-200 8 Gbit part.
714class WideIO_200_x128(DRAMCtrl):
715 # No DLL for WideIO
716 dll = False
717
718 # size of device
719 device_size = '1024MB'
720
721 # 1x128 configuration, 1 device with a 128-bit interface
722 device_bus_width = 128
723
724 # This is a BL4 device
725 burst_length = 4
726
727 # Each device has a page (row buffer) size of 4KB
728 # (this depends on the memory density)
729 device_rowbuffer_size = '4kB'
730
731 # 1x128 configuration, so 1 device
732 devices_per_rank = 1
733
734 # Use one rank for a one-high die stack
735 ranks_per_channel = 1
736
737 # WideIO has 4 banks in all configurations
738 banks_per_rank = 4
739
740 # 200 MHz
741 tCK = '5ns'
742
743 # WIO-200
744 tRCD = '18ns'
745 tCL = '18ns'
746 tRP = '18ns'
747 tRAS = '42ns'
748 tWR = '15ns'
749 # Read to precharge is same as the burst
750 tRTP = '20ns'
751
752 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
753 # Note this is a BL4 SDR device.
754 tBURST = '20ns'
755
756 # WIO 8 Gb
757 tRFC = '210ns'
758
759 # WIO 8 Gb, <=85C, half for >85C
760 tREFI = '3.9us'
761
762 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
763 tWTR = '15ns'
764
765 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
766 tRTW = '10ns'
767
768 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
769 tCS = '10ns'
770
771 # Activate to activate irrespective of density and speed grade
772 tRRD = '10.0ns'
773
774 # Two instead of four activation window
775 tXAW = '50ns'
776 activation_limit = 2
777
778 # The WideIO specification does not provide current information
779
780# A single LPDDR3 x32 interface (one command/address bus), with
781# default timings based on a LPDDR3-1600 4 Gbit part (Micron
782# EDF8132A1MC) in a 1x32 configuration.
783class LPDDR3_1600_x32(DRAMCtrl):
784 # No DLL for LPDDR3
785 dll = False
786
787 # size of device
788 device_size = '512MB'
789
790 # 1x32 configuration, 1 device with a 32-bit interface
791 device_bus_width = 32
792
793 # LPDDR3 is a BL8 device
794 burst_length = 8
795
796 # Each device has a page (row buffer) size of 4KB
797 device_rowbuffer_size = '4kB'
798
799 # 1x32 configuration, so 1 device
800 devices_per_rank = 1
801
802 # Technically the datasheet is a dual-rank package, but for
803 # comparison with the LPDDR2 config we stick to a single rank
804 ranks_per_channel = 1
805
806 # LPDDR3 has 8 banks in all configurations
807 banks_per_rank = 8
808
809 # 800 MHz
810 tCK = '1.25ns'
811
812 tRCD = '18ns'
813
814 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
815 tCL = '15ns'
816
817 tRAS = '42ns'
818 tWR = '15ns'
819
820 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
821 tRTP = '7.5ns'
822
823 # Pre-charge one bank 18 ns (all banks 21 ns)
824 tRP = '18ns'
825
826 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
827 # Note this is a BL8 DDR device.
828 # Requests larger than 32 bytes are broken down into multiple requests
829 # in the controller
830 tBURST = '5ns'
831
832 # LPDDR3, 4 Gb
833 tRFC = '130ns'
834 tREFI = '3.9us'
835
|
818 # Irrespective of speed grade, tWTR is 7.5 ns
819 tWTR = '7.5ns'
820
821 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
822 tRTW = '2.5ns'
823
824 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
825 tCS = '2.5ns'
826
827 # Activate to activate irrespective of density and speed grade
828 tRRD = '10.0ns'
829
830 # Irrespective of size, tFAW is 50 ns
831 tXAW = '50ns'
832 activation_limit = 4
833
834 # Current values from datasheet
835 IDD0 = '8mA'
836 IDD02 = '60mA'
837 IDD2N = '0.8mA'
838 IDD2N2 = '26mA'
839 IDD3N = '2mA'
840 IDD3N2 = '34mA'
841 IDD4W = '2mA'
842 IDD4W2 = '190mA'
843 IDD4R = '2mA'
844 IDD4R2 = '230mA'
845 IDD5 = '28mA'
846 IDD52 = '150mA'
847 VDD = '1.8V'
848 VDD2 = '1.2V'
849
850# A single GDDR5 x64 interface, with
851# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
852# H5GQ1H24AFR) in a 2x32 configuration.
853class GDDR5_4000_x64(DRAMCtrl):
854 # size of device
855 device_size = '128MB'
856
857 # 2x32 configuration, 1 device with a 32-bit interface
858 device_bus_width = 32
859
860 # GDDR5 is a BL8 device
861 burst_length = 8
862
863 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
864 device_rowbuffer_size = '256B'
865
866 # 2x32 configuration, so 2 devices
867 devices_per_rank = 2
868
869 # assume single rank
870 ranks_per_channel = 1
871
872 # GDDR5 has 4 bank groups
873 bank_groups_per_rank = 4
874
875 # GDDR5 has 16 banks with 4 bank groups
876 banks_per_rank = 16
877
878 # 1000 MHz
879 tCK = '1ns'
880
881 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
882 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
883 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
884 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
885 # With bank group architectures, tBURST represents the CAS-to-CAS
886 # delay for bursts to different bank groups (tCCD_S)
887 tBURST = '2ns'
888
889 # @1000MHz data rate, tCCD_L is 3 CK
890 # CAS-to-CAS delay for bursts to the same bank group
891 # tBURST is equivalent to tCCD_S; no explicit parameter required
892 # for CAS-to-CAS delay for bursts to different bank groups
893 tCCD_L = '3ns';
894
895 tRCD = '12ns'
896
897 # tCL is not directly found in datasheet and assumed equal tRCD
898 tCL = '12ns'
899
900 tRP = '12ns'
901 tRAS = '28ns'
902
903 # RRD_S (different bank group)
904 # RRD_S is 5.5 ns in datasheet.
905 # rounded to the next multiple of tCK
906 tRRD = '6ns'
907
908 # RRD_L (same bank group)
909 # RRD_L is 5.5 ns in datasheet.
910 # rounded to the next multiple of tCK
911 tRRD_L = '6ns'
912
913 tXAW = '23ns'
914
915 # tXAW < 4 x tRRD.
916 # Therefore, activation limit is set to 0
917 activation_limit = 0
918
919 tRFC = '65ns'
920 tWR = '12ns'
921
922 # Here using the average of WTR_S and WTR_L
923 tWTR = '5ns'
924
925 # Read-to-Precharge 2 CK
926 tRTP = '2ns'
927
928 # Assume 2 cycles
929 tRTW = '2ns'
930
931# A single HBM x128 interface (one command and address bus), with
932# default timings based on data publically released
933# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
934# IDD measurement values, and by extrapolating data from other classes.
935# Architecture values based on published HBM spec
936# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
937class HBM_1000_4H_x128(DRAMCtrl):
938 # HBM gen1 supports up to 8 128-bit physical channels
939 # Configuration defines a single channel, with the capacity
940 # set to (full_ stack_capacity / 8) based on 2Gb dies
941 # To use all 8 channels, set 'channels' parameter to 8 in
942 # system configuration
943
944 # 128-bit interface legacy mode
945 device_bus_width = 128
946
947 # HBM supports BL4 and BL2 (legacy mode only)
948 burst_length = 4
949
950 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
951 # with 8 channels, 128MB per channel
952 device_size = '128MB'
953
954 device_rowbuffer_size = '2kB'
955
956 # 1x128 configuration
957 devices_per_rank = 1
958
959 # HBM does not have a CS pin; set rank to 1
960 ranks_per_channel = 1
961
962 # HBM has 8 or 16 banks depending on capacity
963 # 2Gb dies have 8 banks
964 banks_per_rank = 8
965
966 # depending on frequency, bank groups may be required
967 # will always have 4 bank groups when enabled
968 # current specifications do not define the minimum frequency for
969 # bank group architecture
970 # setting bank_groups_per_rank to 0 to disable until range is defined
971 bank_groups_per_rank = 0
972
973 # 500 MHz for 1Gbps DDR data rate
974 tCK = '2ns'
975
976 # use values from IDD measurement in JEDEC spec
977 # use tRP value for tRCD and tCL similar to other classes
978 tRP = '15ns'
979 tRCD = '15ns'
980 tCL = '15ns'
981 tRAS = '33ns'
982
983 # BL2 and BL4 supported, default to BL4
984 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
985 tBURST = '4ns'
986
987 # value for 2Gb device from JEDEC spec
988 tRFC = '160ns'
989
990 # value for 2Gb device from JEDEC spec
991 tREFI = '3.9us'
992
993 # extrapolate the following from LPDDR configs, using ns values
994 # to minimize burst length, prefetch differences
995 tWR = '18ns'
996 tRTP = '7.5ns'
997 tWTR = '10ns'
998
999 # start with 2 cycles turnaround, similar to other memory classes
1000 # could be more with variations across the stack
1001 tRTW = '4ns'
1002
1003 # single rank device, set to 0
1004 tCS = '0ns'
1005
1006 # from MemCon example, tRRD is 4ns with 2ns tCK
1007 tRRD = '4ns'
1008
1009 # from MemCon example, tFAW is 30ns with 2ns tCK
1010 tXAW = '30ns'
1011 activation_limit = 4
1012
1013 # 4tCK
1014 tXP = '8ns'
1015
1016 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1017 tXS = '168ns'
1018
1019# A single HBM x64 interface (one command and address bus), with
1020# default timings based on HBM gen1 and data publically released
1021# A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1022# Note: This defines a pseudo-channel with a unique controller
1023# instantiated per pseudo-channel
1024# Stay at same IO rate (1Gbps) to maintain timing relationship with
1025# HBM gen1 class (HBM_1000_4H_x128) where possible
1026class HBM_1000_4H_x64(HBM_1000_4H_x128):
1027 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1028 # Configuration defines a single pseudo channel, with the capacity
1029 # set to (full_ stack_capacity / 16) based on 8Gb dies
1030 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1031 # system configuration
1032
1033 # 64-bit pseudo-channle interface
1034 device_bus_width = 64
1035
1036 # HBM pseudo-channel only supports BL4
1037 burst_length = 4
1038
1039 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1040 # with 16 channels, 256MB per channel
1041 device_size = '256MB'
1042
1043 # page size is halved with pseudo-channel; maintaining the same same number
1044 # of rows per pseudo-channel with 2X banks across 2 channels
1045 device_rowbuffer_size = '1kB'
1046
1047 # HBM has 8 or 16 banks depending on capacity
1048 # Starting with 4Gb dies, 16 banks are defined
1049 banks_per_rank = 16
1050
1051 # reset tRFC for larger, 8Gb device
1052 # use HBM1 4Gb value as a starting point
1053 tRFC = '260ns'
1054
1055 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1056 tXS = '268ns'
1057 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1058 tCS = '2ns'
1059 tREFI = '3.9us'
| 842 # Irrespective of speed grade, tWTR is 7.5 ns
843 tWTR = '7.5ns'
844
845 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
846 tRTW = '2.5ns'
847
848 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
849 tCS = '2.5ns'
850
851 # Activate to activate irrespective of density and speed grade
852 tRRD = '10.0ns'
853
854 # Irrespective of size, tFAW is 50 ns
855 tXAW = '50ns'
856 activation_limit = 4
857
858 # Current values from datasheet
859 IDD0 = '8mA'
860 IDD02 = '60mA'
861 IDD2N = '0.8mA'
862 IDD2N2 = '26mA'
863 IDD3N = '2mA'
864 IDD3N2 = '34mA'
865 IDD4W = '2mA'
866 IDD4W2 = '190mA'
867 IDD4R = '2mA'
868 IDD4R2 = '230mA'
869 IDD5 = '28mA'
870 IDD52 = '150mA'
871 VDD = '1.8V'
872 VDD2 = '1.2V'
873
874# A single GDDR5 x64 interface, with
875# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
876# H5GQ1H24AFR) in a 2x32 configuration.
877class GDDR5_4000_x64(DRAMCtrl):
878 # size of device
879 device_size = '128MB'
880
881 # 2x32 configuration, 1 device with a 32-bit interface
882 device_bus_width = 32
883
884 # GDDR5 is a BL8 device
885 burst_length = 8
886
887 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
888 device_rowbuffer_size = '256B'
889
890 # 2x32 configuration, so 2 devices
891 devices_per_rank = 2
892
893 # assume single rank
894 ranks_per_channel = 1
895
896 # GDDR5 has 4 bank groups
897 bank_groups_per_rank = 4
898
899 # GDDR5 has 16 banks with 4 bank groups
900 banks_per_rank = 16
901
902 # 1000 MHz
903 tCK = '1ns'
904
905 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
906 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
907 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
908 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
909 # With bank group architectures, tBURST represents the CAS-to-CAS
910 # delay for bursts to different bank groups (tCCD_S)
911 tBURST = '2ns'
912
913 # @1000MHz data rate, tCCD_L is 3 CK
914 # CAS-to-CAS delay for bursts to the same bank group
915 # tBURST is equivalent to tCCD_S; no explicit parameter required
916 # for CAS-to-CAS delay for bursts to different bank groups
917 tCCD_L = '3ns';
918
919 tRCD = '12ns'
920
921 # tCL is not directly found in datasheet and assumed equal tRCD
922 tCL = '12ns'
923
924 tRP = '12ns'
925 tRAS = '28ns'
926
927 # RRD_S (different bank group)
928 # RRD_S is 5.5 ns in datasheet.
929 # rounded to the next multiple of tCK
930 tRRD = '6ns'
931
932 # RRD_L (same bank group)
933 # RRD_L is 5.5 ns in datasheet.
934 # rounded to the next multiple of tCK
935 tRRD_L = '6ns'
936
937 tXAW = '23ns'
938
939 # tXAW < 4 x tRRD.
940 # Therefore, activation limit is set to 0
941 activation_limit = 0
942
943 tRFC = '65ns'
944 tWR = '12ns'
945
946 # Here using the average of WTR_S and WTR_L
947 tWTR = '5ns'
948
949 # Read-to-Precharge 2 CK
950 tRTP = '2ns'
951
952 # Assume 2 cycles
953 tRTW = '2ns'
954
955# A single HBM x128 interface (one command and address bus), with
956# default timings based on data publically released
957# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
958# IDD measurement values, and by extrapolating data from other classes.
959# Architecture values based on published HBM spec
960# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
961class HBM_1000_4H_x128(DRAMCtrl):
962 # HBM gen1 supports up to 8 128-bit physical channels
963 # Configuration defines a single channel, with the capacity
964 # set to (full_ stack_capacity / 8) based on 2Gb dies
965 # To use all 8 channels, set 'channels' parameter to 8 in
966 # system configuration
967
968 # 128-bit interface legacy mode
969 device_bus_width = 128
970
971 # HBM supports BL4 and BL2 (legacy mode only)
972 burst_length = 4
973
974 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
975 # with 8 channels, 128MB per channel
976 device_size = '128MB'
977
978 device_rowbuffer_size = '2kB'
979
980 # 1x128 configuration
981 devices_per_rank = 1
982
983 # HBM does not have a CS pin; set rank to 1
984 ranks_per_channel = 1
985
986 # HBM has 8 or 16 banks depending on capacity
987 # 2Gb dies have 8 banks
988 banks_per_rank = 8
989
990 # depending on frequency, bank groups may be required
991 # will always have 4 bank groups when enabled
992 # current specifications do not define the minimum frequency for
993 # bank group architecture
994 # setting bank_groups_per_rank to 0 to disable until range is defined
995 bank_groups_per_rank = 0
996
997 # 500 MHz for 1Gbps DDR data rate
998 tCK = '2ns'
999
1000 # use values from IDD measurement in JEDEC spec
1001 # use tRP value for tRCD and tCL similar to other classes
1002 tRP = '15ns'
1003 tRCD = '15ns'
1004 tCL = '15ns'
1005 tRAS = '33ns'
1006
1007 # BL2 and BL4 supported, default to BL4
1008 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
1009 tBURST = '4ns'
1010
1011 # value for 2Gb device from JEDEC spec
1012 tRFC = '160ns'
1013
1014 # value for 2Gb device from JEDEC spec
1015 tREFI = '3.9us'
1016
1017 # extrapolate the following from LPDDR configs, using ns values
1018 # to minimize burst length, prefetch differences
1019 tWR = '18ns'
1020 tRTP = '7.5ns'
1021 tWTR = '10ns'
1022
1023 # start with 2 cycles turnaround, similar to other memory classes
1024 # could be more with variations across the stack
1025 tRTW = '4ns'
1026
1027 # single rank device, set to 0
1028 tCS = '0ns'
1029
1030 # from MemCon example, tRRD is 4ns with 2ns tCK
1031 tRRD = '4ns'
1032
1033 # from MemCon example, tFAW is 30ns with 2ns tCK
1034 tXAW = '30ns'
1035 activation_limit = 4
1036
1037 # 4tCK
1038 tXP = '8ns'
1039
1040 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1041 tXS = '168ns'
1042
1043# A single HBM x64 interface (one command and address bus), with
1044# default timings based on HBM gen1 and data publically released
1045# A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1046# Note: This defines a pseudo-channel with a unique controller
1047# instantiated per pseudo-channel
1048# Stay at same IO rate (1Gbps) to maintain timing relationship with
1049# HBM gen1 class (HBM_1000_4H_x128) where possible
1050class HBM_1000_4H_x64(HBM_1000_4H_x128):
1051 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1052 # Configuration defines a single pseudo channel, with the capacity
1053 # set to (full_ stack_capacity / 16) based on 8Gb dies
1054 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1055 # system configuration
1056
1057 # 64-bit pseudo-channle interface
1058 device_bus_width = 64
1059
1060 # HBM pseudo-channel only supports BL4
1061 burst_length = 4
1062
1063 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1064 # with 16 channels, 256MB per channel
1065 device_size = '256MB'
1066
1067 # page size is halved with pseudo-channel; maintaining the same same number
1068 # of rows per pseudo-channel with 2X banks across 2 channels
1069 device_rowbuffer_size = '1kB'
1070
1071 # HBM has 8 or 16 banks depending on capacity
1072 # Starting with 4Gb dies, 16 banks are defined
1073 banks_per_rank = 16
1074
1075 # reset tRFC for larger, 8Gb device
1076 # use HBM1 4Gb value as a starting point
1077 tRFC = '260ns'
1078
1079 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1080 tXS = '268ns'
1081 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1082 tCS = '2ns'
1083 tREFI = '3.9us'
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