1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2013 Amin Farmahini-Farahani
14# Copyright (c) 2015 University of Kaiserslautern
| 1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2013 Amin Farmahini-Farahani
14# Copyright (c) 2015 University of Kaiserslautern
|
| 15# Copyright (c) 2015 The University of Bologna
|
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Andreas Hansson
41# Ani Udipi
42# Omar Naji
43# Matthias Jung
| 16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Andreas Hansson
42# Ani Udipi
43# Omar Naji
44# Matthias Jung
|
| 45# Erfan Azarkhish
|
44
45from m5.params import *
46from AbstractMemory import *
47
48# Enum for memory scheduling algorithms, currently First-Come
49# First-Served and a First-Row Hit then First-Come First-Served
50class MemSched(Enum): vals = ['fcfs', 'frfcfs']
51
52# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
53# channel, rank, bank, row and column, respectively, and going from
54# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
55# suitable for an open-page policy, optimising for sequential accesses
56# hitting in the open row. For a closed-page policy, RoCoRaBaCh
57# maximises parallelism.
58class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
59
60# Enum for the page policy, either open, open_adaptive, close, or
61# close_adaptive.
62class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
63 'close_adaptive']
64
65# DRAMCtrl is a single-channel single-ported DRAM controller model
66# that aims to model the most important system-level performance
67# effects of a DRAM without getting into too much detail of the DRAM
68# itself.
69class DRAMCtrl(AbstractMemory):
70 type = 'DRAMCtrl'
71 cxx_header = "mem/dram_ctrl.hh"
72
73 # single-ported on the system interface side, instantiate with a
74 # bus in front of the controller for multiple ports
75 port = SlavePort("Slave port")
76
77 # the basic configuration of the controller architecture, note
78 # that each entry corresponds to a burst for the specific DRAM
79 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
80 # the cacheline size or request/packet size
81 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
82 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
83
84 # threshold in percent for when to forcefully trigger writes and
85 # start emptying the write buffer
86 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
87
88 # threshold in percentage for when to start writes if the read
89 # queue is empty
90 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
91
92 # minimum write bursts to schedule before switching back to reads
93 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
94 "switching to reads")
95
96 # scheduler, address map and page policy
97 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
98 addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
99 page_policy = Param.PageManage('open_adaptive', "Page management policy")
100
101 # enforce a limit on the number of accesses per row
102 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
103 "closing");
104
105 # size of DRAM Chip in Bytes
106 device_size = Param.MemorySize("Size of DRAM chip")
107
108 # pipeline latency of the controller and PHY, split into a
109 # frontend part and a backend part, with reads and writes serviced
110 # by the queues only seeing the frontend contribution, and reads
111 # serviced by the memory seeing the sum of the two
112 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
113 static_backend_latency = Param.Latency("10ns", "Static backend latency")
114
115 # the physical organisation of the DRAM
116 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
117 "device/chip")
118 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
119 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
120 "device/chip")
121 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
122 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
123
124 # default to 0 bank groups per rank, indicating bank group architecture
125 # is not used
126 # update per memory class when bank group architecture is supported
127 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
128 banks_per_rank = Param.Unsigned("Number of banks per rank")
129 # only used for the address mapping as the controller by
130 # construction is a single channel and multiple controllers have
131 # to be instantiated for a multi-channel configuration
132 channels = Param.Unsigned(1, "Number of channels")
133
134 # For power modelling we need to know if the DRAM has a DLL or not
135 dll = Param.Bool(True, "DRAM has DLL or not")
136
137 # DRAMPower provides in addition to the core power, the possibility to
138 # include RD/WR termination and IO power. This calculation assumes some
139 # default values. The integration of DRAMPower with gem5 does not include
140 # IO and RD/WR termination power by default. This might be added as an
141 # additional feature in the future.
142
143 # timing behaviour and constraints - all in nanoseconds
144
145 # the base clock period of the DRAM
146 tCK = Param.Latency("Clock period")
147
148 # the amount of time in nanoseconds from issuing an activate command
149 # to the data being available in the row buffer for a read/write
150 tRCD = Param.Latency("RAS to CAS delay")
151
152 # the time from issuing a read/write command to seeing the actual data
153 tCL = Param.Latency("CAS latency")
154
155 # minimum time between a precharge and subsequent activate
156 tRP = Param.Latency("Row precharge time")
157
158 # minimum time between an activate and a precharge to the same row
159 tRAS = Param.Latency("ACT to PRE delay")
160
161 # minimum time between a write data transfer and a precharge
162 tWR = Param.Latency("Write recovery time")
163
164 # minimum time between a read and precharge command
165 tRTP = Param.Latency("Read to precharge")
166
167 # time to complete a burst transfer, typically the burst length
168 # divided by two due to the DDR bus, but by making it a parameter
169 # it is easier to also evaluate SDR memories like WideIO.
170 # This parameter has to account for burst length.
171 # Read/Write requests with data size larger than one full burst are broken
172 # down into multiple requests in the controller
173 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
174 # With bank group architectures, tBURST represents the CAS-to-CAS
175 # delay for bursts to different bank groups (tCCD_S)
176 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
177
178 # CAS-to-CAS delay for bursts to the same bank group
179 # only utilized with bank group architectures; set to 0 for default case
180 # tBURST is equivalent to tCCD_S; no explicit parameter required
181 # for CAS-to-CAS delay for bursts to different bank groups
182 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
183
184 # time taken to complete one refresh cycle (N rows in all banks)
185 tRFC = Param.Latency("Refresh cycle time")
186
187 # refresh command interval, how often a "ref" command needs
188 # to be sent. It is 7.8 us for a 64ms refresh requirement
189 tREFI = Param.Latency("Refresh command interval")
190
191 # write-to-read, same rank turnaround penalty
192 tWTR = Param.Latency("Write to read, same rank switching time")
193
194 # read-to-write, same rank turnaround penalty
195 tRTW = Param.Latency("Read to write, same rank switching time")
196
197 # rank-to-rank bus delay penalty
198 # this does not correlate to a memory timing parameter and encompasses:
199 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
200 # different rank bus delay
201 tCS = Param.Latency("Rank to rank switching time")
202
203 # minimum row activate to row activate delay time
204 tRRD = Param.Latency("ACT to ACT delay")
205
206 # only utilized with bank group architectures; set to 0 for default case
207 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
208
209 # time window in which a maximum number of activates are allowed
210 # to take place, set to 0 to disable
211 tXAW = Param.Latency("X activation window")
212 activation_limit = Param.Unsigned("Max number of activates in window")
213
214 # time to exit power-down mode
215 # Exit power-down to next valid command delay
216 tXP = Param.Latency("0ns", "Power-up Delay")
217
218 # Exit Powerdown to commands requiring a locked DLL
219 tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
220
221 # time to exit self-refresh mode
222 tXS = Param.Latency("0ns", "Self-refresh exit latency")
223
224 # time to exit self-refresh mode with locked DLL
225 tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
226
227 # Currently rolled into other params
228 ######################################################################
229
230 # tRC - assumed to be tRAS + tRP
231
232 # Power Behaviour and Constraints
233 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
234 # defined as VDD and VDD2. Each current is defined for each voltage domain
235 # separately. For example, current IDD0 is active-precharge current for
236 # voltage domain VDD and current IDD02 is active-precharge current for
237 # voltage domain VDD2.
238 # By default all currents are set to 0mA. Users who are only interested in
239 # the performance of DRAMs can leave them at 0.
240
241 # Operating 1 Bank Active-Precharge current
242 IDD0 = Param.Current("0mA", "Active precharge current")
243
244 # Operating 1 Bank Active-Precharge current multiple voltage Range
245 IDD02 = Param.Current("0mA", "Active precharge current VDD2")
246
247 # Precharge Power-down Current: Slow exit
248 IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
249
250 # Precharge Power-down Current: Slow exit multiple voltage Range
251 IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
252
253 # Precharge Power-down Current: Fast exit
254 IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
255
256 # Precharge Power-down Current: Fast exit multiple voltage Range
257 IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
258
259 # Precharge Standby current
260 IDD2N = Param.Current("0mA", "Precharge Standby current")
261
262 # Precharge Standby current multiple voltage range
263 IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
264
265 # Active Power-down current: slow exit
266 IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
267
268 # Active Power-down current: slow exit multiple voltage range
269 IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
270
271 # Active Power-down current : fast exit
272 IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
273
274 # Active Power-down current : fast exit multiple voltage range
275 IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
276
277 # Active Standby current
278 IDD3N = Param.Current("0mA", "Active Standby current")
279
280 # Active Standby current multiple voltage range
281 IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
282
283 # Burst Read Operating Current
284 IDD4R = Param.Current("0mA", "READ current")
285
286 # Burst Read Operating Current multiple voltage range
287 IDD4R2 = Param.Current("0mA", "READ current VDD2")
288
289 # Burst Write Operating Current
290 IDD4W = Param.Current("0mA", "WRITE current")
291
292 # Burst Write Operating Current multiple voltage range
293 IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
294
295 # Refresh Current
296 IDD5 = Param.Current("0mA", "Refresh current")
297
298 # Refresh Current multiple voltage range
299 IDD52 = Param.Current("0mA", "Refresh current VDD2")
300
301 # Self-Refresh Current
302 IDD6 = Param.Current("0mA", "Self-refresh Current")
303
304 # Self-Refresh Current multiple voltage range
305 IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
306
307 # Main voltage range of the DRAM
308 VDD = Param.Voltage("0V", "Main Voltage Range")
309
310 # Second voltage range defined by some DRAMs
311 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
312
313# A single DDR3-1600 x64 channel (one command and address bus), with
314# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
315# an 8x8 configuration.
316class DDR3_1600_x64(DRAMCtrl):
317 # size of device in bytes
318 device_size = '512MB'
319
320 # 8x8 configuration, 8 devices each with an 8-bit interface
321 device_bus_width = 8
322
323 # DDR3 is a BL8 device
324 burst_length = 8
325
326 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
327 device_rowbuffer_size = '1kB'
328
329 # 8x8 configuration, so 8 devices
330 devices_per_rank = 8
331
332 # Use two ranks
333 ranks_per_channel = 2
334
335 # DDR3 has 8 banks in all configurations
336 banks_per_rank = 8
337
338 # 800 MHz
339 tCK = '1.25ns'
340
341 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
342 tBURST = '5ns'
343
344 # DDR3-1600 11-11-11
345 tRCD = '13.75ns'
346 tCL = '13.75ns'
347 tRP = '13.75ns'
348 tRAS = '35ns'
349 tRRD = '6ns'
350 tXAW = '30ns'
351 activation_limit = 4
352 tRFC = '260ns'
353
354 tWR = '15ns'
355
356 # Greater of 4 CK or 7.5 ns
357 tWTR = '7.5ns'
358
359 # Greater of 4 CK or 7.5 ns
360 tRTP = '7.5ns'
361
362 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
363 tRTW = '2.5ns'
364
365 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
366 tCS = '2.5ns'
367
368 # <=85C, half for >85C
369 tREFI = '7.8us'
370
371 # Current values from datasheet
372 IDD0 = '75mA'
373 IDD2N = '50mA'
374 IDD3N = '57mA'
375 IDD4W = '165mA'
376 IDD4R = '187mA'
377 IDD5 = '220mA'
378 VDD = '1.5V'
379
380# A single HMC-2500 x32 model based on:
381# [1] DRAMSpec: a high-level DRAM bank modelling tool
382# developed at the University of Kaiserslautern. This high level tool
383# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
384# estimate the DRAM bank latency and power numbers.
| 46
47from m5.params import *
48from AbstractMemory import *
49
50# Enum for memory scheduling algorithms, currently First-Come
51# First-Served and a First-Row Hit then First-Come First-Served
52class MemSched(Enum): vals = ['fcfs', 'frfcfs']
53
54# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
55# channel, rank, bank, row and column, respectively, and going from
56# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
57# suitable for an open-page policy, optimising for sequential accesses
58# hitting in the open row. For a closed-page policy, RoCoRaBaCh
59# maximises parallelism.
60class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
61
62# Enum for the page policy, either open, open_adaptive, close, or
63# close_adaptive.
64class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
65 'close_adaptive']
66
67# DRAMCtrl is a single-channel single-ported DRAM controller model
68# that aims to model the most important system-level performance
69# effects of a DRAM without getting into too much detail of the DRAM
70# itself.
71class DRAMCtrl(AbstractMemory):
72 type = 'DRAMCtrl'
73 cxx_header = "mem/dram_ctrl.hh"
74
75 # single-ported on the system interface side, instantiate with a
76 # bus in front of the controller for multiple ports
77 port = SlavePort("Slave port")
78
79 # the basic configuration of the controller architecture, note
80 # that each entry corresponds to a burst for the specific DRAM
81 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
82 # the cacheline size or request/packet size
83 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
84 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
85
86 # threshold in percent for when to forcefully trigger writes and
87 # start emptying the write buffer
88 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
89
90 # threshold in percentage for when to start writes if the read
91 # queue is empty
92 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
93
94 # minimum write bursts to schedule before switching back to reads
95 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
96 "switching to reads")
97
98 # scheduler, address map and page policy
99 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
100 addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
101 page_policy = Param.PageManage('open_adaptive', "Page management policy")
102
103 # enforce a limit on the number of accesses per row
104 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
105 "closing");
106
107 # size of DRAM Chip in Bytes
108 device_size = Param.MemorySize("Size of DRAM chip")
109
110 # pipeline latency of the controller and PHY, split into a
111 # frontend part and a backend part, with reads and writes serviced
112 # by the queues only seeing the frontend contribution, and reads
113 # serviced by the memory seeing the sum of the two
114 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
115 static_backend_latency = Param.Latency("10ns", "Static backend latency")
116
117 # the physical organisation of the DRAM
118 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
119 "device/chip")
120 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
121 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
122 "device/chip")
123 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
124 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
125
126 # default to 0 bank groups per rank, indicating bank group architecture
127 # is not used
128 # update per memory class when bank group architecture is supported
129 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
130 banks_per_rank = Param.Unsigned("Number of banks per rank")
131 # only used for the address mapping as the controller by
132 # construction is a single channel and multiple controllers have
133 # to be instantiated for a multi-channel configuration
134 channels = Param.Unsigned(1, "Number of channels")
135
136 # For power modelling we need to know if the DRAM has a DLL or not
137 dll = Param.Bool(True, "DRAM has DLL or not")
138
139 # DRAMPower provides in addition to the core power, the possibility to
140 # include RD/WR termination and IO power. This calculation assumes some
141 # default values. The integration of DRAMPower with gem5 does not include
142 # IO and RD/WR termination power by default. This might be added as an
143 # additional feature in the future.
144
145 # timing behaviour and constraints - all in nanoseconds
146
147 # the base clock period of the DRAM
148 tCK = Param.Latency("Clock period")
149
150 # the amount of time in nanoseconds from issuing an activate command
151 # to the data being available in the row buffer for a read/write
152 tRCD = Param.Latency("RAS to CAS delay")
153
154 # the time from issuing a read/write command to seeing the actual data
155 tCL = Param.Latency("CAS latency")
156
157 # minimum time between a precharge and subsequent activate
158 tRP = Param.Latency("Row precharge time")
159
160 # minimum time between an activate and a precharge to the same row
161 tRAS = Param.Latency("ACT to PRE delay")
162
163 # minimum time between a write data transfer and a precharge
164 tWR = Param.Latency("Write recovery time")
165
166 # minimum time between a read and precharge command
167 tRTP = Param.Latency("Read to precharge")
168
169 # time to complete a burst transfer, typically the burst length
170 # divided by two due to the DDR bus, but by making it a parameter
171 # it is easier to also evaluate SDR memories like WideIO.
172 # This parameter has to account for burst length.
173 # Read/Write requests with data size larger than one full burst are broken
174 # down into multiple requests in the controller
175 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
176 # With bank group architectures, tBURST represents the CAS-to-CAS
177 # delay for bursts to different bank groups (tCCD_S)
178 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
179
180 # CAS-to-CAS delay for bursts to the same bank group
181 # only utilized with bank group architectures; set to 0 for default case
182 # tBURST is equivalent to tCCD_S; no explicit parameter required
183 # for CAS-to-CAS delay for bursts to different bank groups
184 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
185
186 # time taken to complete one refresh cycle (N rows in all banks)
187 tRFC = Param.Latency("Refresh cycle time")
188
189 # refresh command interval, how often a "ref" command needs
190 # to be sent. It is 7.8 us for a 64ms refresh requirement
191 tREFI = Param.Latency("Refresh command interval")
192
193 # write-to-read, same rank turnaround penalty
194 tWTR = Param.Latency("Write to read, same rank switching time")
195
196 # read-to-write, same rank turnaround penalty
197 tRTW = Param.Latency("Read to write, same rank switching time")
198
199 # rank-to-rank bus delay penalty
200 # this does not correlate to a memory timing parameter and encompasses:
201 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
202 # different rank bus delay
203 tCS = Param.Latency("Rank to rank switching time")
204
205 # minimum row activate to row activate delay time
206 tRRD = Param.Latency("ACT to ACT delay")
207
208 # only utilized with bank group architectures; set to 0 for default case
209 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
210
211 # time window in which a maximum number of activates are allowed
212 # to take place, set to 0 to disable
213 tXAW = Param.Latency("X activation window")
214 activation_limit = Param.Unsigned("Max number of activates in window")
215
216 # time to exit power-down mode
217 # Exit power-down to next valid command delay
218 tXP = Param.Latency("0ns", "Power-up Delay")
219
220 # Exit Powerdown to commands requiring a locked DLL
221 tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
222
223 # time to exit self-refresh mode
224 tXS = Param.Latency("0ns", "Self-refresh exit latency")
225
226 # time to exit self-refresh mode with locked DLL
227 tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
228
229 # Currently rolled into other params
230 ######################################################################
231
232 # tRC - assumed to be tRAS + tRP
233
234 # Power Behaviour and Constraints
235 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
236 # defined as VDD and VDD2. Each current is defined for each voltage domain
237 # separately. For example, current IDD0 is active-precharge current for
238 # voltage domain VDD and current IDD02 is active-precharge current for
239 # voltage domain VDD2.
240 # By default all currents are set to 0mA. Users who are only interested in
241 # the performance of DRAMs can leave them at 0.
242
243 # Operating 1 Bank Active-Precharge current
244 IDD0 = Param.Current("0mA", "Active precharge current")
245
246 # Operating 1 Bank Active-Precharge current multiple voltage Range
247 IDD02 = Param.Current("0mA", "Active precharge current VDD2")
248
249 # Precharge Power-down Current: Slow exit
250 IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
251
252 # Precharge Power-down Current: Slow exit multiple voltage Range
253 IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
254
255 # Precharge Power-down Current: Fast exit
256 IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
257
258 # Precharge Power-down Current: Fast exit multiple voltage Range
259 IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
260
261 # Precharge Standby current
262 IDD2N = Param.Current("0mA", "Precharge Standby current")
263
264 # Precharge Standby current multiple voltage range
265 IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
266
267 # Active Power-down current: slow exit
268 IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
269
270 # Active Power-down current: slow exit multiple voltage range
271 IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
272
273 # Active Power-down current : fast exit
274 IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
275
276 # Active Power-down current : fast exit multiple voltage range
277 IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
278
279 # Active Standby current
280 IDD3N = Param.Current("0mA", "Active Standby current")
281
282 # Active Standby current multiple voltage range
283 IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
284
285 # Burst Read Operating Current
286 IDD4R = Param.Current("0mA", "READ current")
287
288 # Burst Read Operating Current multiple voltage range
289 IDD4R2 = Param.Current("0mA", "READ current VDD2")
290
291 # Burst Write Operating Current
292 IDD4W = Param.Current("0mA", "WRITE current")
293
294 # Burst Write Operating Current multiple voltage range
295 IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
296
297 # Refresh Current
298 IDD5 = Param.Current("0mA", "Refresh current")
299
300 # Refresh Current multiple voltage range
301 IDD52 = Param.Current("0mA", "Refresh current VDD2")
302
303 # Self-Refresh Current
304 IDD6 = Param.Current("0mA", "Self-refresh Current")
305
306 # Self-Refresh Current multiple voltage range
307 IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
308
309 # Main voltage range of the DRAM
310 VDD = Param.Voltage("0V", "Main Voltage Range")
311
312 # Second voltage range defined by some DRAMs
313 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
314
315# A single DDR3-1600 x64 channel (one command and address bus), with
316# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
317# an 8x8 configuration.
318class DDR3_1600_x64(DRAMCtrl):
319 # size of device in bytes
320 device_size = '512MB'
321
322 # 8x8 configuration, 8 devices each with an 8-bit interface
323 device_bus_width = 8
324
325 # DDR3 is a BL8 device
326 burst_length = 8
327
328 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
329 device_rowbuffer_size = '1kB'
330
331 # 8x8 configuration, so 8 devices
332 devices_per_rank = 8
333
334 # Use two ranks
335 ranks_per_channel = 2
336
337 # DDR3 has 8 banks in all configurations
338 banks_per_rank = 8
339
340 # 800 MHz
341 tCK = '1.25ns'
342
343 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
344 tBURST = '5ns'
345
346 # DDR3-1600 11-11-11
347 tRCD = '13.75ns'
348 tCL = '13.75ns'
349 tRP = '13.75ns'
350 tRAS = '35ns'
351 tRRD = '6ns'
352 tXAW = '30ns'
353 activation_limit = 4
354 tRFC = '260ns'
355
356 tWR = '15ns'
357
358 # Greater of 4 CK or 7.5 ns
359 tWTR = '7.5ns'
360
361 # Greater of 4 CK or 7.5 ns
362 tRTP = '7.5ns'
363
364 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
365 tRTW = '2.5ns'
366
367 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
368 tCS = '2.5ns'
369
370 # <=85C, half for >85C
371 tREFI = '7.8us'
372
373 # Current values from datasheet
374 IDD0 = '75mA'
375 IDD2N = '50mA'
376 IDD3N = '57mA'
377 IDD4W = '165mA'
378 IDD4R = '187mA'
379 IDD5 = '220mA'
380 VDD = '1.5V'
381
382# A single HMC-2500 x32 model based on:
383# [1] DRAMSpec: a high-level DRAM bank modelling tool
384# developed at the University of Kaiserslautern. This high level tool
385# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
386# estimate the DRAM bank latency and power numbers.
|
385# [2] A Logic-base Interconnect for Supporting Near Memory Computation in the
386# Hybrid Memory Cube (E. Azarkhish et. al)
| 387# [2] High performance AXI-4.0 based interconnect for extensible smart memory
388# cubes (E. Azarkhish et. al)
|
387# Assumed for the HMC model is a 30 nm technology node.
388# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
389# layers).
390# Each layer has 16 vaults and each vault consists of 2 banks per layer.
391# In order to be able to use the same controller used for 2D DRAM generations
392# for HMC, the following analogy is done:
393# Channel (DDR) => Vault (HMC)
394# device_size (DDR) => size of a single layer in a vault
395# ranks per channel (DDR) => number of layers
396# banks per rank (DDR) => banks per layer
397# devices per rank (DDR) => devices per layer ( 1 for HMC).
398# The parameters for which no input is available are inherited from the DDR3
399# configuration.
| 389# Assumed for the HMC model is a 30 nm technology node.
390# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
391# layers).
392# Each layer has 16 vaults and each vault consists of 2 banks per layer.
393# In order to be able to use the same controller used for 2D DRAM generations
394# for HMC, the following analogy is done:
395# Channel (DDR) => Vault (HMC)
396# device_size (DDR) => size of a single layer in a vault
397# ranks per channel (DDR) => number of layers
398# banks per rank (DDR) => banks per layer
399# devices per rank (DDR) => devices per layer ( 1 for HMC).
400# The parameters for which no input is available are inherited from the DDR3
401# configuration.
|
400# This configuration includes the latencies from the DRAM to the logic layer of
401# the HMC
| 402# This configuration includes the latencies from the DRAM to the logic layer
403# of the HMC
|
402class HMC_2500_x32(DDR3_1600_x64):
403 # size of device
404 # two banks per device with each bank 4MB [2]
405 device_size = '8MB'
406
407 # 1x32 configuration, 1 device with 32 TSVs [2]
408 device_bus_width = 32
409
410 # HMC is a BL8 device [2]
411 burst_length = 8
412
413 # Each device has a page (row buffer) size of 256 bytes [2]
414 device_rowbuffer_size = '256B'
415
416 # 1x32 configuration, so 1 device [2]
417 devices_per_rank = 1
418
419 # 4 layers so 4 ranks [2]
420 ranks_per_channel = 4
421
422 # HMC has 2 banks per layer [2]
423 # Each layer represents a rank. With 4 layers and 8 banks in total, each
424 # layer has 2 banks; thus 2 banks per rank.
425 banks_per_rank = 2
426
427 # 1250 MHz [2]
428 tCK = '0.8ns'
429
430 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
431 tBURST = '3.2ns'
432
433 # Values using DRAMSpec HMC model [1]
434 tRCD = '10.2ns'
435 tCL = '9.9ns'
436 tRP = '7.7ns'
437 tRAS = '21.6ns'
438
439 # tRRD depends on the power supply network for each vendor.
440 # We assume a tRRD of a double bank approach to be equal to 4 clock
441 # cycles (Assumption)
442 tRRD = '3.2ns'
443
| 404class HMC_2500_x32(DDR3_1600_x64):
405 # size of device
406 # two banks per device with each bank 4MB [2]
407 device_size = '8MB'
408
409 # 1x32 configuration, 1 device with 32 TSVs [2]
410 device_bus_width = 32
411
412 # HMC is a BL8 device [2]
413 burst_length = 8
414
415 # Each device has a page (row buffer) size of 256 bytes [2]
416 device_rowbuffer_size = '256B'
417
418 # 1x32 configuration, so 1 device [2]
419 devices_per_rank = 1
420
421 # 4 layers so 4 ranks [2]
422 ranks_per_channel = 4
423
424 # HMC has 2 banks per layer [2]
425 # Each layer represents a rank. With 4 layers and 8 banks in total, each
426 # layer has 2 banks; thus 2 banks per rank.
427 banks_per_rank = 2
428
429 # 1250 MHz [2]
430 tCK = '0.8ns'
431
432 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
433 tBURST = '3.2ns'
434
435 # Values using DRAMSpec HMC model [1]
436 tRCD = '10.2ns'
437 tCL = '9.9ns'
438 tRP = '7.7ns'
439 tRAS = '21.6ns'
440
441 # tRRD depends on the power supply network for each vendor.
442 # We assume a tRRD of a double bank approach to be equal to 4 clock
443 # cycles (Assumption)
444 tRRD = '3.2ns'
445
|
444 # activation limit is set to 0 since there are only 2 banks per vault layer.
| 446 # activation limit is set to 0 since there are only 2 banks per vault
447 # layer.
|
445 activation_limit = 0
446
447 # Values using DRAMSpec HMC model [1]
448 tRFC = '59ns'
449 tWR = '8ns'
450 tRTP = '4.9ns'
451
| 448 activation_limit = 0
449
450 # Values using DRAMSpec HMC model [1]
451 tRFC = '59ns'
452 tWR = '8ns'
453 tRTP = '4.9ns'
454
|
452 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz = 0.8
453 # ns (Assumption)
| 455 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
456 # 0.8 ns (Assumption)
|
454 tCS = '0.8ns'
455
456 # Value using DRAMSpec HMC model [1]
457 tREFI = '3.9us'
458
| 457 tCS = '0.8ns'
458
459 # Value using DRAMSpec HMC model [1]
460 tREFI = '3.9us'
461
|
459 # Set default controller parameters
460 page_policy = 'close'
461 write_buffer_size = 8
462 read_buffer_size = 8
| 462 # The default page policy in the vault controllers is simple closed page
463 # [2] nevertheless 'close' policy opens and closes the row multiple times
464 # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
465 page_policy = 'close_adaptive'
466
467 # RoCoRaBaCh resembles the default address mapping in HMC
|
463 addr_mapping = 'RoCoRaBaCh'
464 min_writes_per_switch = 8
465
| 468 addr_mapping = 'RoCoRaBaCh'
469 min_writes_per_switch = 8
470
|
| 471 # These parameters do not directly correlate with buffer_size in real
472 # hardware. Nevertheless, their value has been tuned to achieve a
473 # bandwidth similar to the cycle-accurate model in [2]
474 write_buffer_size = 32
475 read_buffer_size = 32
476
477 # The static latency of the vault controllers is estimated to be smaller
478 # than a full DRAM channel controller
479 static_backend_latency='4ns'
480 static_frontend_latency='4ns'
481
|
466# A single DDR3-2133 x64 channel refining a selected subset of the
467# options for the DDR-1600 configuration, based on the same DDR3-1600
468# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
469# consistent across the two configurations.
470class DDR3_2133_x64(DDR3_1600_x64):
471 # 1066 MHz
472 tCK = '0.938ns'
473
474 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
475 tBURST = '3.752ns'
476
477 # DDR3-2133 14-14-14
478 tRCD = '13.09ns'
479 tCL = '13.09ns'
480 tRP = '13.09ns'
481 tRAS = '33ns'
482 tRRD = '5ns'
483 tXAW = '25ns'
484
485 # Current values from datasheet
486 IDD0 = '70mA'
487 IDD2N = '37mA'
488 IDD3N = '44mA'
489 IDD4W = '157mA'
490 IDD4R = '191mA'
491 IDD5 = '250mA'
492 VDD = '1.5V'
493
494# A single DDR4-2400 x64 channel (one command and address bus), with
495# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8)
496# in an 8x8 configuration.
497class DDR4_2400_x64(DRAMCtrl):
498 # size of device
499 device_size = '512MB'
500
501 # 8x8 configuration, 8 devices each with an 8-bit interface
502 device_bus_width = 8
503
504 # DDR4 is a BL8 device
505 burst_length = 8
506
507 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
508 device_rowbuffer_size = '1kB'
509
510 # 8x8 configuration, so 8 devices
511 devices_per_rank = 8
512
513 # Match our DDR3 configurations which is dual rank
514 ranks_per_channel = 2
515
516 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
517 # Set to 4 for x4, x8 case
518 bank_groups_per_rank = 4
519
520 # DDR4 has 16 banks (4 bank groups) in all
521 # configurations. Currently we do not capture the additional
522 # constraints incurred by the bank groups
523 banks_per_rank = 16
524
525 # override the default buffer sizes and go for something larger to
526 # accommodate the larger bank count
527 write_buffer_size = 128
528 read_buffer_size = 64
529
530 # 1200 MHz
531 tCK = '0.833ns'
532
533 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
534 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
535 # With bank group architectures, tBURST represents the CAS-to-CAS
536 # delay for bursts to different bank groups (tCCD_S)
537 tBURST = '3.333ns'
538
539 # @2400 data rate, tCCD_L is 6 CK
540 # CAS-to-CAS delay for bursts to the same bank group
541 # tBURST is equivalent to tCCD_S; no explicit parameter required
542 # for CAS-to-CAS delay for bursts to different bank groups
543 tCCD_L = '5ns';
544
545 # DDR4-2400 17-17-17
546 tRCD = '14.16ns'
547 tCL = '14.16ns'
548 tRP = '14.16ns'
549 tRAS = '32ns'
550
551 # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
552 tRRD = '3.3ns'
553
554 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
555 tRRD_L = '4.9ns';
556
557 tXAW = '21ns'
558 activation_limit = 4
559 tRFC = '350ns'
560
561 tWR = '15ns'
562
563 # Here using the average of WTR_S and WTR_L
564 tWTR = '5ns'
565
566 # Greater of 4 CK or 7.5 ns
567 tRTP = '7.5ns'
568
569 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
570 tRTW = '1.666ns'
571
572 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
573 tCS = '1.666ns'
574
575 # <=85C, half for >85C
576 tREFI = '7.8us'
577
578 # Current values from datasheet
579 IDD0 = '64mA'
580 IDD02 = '4mA'
581 IDD2N = '50mA'
582 IDD3N = '67mA'
583 IDD3N2 = '3mA'
584 IDD4W = '180mA'
585 IDD4R = '160mA'
586 IDD5 = '192mA'
587 VDD = '1.2V'
588 VDD2 = '2.5V'
589
590# A single LPDDR2-S4 x32 interface (one command/address bus), with
591# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
592# in a 1x32 configuration.
593class LPDDR2_S4_1066_x32(DRAMCtrl):
594 # No DLL in LPDDR2
595 dll = False
596
597 # size of device
598 device_size = '512MB'
599
600 # 1x32 configuration, 1 device with a 32-bit interface
601 device_bus_width = 32
602
603 # LPDDR2_S4 is a BL4 and BL8 device
604 burst_length = 8
605
606 # Each device has a page (row buffer) size of 1KB
607 # (this depends on the memory density)
608 device_rowbuffer_size = '1kB'
609
610 # 1x32 configuration, so 1 device
611 devices_per_rank = 1
612
613 # Use a single rank
614 ranks_per_channel = 1
615
616 # LPDDR2-S4 has 8 banks in all configurations
617 banks_per_rank = 8
618
619 # 533 MHz
620 tCK = '1.876ns'
621
622 # Fixed at 15 ns
623 tRCD = '15ns'
624
625 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
626 tCL = '15ns'
627
628 # Pre-charge one bank 15 ns (all banks 18 ns)
629 tRP = '15ns'
630
631 tRAS = '42ns'
632 tWR = '15ns'
633
634 tRTP = '7.5ns'
635
636 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
637 # Note this is a BL8 DDR device.
638 # Requests larger than 32 bytes are broken down into multiple requests
639 # in the controller
640 tBURST = '7.5ns'
641
642 # LPDDR2-S4, 4 Gbit
643 tRFC = '130ns'
644 tREFI = '3.9us'
645
646 # Irrespective of speed grade, tWTR is 7.5 ns
647 tWTR = '7.5ns'
648
649 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
650 tRTW = '3.75ns'
651
652 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
653 tCS = '3.75ns'
654
655 # Activate to activate irrespective of density and speed grade
656 tRRD = '10.0ns'
657
658 # Irrespective of density, tFAW is 50 ns
659 tXAW = '50ns'
660 activation_limit = 4
661
662 # Current values from datasheet
663 IDD0 = '15mA'
664 IDD02 = '70mA'
665 IDD2N = '2mA'
666 IDD2N2 = '30mA'
667 IDD3N = '2.5mA'
668 IDD3N2 = '30mA'
669 IDD4W = '10mA'
670 IDD4W2 = '190mA'
671 IDD4R = '3mA'
672 IDD4R2 = '220mA'
673 IDD5 = '40mA'
674 IDD52 = '150mA'
675 VDD = '1.8V'
676 VDD2 = '1.2V'
677
678# A single WideIO x128 interface (one command and address bus), with
679# default timings based on an estimated WIO-200 8 Gbit part.
680class WideIO_200_x128(DRAMCtrl):
681 # No DLL for WideIO
682 dll = False
683
684 # size of device
685 device_size = '1024MB'
686
687 # 1x128 configuration, 1 device with a 128-bit interface
688 device_bus_width = 128
689
690 # This is a BL4 device
691 burst_length = 4
692
693 # Each device has a page (row buffer) size of 4KB
694 # (this depends on the memory density)
695 device_rowbuffer_size = '4kB'
696
697 # 1x128 configuration, so 1 device
698 devices_per_rank = 1
699
700 # Use one rank for a one-high die stack
701 ranks_per_channel = 1
702
703 # WideIO has 4 banks in all configurations
704 banks_per_rank = 4
705
706 # 200 MHz
707 tCK = '5ns'
708
709 # WIO-200
710 tRCD = '18ns'
711 tCL = '18ns'
712 tRP = '18ns'
713 tRAS = '42ns'
714 tWR = '15ns'
715 # Read to precharge is same as the burst
716 tRTP = '20ns'
717
718 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
719 # Note this is a BL4 SDR device.
720 tBURST = '20ns'
721
722 # WIO 8 Gb
723 tRFC = '210ns'
724
725 # WIO 8 Gb, <=85C, half for >85C
726 tREFI = '3.9us'
727
728 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
729 tWTR = '15ns'
730
731 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
732 tRTW = '10ns'
733
734 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
735 tCS = '10ns'
736
737 # Activate to activate irrespective of density and speed grade
738 tRRD = '10.0ns'
739
740 # Two instead of four activation window
741 tXAW = '50ns'
742 activation_limit = 2
743
744 # The WideIO specification does not provide current information
745
746# A single LPDDR3 x32 interface (one command/address bus), with
747# default timings based on a LPDDR3-1600 4 Gbit part (Micron
748# EDF8132A1MC) in a 1x32 configuration.
749class LPDDR3_1600_x32(DRAMCtrl):
750 # No DLL for LPDDR3
751 dll = False
752
753 # size of device
754 device_size = '512MB'
755
756 # 1x32 configuration, 1 device with a 32-bit interface
757 device_bus_width = 32
758
759 # LPDDR3 is a BL8 device
760 burst_length = 8
761
762 # Each device has a page (row buffer) size of 4KB
763 device_rowbuffer_size = '4kB'
764
765 # 1x32 configuration, so 1 device
766 devices_per_rank = 1
767
768 # Technically the datasheet is a dual-rank package, but for
769 # comparison with the LPDDR2 config we stick to a single rank
770 ranks_per_channel = 1
771
772 # LPDDR3 has 8 banks in all configurations
773 banks_per_rank = 8
774
775 # 800 MHz
776 tCK = '1.25ns'
777
778 tRCD = '18ns'
779
780 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
781 tCL = '15ns'
782
783 tRAS = '42ns'
784 tWR = '15ns'
785
786 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
787 tRTP = '7.5ns'
788
789 # Pre-charge one bank 18 ns (all banks 21 ns)
790 tRP = '18ns'
791
792 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
793 # Note this is a BL8 DDR device.
794 # Requests larger than 32 bytes are broken down into multiple requests
795 # in the controller
796 tBURST = '5ns'
797
798 # LPDDR3, 4 Gb
799 tRFC = '130ns'
800 tREFI = '3.9us'
801
802 # Irrespective of speed grade, tWTR is 7.5 ns
803 tWTR = '7.5ns'
804
805 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
806 tRTW = '2.5ns'
807
808 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
809 tCS = '2.5ns'
810
811 # Activate to activate irrespective of density and speed grade
812 tRRD = '10.0ns'
813
814 # Irrespective of size, tFAW is 50 ns
815 tXAW = '50ns'
816 activation_limit = 4
817
818 # Current values from datasheet
819 IDD0 = '8mA'
820 IDD02 = '60mA'
821 IDD2N = '0.8mA'
822 IDD2N2 = '26mA'
823 IDD3N = '2mA'
824 IDD3N2 = '34mA'
825 IDD4W = '2mA'
826 IDD4W2 = '190mA'
827 IDD4R = '2mA'
828 IDD4R2 = '230mA'
829 IDD5 = '28mA'
830 IDD52 = '150mA'
831 VDD = '1.8V'
832 VDD2 = '1.2V'
833
834# A single GDDR5 x64 interface, with
835# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
836# H5GQ1H24AFR) in a 2x32 configuration.
837class GDDR5_4000_x64(DRAMCtrl):
838 # size of device
839 device_size = '128MB'
840
841 # 2x32 configuration, 1 device with a 32-bit interface
842 device_bus_width = 32
843
844 # GDDR5 is a BL8 device
845 burst_length = 8
846
847 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
848 device_rowbuffer_size = '256B'
849
850 # 2x32 configuration, so 2 devices
851 devices_per_rank = 2
852
853 # assume single rank
854 ranks_per_channel = 1
855
856 # GDDR5 has 4 bank groups
857 bank_groups_per_rank = 4
858
859 # GDDR5 has 16 banks with 4 bank groups
860 banks_per_rank = 16
861
862 # 1000 MHz
863 tCK = '1ns'
864
865 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
866 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
867 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
868 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
869 # With bank group architectures, tBURST represents the CAS-to-CAS
870 # delay for bursts to different bank groups (tCCD_S)
871 tBURST = '2ns'
872
873 # @1000MHz data rate, tCCD_L is 3 CK
874 # CAS-to-CAS delay for bursts to the same bank group
875 # tBURST is equivalent to tCCD_S; no explicit parameter required
876 # for CAS-to-CAS delay for bursts to different bank groups
877 tCCD_L = '3ns';
878
879 tRCD = '12ns'
880
881 # tCL is not directly found in datasheet and assumed equal tRCD
882 tCL = '12ns'
883
884 tRP = '12ns'
885 tRAS = '28ns'
886
887 # RRD_S (different bank group)
888 # RRD_S is 5.5 ns in datasheet.
889 # rounded to the next multiple of tCK
890 tRRD = '6ns'
891
892 # RRD_L (same bank group)
893 # RRD_L is 5.5 ns in datasheet.
894 # rounded to the next multiple of tCK
895 tRRD_L = '6ns'
896
897 tXAW = '23ns'
898
899 # tXAW < 4 x tRRD.
900 # Therefore, activation limit is set to 0
901 activation_limit = 0
902
903 tRFC = '65ns'
904 tWR = '12ns'
905
906 # Here using the average of WTR_S and WTR_L
907 tWTR = '5ns'
908
909 # Read-to-Precharge 2 CK
910 tRTP = '2ns'
911
912 # Assume 2 cycles
913 tRTW = '2ns'
914
915# A single HBM x128 interface (one command and address bus), with
916# default timings based on data publically released
917# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
918# IDD measurement values, and by extrapolating data from other classes.
919# Architecture values based on published HBM spec
920# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
921class HBM_1000_4H_x128(DRAMCtrl):
922 # HBM gen1 supports up to 8 128-bit physical channels
923 # Configuration defines a single channel, with the capacity
924 # set to (full_ stack_capacity / 8) based on 2Gb dies
925 # To use all 8 channels, set 'channels' parameter to 8 in
926 # system configuration
927
928 # 128-bit interface legacy mode
929 device_bus_width = 128
930
931 # HBM supports BL4 and BL2 (legacy mode only)
932 burst_length = 4
933
934 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
935 # with 8 channels, 128MB per channel
936 device_size = '128MB'
937
938 device_rowbuffer_size = '2kB'
939
940 # 1x128 configuration
941 devices_per_rank = 1
942
943 # HBM does not have a CS pin; set rank to 1
944 ranks_per_channel = 1
945
946 # HBM has 8 or 16 banks depending on capacity
947 # 2Gb dies have 8 banks
948 banks_per_rank = 8
949
950 # depending on frequency, bank groups may be required
951 # will always have 4 bank groups when enabled
952 # current specifications do not define the minimum frequency for
953 # bank group architecture
954 # setting bank_groups_per_rank to 0 to disable until range is defined
955 bank_groups_per_rank = 0
956
957 # 500 MHz for 1Gbps DDR data rate
958 tCK = '2ns'
959
960 # use values from IDD measurement in JEDEC spec
961 # use tRP value for tRCD and tCL similar to other classes
962 tRP = '15ns'
963 tRCD = '15ns'
964 tCL = '15ns'
965 tRAS = '33ns'
966
967 # BL2 and BL4 supported, default to BL4
968 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
969 tBURST = '4ns'
970
971 # value for 2Gb device from JEDEC spec
972 tRFC = '160ns'
973
974 # value for 2Gb device from JEDEC spec
975 tREFI = '3.9us'
976
977 # extrapolate the following from LPDDR configs, using ns values
978 # to minimize burst length, prefetch differences
979 tWR = '18ns'
980 tRTP = '7.5ns'
981 tWTR = '10ns'
982
983 # start with 2 cycles turnaround, similar to other memory classes
984 # could be more with variations across the stack
985 tRTW = '4ns'
986
987 # single rank device, set to 0
988 tCS = '0ns'
989
990 # from MemCon example, tRRD is 4ns with 2ns tCK
991 tRRD = '4ns'
992
993 # from MemCon example, tFAW is 30ns with 2ns tCK
994 tXAW = '30ns'
995 activation_limit = 4
996
997 # 4tCK
998 tXP = '8ns'
999
1000 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1001 tXS = '168ns'
1002
1003# A single HBM x64 interface (one command and address bus), with
1004# default timings based on HBM gen1 and data publically released
1005# A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1006# Note: This defines a pseudo-channel with a unique controller
1007# instantiated per pseudo-channel
1008# Stay at same IO rate (1Gbps) to maintain timing relationship with
1009# HBM gen1 class (HBM_1000_4H_x128) where possible
1010class HBM_1000_4H_x64(HBM_1000_4H_x128):
1011 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1012 # Configuration defines a single pseudo channel, with the capacity
1013 # set to (full_ stack_capacity / 16) based on 8Gb dies
1014 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1015 # system configuration
1016
1017 # 64-bit pseudo-channle interface
1018 device_bus_width = 64
1019
1020 # HBM pseudo-channel only supports BL4
1021 burst_length = 4
1022
1023 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1024 # with 16 channels, 256MB per channel
1025 device_size = '256MB'
1026
1027 # page size is halved with pseudo-channel; maintaining the same same number
1028 # of rows per pseudo-channel with 2X banks across 2 channels
1029 device_rowbuffer_size = '1kB'
1030
1031 # HBM has 8 or 16 banks depending on capacity
1032 # Starting with 4Gb dies, 16 banks are defined
1033 banks_per_rank = 16
1034
1035 # reset tRFC for larger, 8Gb device
1036 # use HBM1 4Gb value as a starting point
1037 tRFC = '260ns'
1038
1039 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1040 tXS = '268ns'
1041 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1042 tCS = '2ns'
1043 tREFI = '3.9us'
| 482# A single DDR3-2133 x64 channel refining a selected subset of the
483# options for the DDR-1600 configuration, based on the same DDR3-1600
484# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
485# consistent across the two configurations.
486class DDR3_2133_x64(DDR3_1600_x64):
487 # 1066 MHz
488 tCK = '0.938ns'
489
490 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
491 tBURST = '3.752ns'
492
493 # DDR3-2133 14-14-14
494 tRCD = '13.09ns'
495 tCL = '13.09ns'
496 tRP = '13.09ns'
497 tRAS = '33ns'
498 tRRD = '5ns'
499 tXAW = '25ns'
500
501 # Current values from datasheet
502 IDD0 = '70mA'
503 IDD2N = '37mA'
504 IDD3N = '44mA'
505 IDD4W = '157mA'
506 IDD4R = '191mA'
507 IDD5 = '250mA'
508 VDD = '1.5V'
509
510# A single DDR4-2400 x64 channel (one command and address bus), with
511# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8)
512# in an 8x8 configuration.
513class DDR4_2400_x64(DRAMCtrl):
514 # size of device
515 device_size = '512MB'
516
517 # 8x8 configuration, 8 devices each with an 8-bit interface
518 device_bus_width = 8
519
520 # DDR4 is a BL8 device
521 burst_length = 8
522
523 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
524 device_rowbuffer_size = '1kB'
525
526 # 8x8 configuration, so 8 devices
527 devices_per_rank = 8
528
529 # Match our DDR3 configurations which is dual rank
530 ranks_per_channel = 2
531
532 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
533 # Set to 4 for x4, x8 case
534 bank_groups_per_rank = 4
535
536 # DDR4 has 16 banks (4 bank groups) in all
537 # configurations. Currently we do not capture the additional
538 # constraints incurred by the bank groups
539 banks_per_rank = 16
540
541 # override the default buffer sizes and go for something larger to
542 # accommodate the larger bank count
543 write_buffer_size = 128
544 read_buffer_size = 64
545
546 # 1200 MHz
547 tCK = '0.833ns'
548
549 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
550 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
551 # With bank group architectures, tBURST represents the CAS-to-CAS
552 # delay for bursts to different bank groups (tCCD_S)
553 tBURST = '3.333ns'
554
555 # @2400 data rate, tCCD_L is 6 CK
556 # CAS-to-CAS delay for bursts to the same bank group
557 # tBURST is equivalent to tCCD_S; no explicit parameter required
558 # for CAS-to-CAS delay for bursts to different bank groups
559 tCCD_L = '5ns';
560
561 # DDR4-2400 17-17-17
562 tRCD = '14.16ns'
563 tCL = '14.16ns'
564 tRP = '14.16ns'
565 tRAS = '32ns'
566
567 # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
568 tRRD = '3.3ns'
569
570 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
571 tRRD_L = '4.9ns';
572
573 tXAW = '21ns'
574 activation_limit = 4
575 tRFC = '350ns'
576
577 tWR = '15ns'
578
579 # Here using the average of WTR_S and WTR_L
580 tWTR = '5ns'
581
582 # Greater of 4 CK or 7.5 ns
583 tRTP = '7.5ns'
584
585 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
586 tRTW = '1.666ns'
587
588 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
589 tCS = '1.666ns'
590
591 # <=85C, half for >85C
592 tREFI = '7.8us'
593
594 # Current values from datasheet
595 IDD0 = '64mA'
596 IDD02 = '4mA'
597 IDD2N = '50mA'
598 IDD3N = '67mA'
599 IDD3N2 = '3mA'
600 IDD4W = '180mA'
601 IDD4R = '160mA'
602 IDD5 = '192mA'
603 VDD = '1.2V'
604 VDD2 = '2.5V'
605
606# A single LPDDR2-S4 x32 interface (one command/address bus), with
607# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
608# in a 1x32 configuration.
609class LPDDR2_S4_1066_x32(DRAMCtrl):
610 # No DLL in LPDDR2
611 dll = False
612
613 # size of device
614 device_size = '512MB'
615
616 # 1x32 configuration, 1 device with a 32-bit interface
617 device_bus_width = 32
618
619 # LPDDR2_S4 is a BL4 and BL8 device
620 burst_length = 8
621
622 # Each device has a page (row buffer) size of 1KB
623 # (this depends on the memory density)
624 device_rowbuffer_size = '1kB'
625
626 # 1x32 configuration, so 1 device
627 devices_per_rank = 1
628
629 # Use a single rank
630 ranks_per_channel = 1
631
632 # LPDDR2-S4 has 8 banks in all configurations
633 banks_per_rank = 8
634
635 # 533 MHz
636 tCK = '1.876ns'
637
638 # Fixed at 15 ns
639 tRCD = '15ns'
640
641 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
642 tCL = '15ns'
643
644 # Pre-charge one bank 15 ns (all banks 18 ns)
645 tRP = '15ns'
646
647 tRAS = '42ns'
648 tWR = '15ns'
649
650 tRTP = '7.5ns'
651
652 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
653 # Note this is a BL8 DDR device.
654 # Requests larger than 32 bytes are broken down into multiple requests
655 # in the controller
656 tBURST = '7.5ns'
657
658 # LPDDR2-S4, 4 Gbit
659 tRFC = '130ns'
660 tREFI = '3.9us'
661
662 # Irrespective of speed grade, tWTR is 7.5 ns
663 tWTR = '7.5ns'
664
665 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
666 tRTW = '3.75ns'
667
668 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
669 tCS = '3.75ns'
670
671 # Activate to activate irrespective of density and speed grade
672 tRRD = '10.0ns'
673
674 # Irrespective of density, tFAW is 50 ns
675 tXAW = '50ns'
676 activation_limit = 4
677
678 # Current values from datasheet
679 IDD0 = '15mA'
680 IDD02 = '70mA'
681 IDD2N = '2mA'
682 IDD2N2 = '30mA'
683 IDD3N = '2.5mA'
684 IDD3N2 = '30mA'
685 IDD4W = '10mA'
686 IDD4W2 = '190mA'
687 IDD4R = '3mA'
688 IDD4R2 = '220mA'
689 IDD5 = '40mA'
690 IDD52 = '150mA'
691 VDD = '1.8V'
692 VDD2 = '1.2V'
693
694# A single WideIO x128 interface (one command and address bus), with
695# default timings based on an estimated WIO-200 8 Gbit part.
696class WideIO_200_x128(DRAMCtrl):
697 # No DLL for WideIO
698 dll = False
699
700 # size of device
701 device_size = '1024MB'
702
703 # 1x128 configuration, 1 device with a 128-bit interface
704 device_bus_width = 128
705
706 # This is a BL4 device
707 burst_length = 4
708
709 # Each device has a page (row buffer) size of 4KB
710 # (this depends on the memory density)
711 device_rowbuffer_size = '4kB'
712
713 # 1x128 configuration, so 1 device
714 devices_per_rank = 1
715
716 # Use one rank for a one-high die stack
717 ranks_per_channel = 1
718
719 # WideIO has 4 banks in all configurations
720 banks_per_rank = 4
721
722 # 200 MHz
723 tCK = '5ns'
724
725 # WIO-200
726 tRCD = '18ns'
727 tCL = '18ns'
728 tRP = '18ns'
729 tRAS = '42ns'
730 tWR = '15ns'
731 # Read to precharge is same as the burst
732 tRTP = '20ns'
733
734 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
735 # Note this is a BL4 SDR device.
736 tBURST = '20ns'
737
738 # WIO 8 Gb
739 tRFC = '210ns'
740
741 # WIO 8 Gb, <=85C, half for >85C
742 tREFI = '3.9us'
743
744 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
745 tWTR = '15ns'
746
747 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
748 tRTW = '10ns'
749
750 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
751 tCS = '10ns'
752
753 # Activate to activate irrespective of density and speed grade
754 tRRD = '10.0ns'
755
756 # Two instead of four activation window
757 tXAW = '50ns'
758 activation_limit = 2
759
760 # The WideIO specification does not provide current information
761
762# A single LPDDR3 x32 interface (one command/address bus), with
763# default timings based on a LPDDR3-1600 4 Gbit part (Micron
764# EDF8132A1MC) in a 1x32 configuration.
765class LPDDR3_1600_x32(DRAMCtrl):
766 # No DLL for LPDDR3
767 dll = False
768
769 # size of device
770 device_size = '512MB'
771
772 # 1x32 configuration, 1 device with a 32-bit interface
773 device_bus_width = 32
774
775 # LPDDR3 is a BL8 device
776 burst_length = 8
777
778 # Each device has a page (row buffer) size of 4KB
779 device_rowbuffer_size = '4kB'
780
781 # 1x32 configuration, so 1 device
782 devices_per_rank = 1
783
784 # Technically the datasheet is a dual-rank package, but for
785 # comparison with the LPDDR2 config we stick to a single rank
786 ranks_per_channel = 1
787
788 # LPDDR3 has 8 banks in all configurations
789 banks_per_rank = 8
790
791 # 800 MHz
792 tCK = '1.25ns'
793
794 tRCD = '18ns'
795
796 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
797 tCL = '15ns'
798
799 tRAS = '42ns'
800 tWR = '15ns'
801
802 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
803 tRTP = '7.5ns'
804
805 # Pre-charge one bank 18 ns (all banks 21 ns)
806 tRP = '18ns'
807
808 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
809 # Note this is a BL8 DDR device.
810 # Requests larger than 32 bytes are broken down into multiple requests
811 # in the controller
812 tBURST = '5ns'
813
814 # LPDDR3, 4 Gb
815 tRFC = '130ns'
816 tREFI = '3.9us'
817
818 # Irrespective of speed grade, tWTR is 7.5 ns
819 tWTR = '7.5ns'
820
821 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
822 tRTW = '2.5ns'
823
824 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
825 tCS = '2.5ns'
826
827 # Activate to activate irrespective of density and speed grade
828 tRRD = '10.0ns'
829
830 # Irrespective of size, tFAW is 50 ns
831 tXAW = '50ns'
832 activation_limit = 4
833
834 # Current values from datasheet
835 IDD0 = '8mA'
836 IDD02 = '60mA'
837 IDD2N = '0.8mA'
838 IDD2N2 = '26mA'
839 IDD3N = '2mA'
840 IDD3N2 = '34mA'
841 IDD4W = '2mA'
842 IDD4W2 = '190mA'
843 IDD4R = '2mA'
844 IDD4R2 = '230mA'
845 IDD5 = '28mA'
846 IDD52 = '150mA'
847 VDD = '1.8V'
848 VDD2 = '1.2V'
849
850# A single GDDR5 x64 interface, with
851# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
852# H5GQ1H24AFR) in a 2x32 configuration.
853class GDDR5_4000_x64(DRAMCtrl):
854 # size of device
855 device_size = '128MB'
856
857 # 2x32 configuration, 1 device with a 32-bit interface
858 device_bus_width = 32
859
860 # GDDR5 is a BL8 device
861 burst_length = 8
862
863 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
864 device_rowbuffer_size = '256B'
865
866 # 2x32 configuration, so 2 devices
867 devices_per_rank = 2
868
869 # assume single rank
870 ranks_per_channel = 1
871
872 # GDDR5 has 4 bank groups
873 bank_groups_per_rank = 4
874
875 # GDDR5 has 16 banks with 4 bank groups
876 banks_per_rank = 16
877
878 # 1000 MHz
879 tCK = '1ns'
880
881 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
882 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
883 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
884 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
885 # With bank group architectures, tBURST represents the CAS-to-CAS
886 # delay for bursts to different bank groups (tCCD_S)
887 tBURST = '2ns'
888
889 # @1000MHz data rate, tCCD_L is 3 CK
890 # CAS-to-CAS delay for bursts to the same bank group
891 # tBURST is equivalent to tCCD_S; no explicit parameter required
892 # for CAS-to-CAS delay for bursts to different bank groups
893 tCCD_L = '3ns';
894
895 tRCD = '12ns'
896
897 # tCL is not directly found in datasheet and assumed equal tRCD
898 tCL = '12ns'
899
900 tRP = '12ns'
901 tRAS = '28ns'
902
903 # RRD_S (different bank group)
904 # RRD_S is 5.5 ns in datasheet.
905 # rounded to the next multiple of tCK
906 tRRD = '6ns'
907
908 # RRD_L (same bank group)
909 # RRD_L is 5.5 ns in datasheet.
910 # rounded to the next multiple of tCK
911 tRRD_L = '6ns'
912
913 tXAW = '23ns'
914
915 # tXAW < 4 x tRRD.
916 # Therefore, activation limit is set to 0
917 activation_limit = 0
918
919 tRFC = '65ns'
920 tWR = '12ns'
921
922 # Here using the average of WTR_S and WTR_L
923 tWTR = '5ns'
924
925 # Read-to-Precharge 2 CK
926 tRTP = '2ns'
927
928 # Assume 2 cycles
929 tRTW = '2ns'
930
931# A single HBM x128 interface (one command and address bus), with
932# default timings based on data publically released
933# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
934# IDD measurement values, and by extrapolating data from other classes.
935# Architecture values based on published HBM spec
936# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
937class HBM_1000_4H_x128(DRAMCtrl):
938 # HBM gen1 supports up to 8 128-bit physical channels
939 # Configuration defines a single channel, with the capacity
940 # set to (full_ stack_capacity / 8) based on 2Gb dies
941 # To use all 8 channels, set 'channels' parameter to 8 in
942 # system configuration
943
944 # 128-bit interface legacy mode
945 device_bus_width = 128
946
947 # HBM supports BL4 and BL2 (legacy mode only)
948 burst_length = 4
949
950 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
951 # with 8 channels, 128MB per channel
952 device_size = '128MB'
953
954 device_rowbuffer_size = '2kB'
955
956 # 1x128 configuration
957 devices_per_rank = 1
958
959 # HBM does not have a CS pin; set rank to 1
960 ranks_per_channel = 1
961
962 # HBM has 8 or 16 banks depending on capacity
963 # 2Gb dies have 8 banks
964 banks_per_rank = 8
965
966 # depending on frequency, bank groups may be required
967 # will always have 4 bank groups when enabled
968 # current specifications do not define the minimum frequency for
969 # bank group architecture
970 # setting bank_groups_per_rank to 0 to disable until range is defined
971 bank_groups_per_rank = 0
972
973 # 500 MHz for 1Gbps DDR data rate
974 tCK = '2ns'
975
976 # use values from IDD measurement in JEDEC spec
977 # use tRP value for tRCD and tCL similar to other classes
978 tRP = '15ns'
979 tRCD = '15ns'
980 tCL = '15ns'
981 tRAS = '33ns'
982
983 # BL2 and BL4 supported, default to BL4
984 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
985 tBURST = '4ns'
986
987 # value for 2Gb device from JEDEC spec
988 tRFC = '160ns'
989
990 # value for 2Gb device from JEDEC spec
991 tREFI = '3.9us'
992
993 # extrapolate the following from LPDDR configs, using ns values
994 # to minimize burst length, prefetch differences
995 tWR = '18ns'
996 tRTP = '7.5ns'
997 tWTR = '10ns'
998
999 # start with 2 cycles turnaround, similar to other memory classes
1000 # could be more with variations across the stack
1001 tRTW = '4ns'
1002
1003 # single rank device, set to 0
1004 tCS = '0ns'
1005
1006 # from MemCon example, tRRD is 4ns with 2ns tCK
1007 tRRD = '4ns'
1008
1009 # from MemCon example, tFAW is 30ns with 2ns tCK
1010 tXAW = '30ns'
1011 activation_limit = 4
1012
1013 # 4tCK
1014 tXP = '8ns'
1015
1016 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1017 tXS = '168ns'
1018
1019# A single HBM x64 interface (one command and address bus), with
1020# default timings based on HBM gen1 and data publically released
1021# A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1022# Note: This defines a pseudo-channel with a unique controller
1023# instantiated per pseudo-channel
1024# Stay at same IO rate (1Gbps) to maintain timing relationship with
1025# HBM gen1 class (HBM_1000_4H_x128) where possible
1026class HBM_1000_4H_x64(HBM_1000_4H_x128):
1027 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1028 # Configuration defines a single pseudo channel, with the capacity
1029 # set to (full_ stack_capacity / 16) based on 8Gb dies
1030 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1031 # system configuration
1032
1033 # 64-bit pseudo-channle interface
1034 device_bus_width = 64
1035
1036 # HBM pseudo-channel only supports BL4
1037 burst_length = 4
1038
1039 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1040 # with 16 channels, 256MB per channel
1041 device_size = '256MB'
1042
1043 # page size is halved with pseudo-channel; maintaining the same same number
1044 # of rows per pseudo-channel with 2X banks across 2 channels
1045 device_rowbuffer_size = '1kB'
1046
1047 # HBM has 8 or 16 banks depending on capacity
1048 # Starting with 4Gb dies, 16 banks are defined
1049 banks_per_rank = 16
1050
1051 # reset tRFC for larger, 8Gb device
1052 # use HBM1 4Gb value as a starting point
1053 tRFC = '260ns'
1054
1055 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1056 tXS = '268ns'
1057 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1058 tCS = '2ns'
1059 tREFI = '3.9us'
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