14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Andreas Hansson
40# Ani Udipi
| 15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Andreas Hansson
41# Ani Udipi
|
41
42from m5.params import *
43from AbstractMemory import *
44
45# Enum for memory scheduling algorithms, currently First-Come
46# First-Served and a First-Row Hit then First-Come First-Served
47class MemSched(Enum): vals = ['fcfs', 'frfcfs']
48
49# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
50# channel, rank, bank, row and column, respectively, and going from
51# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
52# suitable for an open-page policy, optimising for sequential accesses
53# hitting in the open row. For a closed-page policy, RoCoRaBaCh
54# maximises parallelism.
55class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
56
57# Enum for the page policy, either open, open_adaptive, close, or
58# close_adaptive.
59class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
60 'close_adaptive']
61
62# DRAMCtrl is a single-channel single-ported DRAM controller model
63# that aims to model the most important system-level performance
64# effects of a DRAM without getting into too much detail of the DRAM
65# itself.
66class DRAMCtrl(AbstractMemory):
67 type = 'DRAMCtrl'
68 cxx_header = "mem/dram_ctrl.hh"
69
70 # single-ported on the system interface side, instantiate with a
71 # bus in front of the controller for multiple ports
72 port = SlavePort("Slave port")
73
74 # the basic configuration of the controller architecture, note
75 # that each entry corresponds to a burst for the specific DRAM
76 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
77 # the cacheline size or request/packet size
78 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
79 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
80
81 # threshold in percent for when to forcefully trigger writes and
82 # start emptying the write buffer
83 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
84
85 # threshold in percentage for when to start writes if the read
86 # queue is empty
87 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
88
89 # minimum write bursts to schedule before switching back to reads
90 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
91 "switching to reads")
92
93 # scheduler, address map and page policy
94 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
95 addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
96 page_policy = Param.PageManage('open_adaptive', "Page management policy")
97
98 # enforce a limit on the number of accesses per row
99 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
100 "closing");
101
102 # size of DRAM Chip in Bytes
103 device_size = Param.MemorySize("Size of DRAM chip")
104
105 # pipeline latency of the controller and PHY, split into a
106 # frontend part and a backend part, with reads and writes serviced
107 # by the queues only seeing the frontend contribution, and reads
108 # serviced by the memory seeing the sum of the two
109 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
110 static_backend_latency = Param.Latency("10ns", "Static backend latency")
111
112 # the physical organisation of the DRAM
113 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
114 "device/chip")
115 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
116 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
117 "device/chip")
118 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
119 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
120
121 # default to 0 bank groups per rank, indicating bank group architecture
122 # is not used
123 # update per memory class when bank group architecture is supported
124 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
125 banks_per_rank = Param.Unsigned("Number of banks per rank")
126 # only used for the address mapping as the controller by
127 # construction is a single channel and multiple controllers have
128 # to be instantiated for a multi-channel configuration
129 channels = Param.Unsigned(1, "Number of channels")
130
131 # For power modelling we need to know if the DRAM has a DLL or not
132 dll = Param.Bool(True, "DRAM has DLL or not")
133
134 # DRAMPower provides in addition to the core power, the possibility to
135 # include RD/WR termination and IO power. This calculation assumes some
136 # default values. The integration of DRAMPower with gem5 does not include
137 # IO and RD/WR termination power by default. This might be added as an
138 # additional feature in the future.
139
140 # timing behaviour and constraints - all in nanoseconds
141
142 # the base clock period of the DRAM
143 tCK = Param.Latency("Clock period")
144
145 # the amount of time in nanoseconds from issuing an activate command
146 # to the data being available in the row buffer for a read/write
147 tRCD = Param.Latency("RAS to CAS delay")
148
149 # the time from issuing a read/write command to seeing the actual data
150 tCL = Param.Latency("CAS latency")
151
152 # minimum time between a precharge and subsequent activate
153 tRP = Param.Latency("Row precharge time")
154
155 # minimum time between an activate and a precharge to the same row
156 tRAS = Param.Latency("ACT to PRE delay")
157
158 # minimum time between a write data transfer and a precharge
159 tWR = Param.Latency("Write recovery time")
160
161 # minimum time between a read and precharge command
162 tRTP = Param.Latency("Read to precharge")
163
164 # time to complete a burst transfer, typically the burst length
165 # divided by two due to the DDR bus, but by making it a parameter
166 # it is easier to also evaluate SDR memories like WideIO.
167 # This parameter has to account for burst length.
168 # Read/Write requests with data size larger than one full burst are broken
169 # down into multiple requests in the controller
170 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
171 # With bank group architectures, tBURST represents the CAS-to-CAS
172 # delay for bursts to different bank groups (tCCD_S)
173 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
174
175 # CAS-to-CAS delay for bursts to the same bank group
176 # only utilized with bank group architectures; set to 0 for default case
177 # tBURST is equivalent to tCCD_S; no explicit parameter required
178 # for CAS-to-CAS delay for bursts to different bank groups
179 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
180
181 # time taken to complete one refresh cycle (N rows in all banks)
182 tRFC = Param.Latency("Refresh cycle time")
183
184 # refresh command interval, how often a "ref" command needs
185 # to be sent. It is 7.8 us for a 64ms refresh requirement
186 tREFI = Param.Latency("Refresh command interval")
187
188 # write-to-read, same rank turnaround penalty
189 tWTR = Param.Latency("Write to read, same rank switching time")
190
191 # read-to-write, same rank turnaround penalty
192 tRTW = Param.Latency("Read to write, same rank switching time")
193
194 # rank-to-rank bus delay penalty
195 # this does not correlate to a memory timing parameter and encompasses:
196 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
197 # different rank bus delay
198 tCS = Param.Latency("Rank to rank switching time")
199
200 # minimum row activate to row activate delay time
201 tRRD = Param.Latency("ACT to ACT delay")
202
203 # only utilized with bank group architectures; set to 0 for default case
204 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
205
206 # time window in which a maximum number of activates are allowed
207 # to take place, set to 0 to disable
208 tXAW = Param.Latency("X activation window")
209 activation_limit = Param.Unsigned("Max number of activates in window")
210
211 # time to exit power-down mode
212 # Exit power-down to next valid command delay
213 tXP = Param.Latency("0ns", "Power-up Delay")
214
215 # Exit Powerdown to commands requiring a locked DLL
216 tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
217
218 # time to exit self-refresh mode
219 tXS = Param.Latency("0ns", "Self-refresh exit latency")
220
221 # time to exit self-refresh mode with locked DLL
222 tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
223
224 # Currently rolled into other params
225 ######################################################################
226
227 # tRC - assumed to be tRAS + tRP
228
229 # Power Behaviour and Constraints
230 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
231 # defined as VDD and VDD2. Each current is defined for each voltage domain
232 # separately. For example, current IDD0 is active-precharge current for
233 # voltage domain VDD and current IDD02 is active-precharge current for
234 # voltage domain VDD2.
235 # By default all currents are set to 0mA. Users who are only interested in
236 # the performance of DRAMs can leave them at 0.
237
238 # Operating 1 Bank Active-Precharge current
239 IDD0 = Param.Current("0mA", "Active precharge current")
240
241 # Operating 1 Bank Active-Precharge current multiple voltage Range
242 IDD02 = Param.Current("0mA", "Active precharge current VDD2")
243
244 # Precharge Power-down Current: Slow exit
245 IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
246
247 # Precharge Power-down Current: Slow exit multiple voltage Range
248 IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
249
250 # Precharge Power-down Current: Fast exit
251 IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
252
253 # Precharge Power-down Current: Fast exit multiple voltage Range
254 IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
255
256 # Precharge Standby current
257 IDD2N = Param.Current("0mA", "Precharge Standby current")
258
259 # Precharge Standby current multiple voltage range
260 IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
261
262 # Active Power-down current: slow exit
263 IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
264
265 # Active Power-down current: slow exit multiple voltage range
266 IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
267
268 # Active Power-down current : fast exit
269 IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
270
271 # Active Power-down current : fast exit multiple voltage range
272 IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
273
274 # Active Standby current
275 IDD3N = Param.Current("0mA", "Active Standby current")
276
277 # Active Standby current multiple voltage range
278 IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
279
280 # Burst Read Operating Current
281 IDD4R = Param.Current("0mA", "READ current")
282
283 # Burst Read Operating Current multiple voltage range
284 IDD4R2 = Param.Current("0mA", "READ current VDD2")
285
286 # Burst Write Operating Current
287 IDD4W = Param.Current("0mA", "WRITE current")
288
289 # Burst Write Operating Current multiple voltage range
290 IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
291
292 # Refresh Current
293 IDD5 = Param.Current("0mA", "Refresh current")
294
295 # Refresh Current multiple voltage range
296 IDD52 = Param.Current("0mA", "Refresh current VDD2")
297
298 # Self-Refresh Current
299 IDD6 = Param.Current("0mA", "Self-refresh Current")
300
301 # Self-Refresh Current multiple voltage range
302 IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
303
304 # Main voltage range of the DRAM
305 VDD = Param.Voltage("0V", "Main Voltage Range")
306
307 # Second voltage range defined by some DRAMs
308 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
309
310# A single DDR3-1600 x64 channel (one command and address bus), with
311# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
312# an 8x8 configuration.
313class DDR3_1600_x64(DRAMCtrl):
314 # size of device in bytes
315 device_size = '512MB'
316
317 # 8x8 configuration, 8 devices each with an 8-bit interface
318 device_bus_width = 8
319
320 # DDR3 is a BL8 device
321 burst_length = 8
322
323 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
324 device_rowbuffer_size = '1kB'
325
326 # 8x8 configuration, so 8 devices
327 devices_per_rank = 8
328
329 # Use two ranks
330 ranks_per_channel = 2
331
332 # DDR3 has 8 banks in all configurations
333 banks_per_rank = 8
334
335 # 800 MHz
336 tCK = '1.25ns'
337
338 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
339 tBURST = '5ns'
340
341 # DDR3-1600 11-11-11
342 tRCD = '13.75ns'
343 tCL = '13.75ns'
344 tRP = '13.75ns'
345 tRAS = '35ns'
346 tRRD = '6ns'
347 tXAW = '30ns'
348 activation_limit = 4
349 tRFC = '260ns'
350
351 tWR = '15ns'
352
353 # Greater of 4 CK or 7.5 ns
354 tWTR = '7.5ns'
355
356 # Greater of 4 CK or 7.5 ns
357 tRTP = '7.5ns'
358
359 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
360 tRTW = '2.5ns'
361
362 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
363 tCS = '2.5ns'
364
365 # <=85C, half for >85C
366 tREFI = '7.8us'
367
368 # Current values from datasheet
369 IDD0 = '75mA'
370 IDD2N = '50mA'
371 IDD3N = '57mA'
372 IDD4W = '165mA'
373 IDD4R = '187mA'
374 IDD5 = '220mA'
375 VDD = '1.5V'
376
| 44
45from m5.params import *
46from AbstractMemory import *
47
48# Enum for memory scheduling algorithms, currently First-Come
49# First-Served and a First-Row Hit then First-Come First-Served
50class MemSched(Enum): vals = ['fcfs', 'frfcfs']
51
52# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
53# channel, rank, bank, row and column, respectively, and going from
54# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
55# suitable for an open-page policy, optimising for sequential accesses
56# hitting in the open row. For a closed-page policy, RoCoRaBaCh
57# maximises parallelism.
58class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
59
60# Enum for the page policy, either open, open_adaptive, close, or
61# close_adaptive.
62class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
63 'close_adaptive']
64
65# DRAMCtrl is a single-channel single-ported DRAM controller model
66# that aims to model the most important system-level performance
67# effects of a DRAM without getting into too much detail of the DRAM
68# itself.
69class DRAMCtrl(AbstractMemory):
70 type = 'DRAMCtrl'
71 cxx_header = "mem/dram_ctrl.hh"
72
73 # single-ported on the system interface side, instantiate with a
74 # bus in front of the controller for multiple ports
75 port = SlavePort("Slave port")
76
77 # the basic configuration of the controller architecture, note
78 # that each entry corresponds to a burst for the specific DRAM
79 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
80 # the cacheline size or request/packet size
81 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
82 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
83
84 # threshold in percent for when to forcefully trigger writes and
85 # start emptying the write buffer
86 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
87
88 # threshold in percentage for when to start writes if the read
89 # queue is empty
90 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
91
92 # minimum write bursts to schedule before switching back to reads
93 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
94 "switching to reads")
95
96 # scheduler, address map and page policy
97 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
98 addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
99 page_policy = Param.PageManage('open_adaptive', "Page management policy")
100
101 # enforce a limit on the number of accesses per row
102 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
103 "closing");
104
105 # size of DRAM Chip in Bytes
106 device_size = Param.MemorySize("Size of DRAM chip")
107
108 # pipeline latency of the controller and PHY, split into a
109 # frontend part and a backend part, with reads and writes serviced
110 # by the queues only seeing the frontend contribution, and reads
111 # serviced by the memory seeing the sum of the two
112 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
113 static_backend_latency = Param.Latency("10ns", "Static backend latency")
114
115 # the physical organisation of the DRAM
116 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
117 "device/chip")
118 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
119 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
120 "device/chip")
121 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
122 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
123
124 # default to 0 bank groups per rank, indicating bank group architecture
125 # is not used
126 # update per memory class when bank group architecture is supported
127 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
128 banks_per_rank = Param.Unsigned("Number of banks per rank")
129 # only used for the address mapping as the controller by
130 # construction is a single channel and multiple controllers have
131 # to be instantiated for a multi-channel configuration
132 channels = Param.Unsigned(1, "Number of channels")
133
134 # For power modelling we need to know if the DRAM has a DLL or not
135 dll = Param.Bool(True, "DRAM has DLL or not")
136
137 # DRAMPower provides in addition to the core power, the possibility to
138 # include RD/WR termination and IO power. This calculation assumes some
139 # default values. The integration of DRAMPower with gem5 does not include
140 # IO and RD/WR termination power by default. This might be added as an
141 # additional feature in the future.
142
143 # timing behaviour and constraints - all in nanoseconds
144
145 # the base clock period of the DRAM
146 tCK = Param.Latency("Clock period")
147
148 # the amount of time in nanoseconds from issuing an activate command
149 # to the data being available in the row buffer for a read/write
150 tRCD = Param.Latency("RAS to CAS delay")
151
152 # the time from issuing a read/write command to seeing the actual data
153 tCL = Param.Latency("CAS latency")
154
155 # minimum time between a precharge and subsequent activate
156 tRP = Param.Latency("Row precharge time")
157
158 # minimum time between an activate and a precharge to the same row
159 tRAS = Param.Latency("ACT to PRE delay")
160
161 # minimum time between a write data transfer and a precharge
162 tWR = Param.Latency("Write recovery time")
163
164 # minimum time between a read and precharge command
165 tRTP = Param.Latency("Read to precharge")
166
167 # time to complete a burst transfer, typically the burst length
168 # divided by two due to the DDR bus, but by making it a parameter
169 # it is easier to also evaluate SDR memories like WideIO.
170 # This parameter has to account for burst length.
171 # Read/Write requests with data size larger than one full burst are broken
172 # down into multiple requests in the controller
173 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
174 # With bank group architectures, tBURST represents the CAS-to-CAS
175 # delay for bursts to different bank groups (tCCD_S)
176 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
177
178 # CAS-to-CAS delay for bursts to the same bank group
179 # only utilized with bank group architectures; set to 0 for default case
180 # tBURST is equivalent to tCCD_S; no explicit parameter required
181 # for CAS-to-CAS delay for bursts to different bank groups
182 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
183
184 # time taken to complete one refresh cycle (N rows in all banks)
185 tRFC = Param.Latency("Refresh cycle time")
186
187 # refresh command interval, how often a "ref" command needs
188 # to be sent. It is 7.8 us for a 64ms refresh requirement
189 tREFI = Param.Latency("Refresh command interval")
190
191 # write-to-read, same rank turnaround penalty
192 tWTR = Param.Latency("Write to read, same rank switching time")
193
194 # read-to-write, same rank turnaround penalty
195 tRTW = Param.Latency("Read to write, same rank switching time")
196
197 # rank-to-rank bus delay penalty
198 # this does not correlate to a memory timing parameter and encompasses:
199 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
200 # different rank bus delay
201 tCS = Param.Latency("Rank to rank switching time")
202
203 # minimum row activate to row activate delay time
204 tRRD = Param.Latency("ACT to ACT delay")
205
206 # only utilized with bank group architectures; set to 0 for default case
207 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
208
209 # time window in which a maximum number of activates are allowed
210 # to take place, set to 0 to disable
211 tXAW = Param.Latency("X activation window")
212 activation_limit = Param.Unsigned("Max number of activates in window")
213
214 # time to exit power-down mode
215 # Exit power-down to next valid command delay
216 tXP = Param.Latency("0ns", "Power-up Delay")
217
218 # Exit Powerdown to commands requiring a locked DLL
219 tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
220
221 # time to exit self-refresh mode
222 tXS = Param.Latency("0ns", "Self-refresh exit latency")
223
224 # time to exit self-refresh mode with locked DLL
225 tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
226
227 # Currently rolled into other params
228 ######################################################################
229
230 # tRC - assumed to be tRAS + tRP
231
232 # Power Behaviour and Constraints
233 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
234 # defined as VDD and VDD2. Each current is defined for each voltage domain
235 # separately. For example, current IDD0 is active-precharge current for
236 # voltage domain VDD and current IDD02 is active-precharge current for
237 # voltage domain VDD2.
238 # By default all currents are set to 0mA. Users who are only interested in
239 # the performance of DRAMs can leave them at 0.
240
241 # Operating 1 Bank Active-Precharge current
242 IDD0 = Param.Current("0mA", "Active precharge current")
243
244 # Operating 1 Bank Active-Precharge current multiple voltage Range
245 IDD02 = Param.Current("0mA", "Active precharge current VDD2")
246
247 # Precharge Power-down Current: Slow exit
248 IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
249
250 # Precharge Power-down Current: Slow exit multiple voltage Range
251 IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
252
253 # Precharge Power-down Current: Fast exit
254 IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
255
256 # Precharge Power-down Current: Fast exit multiple voltage Range
257 IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
258
259 # Precharge Standby current
260 IDD2N = Param.Current("0mA", "Precharge Standby current")
261
262 # Precharge Standby current multiple voltage range
263 IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
264
265 # Active Power-down current: slow exit
266 IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
267
268 # Active Power-down current: slow exit multiple voltage range
269 IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
270
271 # Active Power-down current : fast exit
272 IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
273
274 # Active Power-down current : fast exit multiple voltage range
275 IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
276
277 # Active Standby current
278 IDD3N = Param.Current("0mA", "Active Standby current")
279
280 # Active Standby current multiple voltage range
281 IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
282
283 # Burst Read Operating Current
284 IDD4R = Param.Current("0mA", "READ current")
285
286 # Burst Read Operating Current multiple voltage range
287 IDD4R2 = Param.Current("0mA", "READ current VDD2")
288
289 # Burst Write Operating Current
290 IDD4W = Param.Current("0mA", "WRITE current")
291
292 # Burst Write Operating Current multiple voltage range
293 IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
294
295 # Refresh Current
296 IDD5 = Param.Current("0mA", "Refresh current")
297
298 # Refresh Current multiple voltage range
299 IDD52 = Param.Current("0mA", "Refresh current VDD2")
300
301 # Self-Refresh Current
302 IDD6 = Param.Current("0mA", "Self-refresh Current")
303
304 # Self-Refresh Current multiple voltage range
305 IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
306
307 # Main voltage range of the DRAM
308 VDD = Param.Voltage("0V", "Main Voltage Range")
309
310 # Second voltage range defined by some DRAMs
311 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
312
313# A single DDR3-1600 x64 channel (one command and address bus), with
314# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
315# an 8x8 configuration.
316class DDR3_1600_x64(DRAMCtrl):
317 # size of device in bytes
318 device_size = '512MB'
319
320 # 8x8 configuration, 8 devices each with an 8-bit interface
321 device_bus_width = 8
322
323 # DDR3 is a BL8 device
324 burst_length = 8
325
326 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
327 device_rowbuffer_size = '1kB'
328
329 # 8x8 configuration, so 8 devices
330 devices_per_rank = 8
331
332 # Use two ranks
333 ranks_per_channel = 2
334
335 # DDR3 has 8 banks in all configurations
336 banks_per_rank = 8
337
338 # 800 MHz
339 tCK = '1.25ns'
340
341 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
342 tBURST = '5ns'
343
344 # DDR3-1600 11-11-11
345 tRCD = '13.75ns'
346 tCL = '13.75ns'
347 tRP = '13.75ns'
348 tRAS = '35ns'
349 tRRD = '6ns'
350 tXAW = '30ns'
351 activation_limit = 4
352 tRFC = '260ns'
353
354 tWR = '15ns'
355
356 # Greater of 4 CK or 7.5 ns
357 tWTR = '7.5ns'
358
359 # Greater of 4 CK or 7.5 ns
360 tRTP = '7.5ns'
361
362 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
363 tRTW = '2.5ns'
364
365 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
366 tCS = '2.5ns'
367
368 # <=85C, half for >85C
369 tREFI = '7.8us'
370
371 # Current values from datasheet
372 IDD0 = '75mA'
373 IDD2N = '50mA'
374 IDD3N = '57mA'
375 IDD4W = '165mA'
376 IDD4R = '187mA'
377 IDD5 = '220mA'
378 VDD = '1.5V'
379
|
377# A single DDR3-2133 x64 channel refining a selected subset of the
378# options for the DDR-1600 configuration, based on the same DDR3-1600
379# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
380# consistent across the two configurations.
381class DDR3_2133_x64(DDR3_1600_x64):
382 # 1066 MHz
383 tCK = '0.938ns'
384
385 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
386 tBURST = '3.752ns'
387
388 # DDR3-2133 14-14-14
389 tRCD = '13.09ns'
390 tCL = '13.09ns'
391 tRP = '13.09ns'
392 tRAS = '33ns'
393 tRRD = '5ns'
394 tXAW = '25ns'
395
396 # Current values from datasheet
397 IDD0 = '70mA'
398 IDD2N = '37mA'
399 IDD3N = '44mA'
400 IDD4W = '157mA'
401 IDD4R = '191mA'
402 IDD5 = '250mA'
403 VDD = '1.5V'
404
405# A single DDR4-2400 x64 channel (one command and address bus), with
406# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8)
407# in an 8x8 configuration.
408class DDR4_2400_x64(DRAMCtrl):
409 # size of device
410 device_size = '512MB'
411
412 # 8x8 configuration, 8 devices each with an 8-bit interface
413 device_bus_width = 8
414
415 # DDR4 is a BL8 device
416 burst_length = 8
417
418 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
419 device_rowbuffer_size = '1kB'
420
421 # 8x8 configuration, so 8 devices
422 devices_per_rank = 8
423
424 # Match our DDR3 configurations which is dual rank
425 ranks_per_channel = 2
426
427 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
428 # Set to 4 for x4, x8 case
429 bank_groups_per_rank = 4
430
431 # DDR4 has 16 banks (4 bank groups) in all
432 # configurations. Currently we do not capture the additional
433 # constraints incurred by the bank groups
434 banks_per_rank = 16
435
436 # 1200 MHz
437 tCK = '0.833ns'
438
439 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
440 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
441 # With bank group architectures, tBURST represents the CAS-to-CAS
442 # delay for bursts to different bank groups (tCCD_S)
443 tBURST = '3.333ns'
444
445 # @2400 data rate, tCCD_L is 6 CK
446 # CAS-to-CAS delay for bursts to the same bank group
447 # tBURST is equivalent to tCCD_S; no explicit parameter required
448 # for CAS-to-CAS delay for bursts to different bank groups
449 tCCD_L = '5ns';
450
451 # DDR4-2400 17-17-17
452 tRCD = '14.16ns'
453 tCL = '14.16ns'
454 tRP = '14.16ns'
455 tRAS = '32ns'
456
457 # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
458 tRRD = '3.3ns'
459
460 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
461 tRRD_L = '4.9ns';
462
463 tXAW = '21ns'
464 activation_limit = 4
465 tRFC = '350ns'
466
467 tWR = '15ns'
468
469 # Here using the average of WTR_S and WTR_L
470 tWTR = '5ns'
471
472 # Greater of 4 CK or 7.5 ns
473 tRTP = '7.5ns'
474
475 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
476 tRTW = '1.666ns'
477
478 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
479 tCS = '1.666ns'
480
481 # <=85C, half for >85C
482 tREFI = '7.8us'
483
484 # Current values from datasheet
485 IDD0 = '64mA'
486 IDD02 = '4mA'
487 IDD2N = '50mA'
488 IDD3N = '67mA'
489 IDD3N2 = '3mA'
490 IDD4W = '180mA'
491 IDD4R = '160mA'
492 IDD5 = '192mA'
493 VDD = '1.2V'
494 VDD2 = '2.5V'
495
496# A single LPDDR2-S4 x32 interface (one command/address bus), with
497# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
498# in a 1x32 configuration.
499class LPDDR2_S4_1066_x32(DRAMCtrl):
500 # No DLL in LPDDR2
501 dll = False
502
503 # size of device
504 device_size = '512MB'
505
506 # 1x32 configuration, 1 device with a 32-bit interface
507 device_bus_width = 32
508
509 # LPDDR2_S4 is a BL4 and BL8 device
510 burst_length = 8
511
512 # Each device has a page (row buffer) size of 1KB
513 # (this depends on the memory density)
514 device_rowbuffer_size = '1kB'
515
516 # 1x32 configuration, so 1 device
517 devices_per_rank = 1
518
519 # Use a single rank
520 ranks_per_channel = 1
521
522 # LPDDR2-S4 has 8 banks in all configurations
523 banks_per_rank = 8
524
525 # 533 MHz
526 tCK = '1.876ns'
527
528 # Fixed at 15 ns
529 tRCD = '15ns'
530
531 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
532 tCL = '15ns'
533
534 # Pre-charge one bank 15 ns (all banks 18 ns)
535 tRP = '15ns'
536
537 tRAS = '42ns'
538 tWR = '15ns'
539
540 tRTP = '7.5ns'
541
542 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
543 # Note this is a BL8 DDR device.
544 # Requests larger than 32 bytes are broken down into multiple requests
545 # in the controller
546 tBURST = '7.5ns'
547
548 # LPDDR2-S4, 4 Gbit
549 tRFC = '130ns'
550 tREFI = '3.9us'
551
552 # Irrespective of speed grade, tWTR is 7.5 ns
553 tWTR = '7.5ns'
554
555 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
556 tRTW = '3.75ns'
557
558 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
559 tCS = '3.75ns'
560
561 # Activate to activate irrespective of density and speed grade
562 tRRD = '10.0ns'
563
564 # Irrespective of density, tFAW is 50 ns
565 tXAW = '50ns'
566 activation_limit = 4
567
568 # Current values from datasheet
569 IDD0 = '15mA'
570 IDD02 = '70mA'
571 IDD2N = '2mA'
572 IDD2N2 = '30mA'
573 IDD3N = '2.5mA'
574 IDD3N2 = '30mA'
575 IDD4W = '10mA'
576 IDD4W2 = '190mA'
577 IDD4R = '3mA'
578 IDD4R2 = '220mA'
579 IDD5 = '40mA'
580 IDD52 = '150mA'
581 VDD = '1.8V'
582 VDD2 = '1.2V'
583
584# A single WideIO x128 interface (one command and address bus), with
585# default timings based on an estimated WIO-200 8 Gbit part.
586class WideIO_200_x128(DRAMCtrl):
587 # No DLL for WideIO
588 dll = False
589
590 # size of device
591 device_size = '1024MB'
592
593 # 1x128 configuration, 1 device with a 128-bit interface
594 device_bus_width = 128
595
596 # This is a BL4 device
597 burst_length = 4
598
599 # Each device has a page (row buffer) size of 4KB
600 # (this depends on the memory density)
601 device_rowbuffer_size = '4kB'
602
603 # 1x128 configuration, so 1 device
604 devices_per_rank = 1
605
606 # Use one rank for a one-high die stack
607 ranks_per_channel = 1
608
609 # WideIO has 4 banks in all configurations
610 banks_per_rank = 4
611
612 # 200 MHz
613 tCK = '5ns'
614
615 # WIO-200
616 tRCD = '18ns'
617 tCL = '18ns'
618 tRP = '18ns'
619 tRAS = '42ns'
620 tWR = '15ns'
621 # Read to precharge is same as the burst
622 tRTP = '20ns'
623
624 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
625 # Note this is a BL4 SDR device.
626 tBURST = '20ns'
627
628 # WIO 8 Gb
629 tRFC = '210ns'
630
631 # WIO 8 Gb, <=85C, half for >85C
632 tREFI = '3.9us'
633
634 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
635 tWTR = '15ns'
636
637 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
638 tRTW = '10ns'
639
640 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
641 tCS = '10ns'
642
643 # Activate to activate irrespective of density and speed grade
644 tRRD = '10.0ns'
645
646 # Two instead of four activation window
647 tXAW = '50ns'
648 activation_limit = 2
649
650 # The WideIO specification does not provide current information
651
652# A single LPDDR3 x32 interface (one command/address bus), with
653# default timings based on a LPDDR3-1600 4 Gbit part (Micron
654# EDF8132A1MC) in a 1x32 configuration.
655class LPDDR3_1600_x32(DRAMCtrl):
656 # No DLL for LPDDR3
657 dll = False
658
659 # size of device
660 device_size = '512MB'
661
662 # 1x32 configuration, 1 device with a 32-bit interface
663 device_bus_width = 32
664
665 # LPDDR3 is a BL8 device
666 burst_length = 8
667
668 # Each device has a page (row buffer) size of 4KB
669 device_rowbuffer_size = '4kB'
670
671 # 1x32 configuration, so 1 device
672 devices_per_rank = 1
673
674 # Technically the datasheet is a dual-rank package, but for
675 # comparison with the LPDDR2 config we stick to a single rank
676 ranks_per_channel = 1
677
678 # LPDDR3 has 8 banks in all configurations
679 banks_per_rank = 8
680
681 # 800 MHz
682 tCK = '1.25ns'
683
684 tRCD = '18ns'
685
686 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
687 tCL = '15ns'
688
689 tRAS = '42ns'
690 tWR = '15ns'
691
692 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
693 tRTP = '7.5ns'
694
695 # Pre-charge one bank 18 ns (all banks 21 ns)
696 tRP = '18ns'
697
698 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
699 # Note this is a BL8 DDR device.
700 # Requests larger than 32 bytes are broken down into multiple requests
701 # in the controller
702 tBURST = '5ns'
703
704 # LPDDR3, 4 Gb
705 tRFC = '130ns'
706 tREFI = '3.9us'
707
708 # Irrespective of speed grade, tWTR is 7.5 ns
709 tWTR = '7.5ns'
710
711 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
712 tRTW = '2.5ns'
713
714 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
715 tCS = '2.5ns'
716
717 # Activate to activate irrespective of density and speed grade
718 tRRD = '10.0ns'
719
720 # Irrespective of size, tFAW is 50 ns
721 tXAW = '50ns'
722 activation_limit = 4
723
724 # Current values from datasheet
725 IDD0 = '8mA'
726 IDD02 = '60mA'
727 IDD2N = '0.8mA'
728 IDD2N2 = '26mA'
729 IDD3N = '2mA'
730 IDD3N2 = '34mA'
731 IDD4W = '2mA'
732 IDD4W2 = '190mA'
733 IDD4R = '2mA'
734 IDD4R2 = '230mA'
735 IDD5 = '28mA'
736 IDD52 = '150mA'
737 VDD = '1.8V'
738 VDD2 = '1.2V'
739
740# A single GDDR5 x64 interface, with
741# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
742# H5GQ1H24AFR) in a 2x32 configuration.
743class GDDR5_4000_x64(DRAMCtrl):
744 # size of device
745 device_size = '128MB'
746
747 # 2x32 configuration, 1 device with a 32-bit interface
748 device_bus_width = 32
749
750 # GDDR5 is a BL8 device
751 burst_length = 8
752
753 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
754 device_rowbuffer_size = '256B'
755
756 # 2x32 configuration, so 2 devices
757 devices_per_rank = 2
758
759 # assume single rank
760 ranks_per_channel = 1
761
762 # GDDR5 has 4 bank groups
763 bank_groups_per_rank = 4
764
765 # GDDR5 has 16 banks with 4 bank groups
766 banks_per_rank = 16
767
768 # 1000 MHz
769 tCK = '1ns'
770
771 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
772 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
773 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
774 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
775 # With bank group architectures, tBURST represents the CAS-to-CAS
776 # delay for bursts to different bank groups (tCCD_S)
777 tBURST = '2ns'
778
779 # @1000MHz data rate, tCCD_L is 3 CK
780 # CAS-to-CAS delay for bursts to the same bank group
781 # tBURST is equivalent to tCCD_S; no explicit parameter required
782 # for CAS-to-CAS delay for bursts to different bank groups
783 tCCD_L = '3ns';
784
785 tRCD = '12ns'
786
787 # tCL is not directly found in datasheet and assumed equal tRCD
788 tCL = '12ns'
789
790 tRP = '12ns'
791 tRAS = '28ns'
792
793 # RRD_S (different bank group)
794 # RRD_S is 5.5 ns in datasheet.
795 # rounded to the next multiple of tCK
796 tRRD = '6ns'
797
798 # RRD_L (same bank group)
799 # RRD_L is 5.5 ns in datasheet.
800 # rounded to the next multiple of tCK
801 tRRD_L = '6ns'
802
803 tXAW = '23ns'
804
805 # tXAW < 4 x tRRD.
806 # Therefore, activation limit is set to 0
807 activation_limit = 0
808
809 tRFC = '65ns'
810 tWR = '12ns'
811
812 # Here using the average of WTR_S and WTR_L
813 tWTR = '5ns'
814
815 # Read-to-Precharge 2 CK
816 tRTP = '2ns'
817
818 # Assume 2 cycles
819 tRTW = '2ns'
820
821 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
822 tCS = '2ns'
823 tREFI = '3.9us'
| 466# A single DDR3-2133 x64 channel refining a selected subset of the
467# options for the DDR-1600 configuration, based on the same DDR3-1600
468# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
469# consistent across the two configurations.
470class DDR3_2133_x64(DDR3_1600_x64):
471 # 1066 MHz
472 tCK = '0.938ns'
473
474 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
475 tBURST = '3.752ns'
476
477 # DDR3-2133 14-14-14
478 tRCD = '13.09ns'
479 tCL = '13.09ns'
480 tRP = '13.09ns'
481 tRAS = '33ns'
482 tRRD = '5ns'
483 tXAW = '25ns'
484
485 # Current values from datasheet
486 IDD0 = '70mA'
487 IDD2N = '37mA'
488 IDD3N = '44mA'
489 IDD4W = '157mA'
490 IDD4R = '191mA'
491 IDD5 = '250mA'
492 VDD = '1.5V'
493
494# A single DDR4-2400 x64 channel (one command and address bus), with
495# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8)
496# in an 8x8 configuration.
497class DDR4_2400_x64(DRAMCtrl):
498 # size of device
499 device_size = '512MB'
500
501 # 8x8 configuration, 8 devices each with an 8-bit interface
502 device_bus_width = 8
503
504 # DDR4 is a BL8 device
505 burst_length = 8
506
507 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
508 device_rowbuffer_size = '1kB'
509
510 # 8x8 configuration, so 8 devices
511 devices_per_rank = 8
512
513 # Match our DDR3 configurations which is dual rank
514 ranks_per_channel = 2
515
516 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
517 # Set to 4 for x4, x8 case
518 bank_groups_per_rank = 4
519
520 # DDR4 has 16 banks (4 bank groups) in all
521 # configurations. Currently we do not capture the additional
522 # constraints incurred by the bank groups
523 banks_per_rank = 16
524
525 # 1200 MHz
526 tCK = '0.833ns'
527
528 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
529 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
530 # With bank group architectures, tBURST represents the CAS-to-CAS
531 # delay for bursts to different bank groups (tCCD_S)
532 tBURST = '3.333ns'
533
534 # @2400 data rate, tCCD_L is 6 CK
535 # CAS-to-CAS delay for bursts to the same bank group
536 # tBURST is equivalent to tCCD_S; no explicit parameter required
537 # for CAS-to-CAS delay for bursts to different bank groups
538 tCCD_L = '5ns';
539
540 # DDR4-2400 17-17-17
541 tRCD = '14.16ns'
542 tCL = '14.16ns'
543 tRP = '14.16ns'
544 tRAS = '32ns'
545
546 # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
547 tRRD = '3.3ns'
548
549 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
550 tRRD_L = '4.9ns';
551
552 tXAW = '21ns'
553 activation_limit = 4
554 tRFC = '350ns'
555
556 tWR = '15ns'
557
558 # Here using the average of WTR_S and WTR_L
559 tWTR = '5ns'
560
561 # Greater of 4 CK or 7.5 ns
562 tRTP = '7.5ns'
563
564 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
565 tRTW = '1.666ns'
566
567 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
568 tCS = '1.666ns'
569
570 # <=85C, half for >85C
571 tREFI = '7.8us'
572
573 # Current values from datasheet
574 IDD0 = '64mA'
575 IDD02 = '4mA'
576 IDD2N = '50mA'
577 IDD3N = '67mA'
578 IDD3N2 = '3mA'
579 IDD4W = '180mA'
580 IDD4R = '160mA'
581 IDD5 = '192mA'
582 VDD = '1.2V'
583 VDD2 = '2.5V'
584
585# A single LPDDR2-S4 x32 interface (one command/address bus), with
586# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
587# in a 1x32 configuration.
588class LPDDR2_S4_1066_x32(DRAMCtrl):
589 # No DLL in LPDDR2
590 dll = False
591
592 # size of device
593 device_size = '512MB'
594
595 # 1x32 configuration, 1 device with a 32-bit interface
596 device_bus_width = 32
597
598 # LPDDR2_S4 is a BL4 and BL8 device
599 burst_length = 8
600
601 # Each device has a page (row buffer) size of 1KB
602 # (this depends on the memory density)
603 device_rowbuffer_size = '1kB'
604
605 # 1x32 configuration, so 1 device
606 devices_per_rank = 1
607
608 # Use a single rank
609 ranks_per_channel = 1
610
611 # LPDDR2-S4 has 8 banks in all configurations
612 banks_per_rank = 8
613
614 # 533 MHz
615 tCK = '1.876ns'
616
617 # Fixed at 15 ns
618 tRCD = '15ns'
619
620 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
621 tCL = '15ns'
622
623 # Pre-charge one bank 15 ns (all banks 18 ns)
624 tRP = '15ns'
625
626 tRAS = '42ns'
627 tWR = '15ns'
628
629 tRTP = '7.5ns'
630
631 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
632 # Note this is a BL8 DDR device.
633 # Requests larger than 32 bytes are broken down into multiple requests
634 # in the controller
635 tBURST = '7.5ns'
636
637 # LPDDR2-S4, 4 Gbit
638 tRFC = '130ns'
639 tREFI = '3.9us'
640
641 # Irrespective of speed grade, tWTR is 7.5 ns
642 tWTR = '7.5ns'
643
644 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
645 tRTW = '3.75ns'
646
647 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
648 tCS = '3.75ns'
649
650 # Activate to activate irrespective of density and speed grade
651 tRRD = '10.0ns'
652
653 # Irrespective of density, tFAW is 50 ns
654 tXAW = '50ns'
655 activation_limit = 4
656
657 # Current values from datasheet
658 IDD0 = '15mA'
659 IDD02 = '70mA'
660 IDD2N = '2mA'
661 IDD2N2 = '30mA'
662 IDD3N = '2.5mA'
663 IDD3N2 = '30mA'
664 IDD4W = '10mA'
665 IDD4W2 = '190mA'
666 IDD4R = '3mA'
667 IDD4R2 = '220mA'
668 IDD5 = '40mA'
669 IDD52 = '150mA'
670 VDD = '1.8V'
671 VDD2 = '1.2V'
672
673# A single WideIO x128 interface (one command and address bus), with
674# default timings based on an estimated WIO-200 8 Gbit part.
675class WideIO_200_x128(DRAMCtrl):
676 # No DLL for WideIO
677 dll = False
678
679 # size of device
680 device_size = '1024MB'
681
682 # 1x128 configuration, 1 device with a 128-bit interface
683 device_bus_width = 128
684
685 # This is a BL4 device
686 burst_length = 4
687
688 # Each device has a page (row buffer) size of 4KB
689 # (this depends on the memory density)
690 device_rowbuffer_size = '4kB'
691
692 # 1x128 configuration, so 1 device
693 devices_per_rank = 1
694
695 # Use one rank for a one-high die stack
696 ranks_per_channel = 1
697
698 # WideIO has 4 banks in all configurations
699 banks_per_rank = 4
700
701 # 200 MHz
702 tCK = '5ns'
703
704 # WIO-200
705 tRCD = '18ns'
706 tCL = '18ns'
707 tRP = '18ns'
708 tRAS = '42ns'
709 tWR = '15ns'
710 # Read to precharge is same as the burst
711 tRTP = '20ns'
712
713 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
714 # Note this is a BL4 SDR device.
715 tBURST = '20ns'
716
717 # WIO 8 Gb
718 tRFC = '210ns'
719
720 # WIO 8 Gb, <=85C, half for >85C
721 tREFI = '3.9us'
722
723 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
724 tWTR = '15ns'
725
726 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
727 tRTW = '10ns'
728
729 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
730 tCS = '10ns'
731
732 # Activate to activate irrespective of density and speed grade
733 tRRD = '10.0ns'
734
735 # Two instead of four activation window
736 tXAW = '50ns'
737 activation_limit = 2
738
739 # The WideIO specification does not provide current information
740
741# A single LPDDR3 x32 interface (one command/address bus), with
742# default timings based on a LPDDR3-1600 4 Gbit part (Micron
743# EDF8132A1MC) in a 1x32 configuration.
744class LPDDR3_1600_x32(DRAMCtrl):
745 # No DLL for LPDDR3
746 dll = False
747
748 # size of device
749 device_size = '512MB'
750
751 # 1x32 configuration, 1 device with a 32-bit interface
752 device_bus_width = 32
753
754 # LPDDR3 is a BL8 device
755 burst_length = 8
756
757 # Each device has a page (row buffer) size of 4KB
758 device_rowbuffer_size = '4kB'
759
760 # 1x32 configuration, so 1 device
761 devices_per_rank = 1
762
763 # Technically the datasheet is a dual-rank package, but for
764 # comparison with the LPDDR2 config we stick to a single rank
765 ranks_per_channel = 1
766
767 # LPDDR3 has 8 banks in all configurations
768 banks_per_rank = 8
769
770 # 800 MHz
771 tCK = '1.25ns'
772
773 tRCD = '18ns'
774
775 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
776 tCL = '15ns'
777
778 tRAS = '42ns'
779 tWR = '15ns'
780
781 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
782 tRTP = '7.5ns'
783
784 # Pre-charge one bank 18 ns (all banks 21 ns)
785 tRP = '18ns'
786
787 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
788 # Note this is a BL8 DDR device.
789 # Requests larger than 32 bytes are broken down into multiple requests
790 # in the controller
791 tBURST = '5ns'
792
793 # LPDDR3, 4 Gb
794 tRFC = '130ns'
795 tREFI = '3.9us'
796
797 # Irrespective of speed grade, tWTR is 7.5 ns
798 tWTR = '7.5ns'
799
800 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
801 tRTW = '2.5ns'
802
803 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
804 tCS = '2.5ns'
805
806 # Activate to activate irrespective of density and speed grade
807 tRRD = '10.0ns'
808
809 # Irrespective of size, tFAW is 50 ns
810 tXAW = '50ns'
811 activation_limit = 4
812
813 # Current values from datasheet
814 IDD0 = '8mA'
815 IDD02 = '60mA'
816 IDD2N = '0.8mA'
817 IDD2N2 = '26mA'
818 IDD3N = '2mA'
819 IDD3N2 = '34mA'
820 IDD4W = '2mA'
821 IDD4W2 = '190mA'
822 IDD4R = '2mA'
823 IDD4R2 = '230mA'
824 IDD5 = '28mA'
825 IDD52 = '150mA'
826 VDD = '1.8V'
827 VDD2 = '1.2V'
828
829# A single GDDR5 x64 interface, with
830# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
831# H5GQ1H24AFR) in a 2x32 configuration.
832class GDDR5_4000_x64(DRAMCtrl):
833 # size of device
834 device_size = '128MB'
835
836 # 2x32 configuration, 1 device with a 32-bit interface
837 device_bus_width = 32
838
839 # GDDR5 is a BL8 device
840 burst_length = 8
841
842 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
843 device_rowbuffer_size = '256B'
844
845 # 2x32 configuration, so 2 devices
846 devices_per_rank = 2
847
848 # assume single rank
849 ranks_per_channel = 1
850
851 # GDDR5 has 4 bank groups
852 bank_groups_per_rank = 4
853
854 # GDDR5 has 16 banks with 4 bank groups
855 banks_per_rank = 16
856
857 # 1000 MHz
858 tCK = '1ns'
859
860 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
861 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
862 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
863 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
864 # With bank group architectures, tBURST represents the CAS-to-CAS
865 # delay for bursts to different bank groups (tCCD_S)
866 tBURST = '2ns'
867
868 # @1000MHz data rate, tCCD_L is 3 CK
869 # CAS-to-CAS delay for bursts to the same bank group
870 # tBURST is equivalent to tCCD_S; no explicit parameter required
871 # for CAS-to-CAS delay for bursts to different bank groups
872 tCCD_L = '3ns';
873
874 tRCD = '12ns'
875
876 # tCL is not directly found in datasheet and assumed equal tRCD
877 tCL = '12ns'
878
879 tRP = '12ns'
880 tRAS = '28ns'
881
882 # RRD_S (different bank group)
883 # RRD_S is 5.5 ns in datasheet.
884 # rounded to the next multiple of tCK
885 tRRD = '6ns'
886
887 # RRD_L (same bank group)
888 # RRD_L is 5.5 ns in datasheet.
889 # rounded to the next multiple of tCK
890 tRRD_L = '6ns'
891
892 tXAW = '23ns'
893
894 # tXAW < 4 x tRRD.
895 # Therefore, activation limit is set to 0
896 activation_limit = 0
897
898 tRFC = '65ns'
899 tWR = '12ns'
900
901 # Here using the average of WTR_S and WTR_L
902 tWTR = '5ns'
903
904 # Read-to-Precharge 2 CK
905 tRTP = '2ns'
906
907 # Assume 2 cycles
908 tRTW = '2ns'
909
910 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
911 tCS = '2ns'
912 tREFI = '3.9us'
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