1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2013 Amin Farmahini-Farahani
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Andreas Hansson
40# Ani Udipi
41
42from m5.params import *
43from AbstractMemory import *
44
45# Enum for memory scheduling algorithms, currently First-Come
46# First-Served and a First-Row Hit then First-Come First-Served
47class MemSched(Enum): vals = ['fcfs', 'frfcfs']
48
49# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
50# channel, rank, bank, row and column, respectively, and going from
51# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
52# suitable for an open-page policy, optimising for sequential accesses
53# hitting in the open row. For a closed-page policy, RoCoRaBaCh
54# maximises parallelism.
55class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
56
57# Enum for the page policy, either open, open_adaptive, close, or
58# close_adaptive.
59class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
60 'close_adaptive']
61
62# DRAMCtrl is a single-channel single-ported DRAM controller model
63# that aims to model the most important system-level performance
64# effects of a DRAM without getting into too much detail of the DRAM
65# itself.
66class DRAMCtrl(AbstractMemory):
67 type = 'DRAMCtrl'
68 cxx_header = "mem/dram_ctrl.hh"
69
70 # single-ported on the system interface side, instantiate with a
71 # bus in front of the controller for multiple ports
72 port = SlavePort("Slave port")
73
74 # the basic configuration of the controller architecture
75 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
76 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
77
78 # threshold in percent for when to forcefully trigger writes and
79 # start emptying the write buffer
80 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
81
82 # threshold in percentage for when to start writes if the read
83 # queue is empty
84 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
85
86 # minimum write bursts to schedule before switching back to reads
87 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
88 "switching to reads")
89
90 # scheduler, address map and page policy
91 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
92 addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy")
93 page_policy = Param.PageManage('open_adaptive', "Page management policy")
94
95 # enforce a limit on the number of accesses per row
96 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
97 "closing");
98
99 # pipeline latency of the controller and PHY, split into a
100 # frontend part and a backend part, with reads and writes serviced
101 # by the queues only seeing the frontend contribution, and reads
102 # serviced by the memory seeing the sum of the two
103 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
104 static_backend_latency = Param.Latency("10ns", "Static backend latency")
105
106 # the physical organisation of the DRAM
107 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
108 "device/chip")
109 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
110 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
111 "device/chip")
112 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
113 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
114
115 # default to 0 bank groups per rank, indicating bank group architecture
116 # is not used
117 # update per memory class when bank group architecture is supported
118 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
119 banks_per_rank = Param.Unsigned("Number of banks per rank")
120 # only used for the address mapping as the controller by
121 # construction is a single channel and multiple controllers have
122 # to be instantiated for a multi-channel configuration
123 channels = Param.Unsigned(1, "Number of channels")
124
| 1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2013 Amin Farmahini-Farahani
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Andreas Hansson
40# Ani Udipi
41
42from m5.params import *
43from AbstractMemory import *
44
45# Enum for memory scheduling algorithms, currently First-Come
46# First-Served and a First-Row Hit then First-Come First-Served
47class MemSched(Enum): vals = ['fcfs', 'frfcfs']
48
49# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
50# channel, rank, bank, row and column, respectively, and going from
51# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
52# suitable for an open-page policy, optimising for sequential accesses
53# hitting in the open row. For a closed-page policy, RoCoRaBaCh
54# maximises parallelism.
55class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
56
57# Enum for the page policy, either open, open_adaptive, close, or
58# close_adaptive.
59class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
60 'close_adaptive']
61
62# DRAMCtrl is a single-channel single-ported DRAM controller model
63# that aims to model the most important system-level performance
64# effects of a DRAM without getting into too much detail of the DRAM
65# itself.
66class DRAMCtrl(AbstractMemory):
67 type = 'DRAMCtrl'
68 cxx_header = "mem/dram_ctrl.hh"
69
70 # single-ported on the system interface side, instantiate with a
71 # bus in front of the controller for multiple ports
72 port = SlavePort("Slave port")
73
74 # the basic configuration of the controller architecture
75 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
76 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
77
78 # threshold in percent for when to forcefully trigger writes and
79 # start emptying the write buffer
80 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
81
82 # threshold in percentage for when to start writes if the read
83 # queue is empty
84 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
85
86 # minimum write bursts to schedule before switching back to reads
87 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
88 "switching to reads")
89
90 # scheduler, address map and page policy
91 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
92 addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy")
93 page_policy = Param.PageManage('open_adaptive', "Page management policy")
94
95 # enforce a limit on the number of accesses per row
96 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
97 "closing");
98
99 # pipeline latency of the controller and PHY, split into a
100 # frontend part and a backend part, with reads and writes serviced
101 # by the queues only seeing the frontend contribution, and reads
102 # serviced by the memory seeing the sum of the two
103 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
104 static_backend_latency = Param.Latency("10ns", "Static backend latency")
105
106 # the physical organisation of the DRAM
107 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
108 "device/chip")
109 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
110 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
111 "device/chip")
112 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
113 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
114
115 # default to 0 bank groups per rank, indicating bank group architecture
116 # is not used
117 # update per memory class when bank group architecture is supported
118 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
119 banks_per_rank = Param.Unsigned("Number of banks per rank")
120 # only used for the address mapping as the controller by
121 # construction is a single channel and multiple controllers have
122 # to be instantiated for a multi-channel configuration
123 channels = Param.Unsigned(1, "Number of channels")
124
|
| 125 # For power modelling we need to know if the DRAM has a DLL or not
126 dll = Param.Bool(True, "DRAM has DLL or not")
127
128 # DRAMPower provides in addition to the core power, the possibility to
129 # include RD/WR termination and IO power. This calculation assumes some
130 # default values. The integration of DRAMPower with gem5 does not include
131 # IO and RD/WR termination power by default. This might be added as an
132 # additional feature in the future.
133
|
125 # timing behaviour and constraints - all in nanoseconds
126
127 # the base clock period of the DRAM
128 tCK = Param.Latency("Clock period")
129
130 # the amount of time in nanoseconds from issuing an activate command
131 # to the data being available in the row buffer for a read/write
132 tRCD = Param.Latency("RAS to CAS delay")
133
134 # the time from issuing a read/write command to seeing the actual data
135 tCL = Param.Latency("CAS latency")
136
137 # minimum time between a precharge and subsequent activate
138 tRP = Param.Latency("Row precharge time")
139
140 # minimum time between an activate and a precharge to the same row
141 tRAS = Param.Latency("ACT to PRE delay")
142
143 # minimum time between a write data transfer and a precharge
144 tWR = Param.Latency("Write recovery time")
145
146 # minimum time between a read and precharge command
147 tRTP = Param.Latency("Read to precharge")
148
149 # time to complete a burst transfer, typically the burst length
150 # divided by two due to the DDR bus, but by making it a parameter
151 # it is easier to also evaluate SDR memories like WideIO.
152 # This parameter has to account for burst length.
153 # Read/Write requests with data size larger than one full burst are broken
154 # down into multiple requests in the controller
155 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
156 # With bank group architectures, tBURST represents the CAS-to-CAS
157 # delay for bursts to different bank groups (tCCD_S)
158 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
159
160 # CAS-to-CAS delay for bursts to the same bank group
161 # only utilized with bank group architectures; set to 0 for default case
162 # tBURST is equivalent to tCCD_S; no explicit parameter required
163 # for CAS-to-CAS delay for bursts to different bank groups
164 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
165
166 # time taken to complete one refresh cycle (N rows in all banks)
167 tRFC = Param.Latency("Refresh cycle time")
168
169 # refresh command interval, how often a "ref" command needs
170 # to be sent. It is 7.8 us for a 64ms refresh requirement
171 tREFI = Param.Latency("Refresh command interval")
172
173 # write-to-read, same rank turnaround penalty
174 tWTR = Param.Latency("Write to read, same rank switching time")
175
176 # read-to-write, same rank turnaround penalty
177 tRTW = Param.Latency("Read to write, same rank switching time")
178
179 # rank-to-rank bus delay penalty
180 # this does not correlate to a memory timing parameter and encompasses:
181 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
182 # different rank bus delay
183 tCS = Param.Latency("Rank to rank switching time")
184
185 # minimum row activate to row activate delay time
186 tRRD = Param.Latency("ACT to ACT delay")
187
188 # only utilized with bank group architectures; set to 0 for default case
189 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
190
191 # time window in which a maximum number of activates are allowed
192 # to take place, set to 0 to disable
193 tXAW = Param.Latency("X activation window")
194 activation_limit = Param.Unsigned("Max number of activates in window")
195
| 134 # timing behaviour and constraints - all in nanoseconds
135
136 # the base clock period of the DRAM
137 tCK = Param.Latency("Clock period")
138
139 # the amount of time in nanoseconds from issuing an activate command
140 # to the data being available in the row buffer for a read/write
141 tRCD = Param.Latency("RAS to CAS delay")
142
143 # the time from issuing a read/write command to seeing the actual data
144 tCL = Param.Latency("CAS latency")
145
146 # minimum time between a precharge and subsequent activate
147 tRP = Param.Latency("Row precharge time")
148
149 # minimum time between an activate and a precharge to the same row
150 tRAS = Param.Latency("ACT to PRE delay")
151
152 # minimum time between a write data transfer and a precharge
153 tWR = Param.Latency("Write recovery time")
154
155 # minimum time between a read and precharge command
156 tRTP = Param.Latency("Read to precharge")
157
158 # time to complete a burst transfer, typically the burst length
159 # divided by two due to the DDR bus, but by making it a parameter
160 # it is easier to also evaluate SDR memories like WideIO.
161 # This parameter has to account for burst length.
162 # Read/Write requests with data size larger than one full burst are broken
163 # down into multiple requests in the controller
164 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
165 # With bank group architectures, tBURST represents the CAS-to-CAS
166 # delay for bursts to different bank groups (tCCD_S)
167 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
168
169 # CAS-to-CAS delay for bursts to the same bank group
170 # only utilized with bank group architectures; set to 0 for default case
171 # tBURST is equivalent to tCCD_S; no explicit parameter required
172 # for CAS-to-CAS delay for bursts to different bank groups
173 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
174
175 # time taken to complete one refresh cycle (N rows in all banks)
176 tRFC = Param.Latency("Refresh cycle time")
177
178 # refresh command interval, how often a "ref" command needs
179 # to be sent. It is 7.8 us for a 64ms refresh requirement
180 tREFI = Param.Latency("Refresh command interval")
181
182 # write-to-read, same rank turnaround penalty
183 tWTR = Param.Latency("Write to read, same rank switching time")
184
185 # read-to-write, same rank turnaround penalty
186 tRTW = Param.Latency("Read to write, same rank switching time")
187
188 # rank-to-rank bus delay penalty
189 # this does not correlate to a memory timing parameter and encompasses:
190 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
191 # different rank bus delay
192 tCS = Param.Latency("Rank to rank switching time")
193
194 # minimum row activate to row activate delay time
195 tRRD = Param.Latency("ACT to ACT delay")
196
197 # only utilized with bank group architectures; set to 0 for default case
198 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
199
200 # time window in which a maximum number of activates are allowed
201 # to take place, set to 0 to disable
202 tXAW = Param.Latency("X activation window")
203 activation_limit = Param.Unsigned("Max number of activates in window")
204
|
| 205 # time to exit power-down mode
206 # Exit power-down to next valid command delay
207 tXP = Param.Latency("0ns", "Power-up Delay")
208
209 # Exit Powerdown to commands requiring a locked DLL
210 tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
211
212 # time to exit self-refresh mode
213 tXS = Param.Latency("0ns", "Self-refresh exit latency")
214
215 # time to exit self-refresh mode with locked DLL
216 tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
217
|
196 # Currently rolled into other params
197 ######################################################################
198
199 # tRC - assumed to be tRAS + tRP
200
| 218 # Currently rolled into other params
219 ######################################################################
220
221 # tRC - assumed to be tRAS + tRP
222
|
| 223 # Power Behaviour and Constraints
224 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
225 # defined as VDD and VDD2. Each current is defined for each voltage domain
226 # separately. For example, current IDD0 is active-precharge current for
227 # voltage domain VDD and current IDD02 is active-precharge current for
228 # voltage domain VDD2.
229 # By default all currents are set to 0mA. Users who are only interested in
230 # the performance of DRAMs can leave them at 0.
231
232 # Operating 1 Bank Active-Precharge current
233 IDD0 = Param.Current("0mA", "Active precharge current")
234
235 # Operating 1 Bank Active-Precharge current multiple voltage Range
236 IDD02 = Param.Current("0mA", "Active precharge current VDD2")
237
238 # Precharge Power-down Current: Slow exit
239 IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
240
241 # Precharge Power-down Current: Slow exit multiple voltage Range
242 IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
243
244 # Precharge Power-down Current: Fast exit
245 IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
246
247 # Precharge Power-down Current: Fast exit multiple voltage Range
248 IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
249
250 # Precharge Standby current
251 IDD2N = Param.Current("0mA", "Precharge Standby current")
252
253 # Precharge Standby current multiple voltage range
254 IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
255
256 # Active Power-down current: slow exit
257 IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
258
259 # Active Power-down current: slow exit multiple voltage range
260 IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
261
262 # Active Power-down current : fast exit
263 IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
264
265 # Active Power-down current : fast exit multiple voltage range
266 IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
267
268 # Active Standby current
269 IDD3N = Param.Current("0mA", "Active Standby current")
270
271 # Active Standby current multiple voltage range
272 IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
273
274 # Burst Read Operating Current
275 IDD4R = Param.Current("0mA", "READ current")
276
277 # Burst Read Operating Current multiple voltage range
278 IDD4R2 = Param.Current("0mA", "READ current VDD2")
279
280 # Burst Write Operating Current
281 IDD4W = Param.Current("0mA", "WRITE current")
282
283 # Burst Write Operating Current multiple voltage range
284 IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
285
286 # Refresh Current
287 IDD5 = Param.Current("0mA", "Refresh current")
288
289 # Refresh Current multiple voltage range
290 IDD52 = Param.Current("0mA", "Refresh current VDD2")
291
292 # Self-Refresh Current
293 IDD6 = Param.Current("0mA", "Self-refresh Current")
294
295 # Self-Refresh Current multiple voltage range
296 IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
297
298 # Main voltage range of the DRAM
299 VDD = Param.Voltage("0V", "Main Voltage Range")
300
301 # Second voltage range defined by some DRAMs
302 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
303
|
201# A single DDR3-1600 x64 channel (one command and address bus), with
202# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
| 304# A single DDR3-1600 x64 channel (one command and address bus), with
305# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
|
203# an 8x8 configuration, amounting to 4 Gbyte of memory.
| 306# an 8x8 configuration.
|
204class DDR3_1600_x64(DRAMCtrl):
205 # 8x8 configuration, 8 devices each with an 8-bit interface
206 device_bus_width = 8
207
208 # DDR3 is a BL8 device
209 burst_length = 8
210
211 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
212 device_rowbuffer_size = '1kB'
213
214 # 8x8 configuration, so 8 devices
215 devices_per_rank = 8
216
217 # Use two ranks
218 ranks_per_channel = 2
219
220 # DDR3 has 8 banks in all configurations
221 banks_per_rank = 8
222
223 # 800 MHz
224 tCK = '1.25ns'
225
226 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
227 tBURST = '5ns'
228
229 # DDR3-1600 11-11-11
230 tRCD = '13.75ns'
231 tCL = '13.75ns'
232 tRP = '13.75ns'
233 tRAS = '35ns'
234 tRRD = '6ns'
235 tXAW = '30ns'
236 activation_limit = 4
237 tRFC = '260ns'
238
239 tWR = '15ns'
240
241 # Greater of 4 CK or 7.5 ns
242 tWTR = '7.5ns'
243
244 # Greater of 4 CK or 7.5 ns
245 tRTP = '7.5ns'
246
247 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
248 tRTW = '2.5ns'
249
250 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
251 tCS = '2.5ns'
252
253 # <=85C, half for >85C
254 tREFI = '7.8us'
255
| 307class DDR3_1600_x64(DRAMCtrl):
308 # 8x8 configuration, 8 devices each with an 8-bit interface
309 device_bus_width = 8
310
311 # DDR3 is a BL8 device
312 burst_length = 8
313
314 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
315 device_rowbuffer_size = '1kB'
316
317 # 8x8 configuration, so 8 devices
318 devices_per_rank = 8
319
320 # Use two ranks
321 ranks_per_channel = 2
322
323 # DDR3 has 8 banks in all configurations
324 banks_per_rank = 8
325
326 # 800 MHz
327 tCK = '1.25ns'
328
329 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
330 tBURST = '5ns'
331
332 # DDR3-1600 11-11-11
333 tRCD = '13.75ns'
334 tCL = '13.75ns'
335 tRP = '13.75ns'
336 tRAS = '35ns'
337 tRRD = '6ns'
338 tXAW = '30ns'
339 activation_limit = 4
340 tRFC = '260ns'
341
342 tWR = '15ns'
343
344 # Greater of 4 CK or 7.5 ns
345 tWTR = '7.5ns'
346
347 # Greater of 4 CK or 7.5 ns
348 tRTP = '7.5ns'
349
350 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
351 tRTW = '2.5ns'
352
353 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
354 tCS = '2.5ns'
355
356 # <=85C, half for >85C
357 tREFI = '7.8us'
358
|
| 359 # Current values from datasheet
360 IDD0 = '75mA'
361 IDD2N = '50mA'
362 IDD3N = '57mA'
363 IDD4W = '165mA'
364 IDD4R = '187mA'
365 IDD5 = '220mA'
366 VDD = '1.5V'
367
|
256# A single DDR3-2133 x64 channel refining a selected subset of the
257# options for the DDR-1600 configuration, based on the same DDR3-1600
258# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
259# consistent across the two configurations.
260class DDR3_2133_x64(DDR3_1600_x64):
261 # 1066 MHz
262 tCK = '0.938ns'
263
264 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
265 tBURST = '3.752ns'
266
267 # DDR3-2133 14-14-14
268 tRCD = '13.09ns'
269 tCL = '13.09ns'
270 tRP = '13.09ns'
271 tRAS = '33ns'
272 tRRD = '5ns'
273 tXAW = '25ns'
274
| 368# A single DDR3-2133 x64 channel refining a selected subset of the
369# options for the DDR-1600 configuration, based on the same DDR3-1600
370# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
371# consistent across the two configurations.
372class DDR3_2133_x64(DDR3_1600_x64):
373 # 1066 MHz
374 tCK = '0.938ns'
375
376 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
377 tBURST = '3.752ns'
378
379 # DDR3-2133 14-14-14
380 tRCD = '13.09ns'
381 tCL = '13.09ns'
382 tRP = '13.09ns'
383 tRAS = '33ns'
384 tRRD = '5ns'
385 tXAW = '25ns'
386
|
| 387 # Current values from datasheet
388 IDD0 = '70mA'
389 IDD2N = '37mA'
390 IDD3N = '44mA'
391 IDD4W = '157mA'
392 IDD4R = '191mA'
393 IDD5 = '250mA'
394 VDD = '1.5V'
395
|
275# A single DDR4-2400 x64 channel (one command and address bus), with
| 396# A single DDR4-2400 x64 channel (one command and address bus), with
|
276# timings based on a DDR4-2400 4 Gbit datasheet (Samsung K4A4G085WD)
277# in an 8x8 configuration, amounting to 4 Gbyte of memory.
| 397# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8)
398# in an 8x8 configuration.
|
278class DDR4_2400_x64(DRAMCtrl):
279 # 8x8 configuration, 8 devices each with an 8-bit interface
280 device_bus_width = 8
281
282 # DDR4 is a BL8 device
283 burst_length = 8
284
285 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
286 device_rowbuffer_size = '1kB'
287
288 # 8x8 configuration, so 8 devices
289 devices_per_rank = 8
290
| 399class DDR4_2400_x64(DRAMCtrl):
400 # 8x8 configuration, 8 devices each with an 8-bit interface
401 device_bus_width = 8
402
403 # DDR4 is a BL8 device
404 burst_length = 8
405
406 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
407 device_rowbuffer_size = '1kB'
408
409 # 8x8 configuration, so 8 devices
410 devices_per_rank = 8
411
|
291 # Use a single rank
292 ranks_per_channel = 1
| 412 # Match our DDR3 configurations which is dual rank
413 ranks_per_channel = 2
|
293
294 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
295 # Set to 4 for x4, x8 case
296 bank_groups_per_rank = 4
297
298 # DDR4 has 16 banks (4 bank groups) in all
299 # configurations. Currently we do not capture the additional
300 # constraints incurred by the bank groups
301 banks_per_rank = 16
302
303 # 1200 MHz
304 tCK = '0.833ns'
305
306 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
307 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
308 # With bank group architectures, tBURST represents the CAS-to-CAS
309 # delay for bursts to different bank groups (tCCD_S)
310 tBURST = '3.333ns'
311
312 # @2400 data rate, tCCD_L is 6 CK
313 # CAS-to-CAS delay for bursts to the same bank group
314 # tBURST is equivalent to tCCD_S; no explicit parameter required
315 # for CAS-to-CAS delay for bursts to different bank groups
316 tCCD_L = '5ns';
317
318 # DDR4-2400 17-17-17
319 tRCD = '14.16ns'
320 tCL = '14.16ns'
321 tRP = '14.16ns'
322 tRAS = '32ns'
323
324 # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
325 tRRD = '3.3ns'
326
327 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
328 tRRD_L = '4.9ns';
329
330 tXAW = '21ns'
331 activation_limit = 4
| 414
415 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
416 # Set to 4 for x4, x8 case
417 bank_groups_per_rank = 4
418
419 # DDR4 has 16 banks (4 bank groups) in all
420 # configurations. Currently we do not capture the additional
421 # constraints incurred by the bank groups
422 banks_per_rank = 16
423
424 # 1200 MHz
425 tCK = '0.833ns'
426
427 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
428 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
429 # With bank group architectures, tBURST represents the CAS-to-CAS
430 # delay for bursts to different bank groups (tCCD_S)
431 tBURST = '3.333ns'
432
433 # @2400 data rate, tCCD_L is 6 CK
434 # CAS-to-CAS delay for bursts to the same bank group
435 # tBURST is equivalent to tCCD_S; no explicit parameter required
436 # for CAS-to-CAS delay for bursts to different bank groups
437 tCCD_L = '5ns';
438
439 # DDR4-2400 17-17-17
440 tRCD = '14.16ns'
441 tCL = '14.16ns'
442 tRP = '14.16ns'
443 tRAS = '32ns'
444
445 # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns)
446 tRRD = '3.3ns'
447
448 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
449 tRRD_L = '4.9ns';
450
451 tXAW = '21ns'
452 activation_limit = 4
|
332 tRFC = '260ns'
| 453 tRFC = '350ns'
|
333
334 tWR = '15ns'
335
336 # Here using the average of WTR_S and WTR_L
337 tWTR = '5ns'
338
339 # Greater of 4 CK or 7.5 ns
340 tRTP = '7.5ns'
341
342 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
343 tRTW = '1.666ns'
344
345 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
346 tCS = '1.666ns'
347
348 # <=85C, half for >85C
349 tREFI = '7.8us'
350
| 454
455 tWR = '15ns'
456
457 # Here using the average of WTR_S and WTR_L
458 tWTR = '5ns'
459
460 # Greater of 4 CK or 7.5 ns
461 tRTP = '7.5ns'
462
463 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
464 tRTW = '1.666ns'
465
466 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
467 tCS = '1.666ns'
468
469 # <=85C, half for >85C
470 tREFI = '7.8us'
471
|
| 472 # Current values from datasheet
473 IDD0 = '64mA'
474 IDD02 = '4mA'
475 IDD2N = '50mA'
476 IDD3N = '67mA'
477 IDD3N2 = '3mA'
478 IDD4W = '180mA'
479 IDD4R = '160mA'
480 IDD5 = '192mA'
481 VDD = '1.2V'
482 VDD2 = '2.5V'
483
|
351# A single LPDDR2-S4 x32 interface (one command/address bus), with
| 484# A single LPDDR2-S4 x32 interface (one command/address bus), with
|
352# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32
353# configuration.
| 485# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
486# in a 1x32 configuration.
|
354class LPDDR2_S4_1066_x32(DRAMCtrl):
| 487class LPDDR2_S4_1066_x32(DRAMCtrl):
|
| 488 # No DLL in LPDDR2
489 dll = False
490
|
355 # 1x32 configuration, 1 device with a 32-bit interface
356 device_bus_width = 32
357
358 # LPDDR2_S4 is a BL4 and BL8 device
359 burst_length = 8
360
361 # Each device has a page (row buffer) size of 1KB
362 # (this depends on the memory density)
363 device_rowbuffer_size = '1kB'
364
365 # 1x32 configuration, so 1 device
366 devices_per_rank = 1
367
368 # Use a single rank
369 ranks_per_channel = 1
370
371 # LPDDR2-S4 has 8 banks in all configurations
372 banks_per_rank = 8
373
374 # 533 MHz
375 tCK = '1.876ns'
376
377 # Fixed at 15 ns
378 tRCD = '15ns'
379
380 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
381 tCL = '15ns'
382
383 # Pre-charge one bank 15 ns (all banks 18 ns)
384 tRP = '15ns'
385
386 tRAS = '42ns'
387 tWR = '15ns'
388
| 491 # 1x32 configuration, 1 device with a 32-bit interface
492 device_bus_width = 32
493
494 # LPDDR2_S4 is a BL4 and BL8 device
495 burst_length = 8
496
497 # Each device has a page (row buffer) size of 1KB
498 # (this depends on the memory density)
499 device_rowbuffer_size = '1kB'
500
501 # 1x32 configuration, so 1 device
502 devices_per_rank = 1
503
504 # Use a single rank
505 ranks_per_channel = 1
506
507 # LPDDR2-S4 has 8 banks in all configurations
508 banks_per_rank = 8
509
510 # 533 MHz
511 tCK = '1.876ns'
512
513 # Fixed at 15 ns
514 tRCD = '15ns'
515
516 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
517 tCL = '15ns'
518
519 # Pre-charge one bank 15 ns (all banks 18 ns)
520 tRP = '15ns'
521
522 tRAS = '42ns'
523 tWR = '15ns'
524
|
389 # 6 CK read to precharge delay
390 tRTP = '11.256ns'
| 525 tRTP = '7.5ns'
|
391
392 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
393 # Note this is a BL8 DDR device.
394 # Requests larger than 32 bytes are broken down into multiple requests
395 # in the controller
396 tBURST = '7.5ns'
397
398 # LPDDR2-S4, 4 Gbit
399 tRFC = '130ns'
400 tREFI = '3.9us'
401
402 # Irrespective of speed grade, tWTR is 7.5 ns
403 tWTR = '7.5ns'
404
405 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
406 tRTW = '3.75ns'
407
408 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
409 tCS = '3.75ns'
410
411 # Activate to activate irrespective of density and speed grade
412 tRRD = '10.0ns'
413
414 # Irrespective of density, tFAW is 50 ns
415 tXAW = '50ns'
416 activation_limit = 4
417
| 526
527 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
528 # Note this is a BL8 DDR device.
529 # Requests larger than 32 bytes are broken down into multiple requests
530 # in the controller
531 tBURST = '7.5ns'
532
533 # LPDDR2-S4, 4 Gbit
534 tRFC = '130ns'
535 tREFI = '3.9us'
536
537 # Irrespective of speed grade, tWTR is 7.5 ns
538 tWTR = '7.5ns'
539
540 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
541 tRTW = '3.75ns'
542
543 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
544 tCS = '3.75ns'
545
546 # Activate to activate irrespective of density and speed grade
547 tRRD = '10.0ns'
548
549 # Irrespective of density, tFAW is 50 ns
550 tXAW = '50ns'
551 activation_limit = 4
552
|
| 553 # Current values from datasheet
554 IDD0 = '15mA'
555 IDD02 = '70mA'
556 IDD2N = '2mA'
557 IDD2N2 = '30mA'
558 IDD3N = '2.5mA'
559 IDD3N2 = '30mA'
560 IDD4W = '10mA'
561 IDD4W2 = '190mA'
562 IDD4R = '3mA'
563 IDD4R2 = '220mA'
564 IDD5 = '40mA'
565 IDD52 = '150mA'
566 VDD = '1.8V'
567 VDD2 = '1.2V'
568
|
418# A single WideIO x128 interface (one command and address bus), with
419# default timings based on an estimated WIO-200 8 Gbit part.
420class WideIO_200_x128(DRAMCtrl):
| 569# A single WideIO x128 interface (one command and address bus), with
570# default timings based on an estimated WIO-200 8 Gbit part.
571class WideIO_200_x128(DRAMCtrl):
|
| 572 # No DLL for WideIO
573 dll = False
574
|
421 # 1x128 configuration, 1 device with a 128-bit interface
422 device_bus_width = 128
423
424 # This is a BL4 device
425 burst_length = 4
426
427 # Each device has a page (row buffer) size of 4KB
428 # (this depends on the memory density)
429 device_rowbuffer_size = '4kB'
430
431 # 1x128 configuration, so 1 device
432 devices_per_rank = 1
433
434 # Use one rank for a one-high die stack
435 ranks_per_channel = 1
436
437 # WideIO has 4 banks in all configurations
438 banks_per_rank = 4
439
440 # 200 MHz
441 tCK = '5ns'
442
443 # WIO-200
444 tRCD = '18ns'
445 tCL = '18ns'
446 tRP = '18ns'
447 tRAS = '42ns'
448 tWR = '15ns'
449 # Read to precharge is same as the burst
450 tRTP = '20ns'
451
452 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
453 # Note this is a BL4 SDR device.
454 tBURST = '20ns'
455
456 # WIO 8 Gb
457 tRFC = '210ns'
458
459 # WIO 8 Gb, <=85C, half for >85C
460 tREFI = '3.9us'
461
462 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
463 tWTR = '15ns'
464
465 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
466 tRTW = '10ns'
467
468 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
469 tCS = '10ns'
470
471 # Activate to activate irrespective of density and speed grade
472 tRRD = '10.0ns'
473
474 # Two instead of four activation window
475 tXAW = '50ns'
476 activation_limit = 2
477
| 575 # 1x128 configuration, 1 device with a 128-bit interface
576 device_bus_width = 128
577
578 # This is a BL4 device
579 burst_length = 4
580
581 # Each device has a page (row buffer) size of 4KB
582 # (this depends on the memory density)
583 device_rowbuffer_size = '4kB'
584
585 # 1x128 configuration, so 1 device
586 devices_per_rank = 1
587
588 # Use one rank for a one-high die stack
589 ranks_per_channel = 1
590
591 # WideIO has 4 banks in all configurations
592 banks_per_rank = 4
593
594 # 200 MHz
595 tCK = '5ns'
596
597 # WIO-200
598 tRCD = '18ns'
599 tCL = '18ns'
600 tRP = '18ns'
601 tRAS = '42ns'
602 tWR = '15ns'
603 # Read to precharge is same as the burst
604 tRTP = '20ns'
605
606 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
607 # Note this is a BL4 SDR device.
608 tBURST = '20ns'
609
610 # WIO 8 Gb
611 tRFC = '210ns'
612
613 # WIO 8 Gb, <=85C, half for >85C
614 tREFI = '3.9us'
615
616 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
617 tWTR = '15ns'
618
619 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
620 tRTW = '10ns'
621
622 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
623 tCS = '10ns'
624
625 # Activate to activate irrespective of density and speed grade
626 tRRD = '10.0ns'
627
628 # Two instead of four activation window
629 tXAW = '50ns'
630 activation_limit = 2
631
|
| 632 # The WideIO specification does not provide current information
633
|
478# A single LPDDR3 x32 interface (one command/address bus), with
| 634# A single LPDDR3 x32 interface (one command/address bus), with
|
479# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32
480# configuration
| 635# default timings based on a LPDDR3-1600 4 Gbit part (Micron
636# EDF8132A1MC) in a 1x32 configuration.
|
481class LPDDR3_1600_x32(DRAMCtrl):
| 637class LPDDR3_1600_x32(DRAMCtrl):
|
| 638 # No DLL for LPDDR3
639 dll = False
640
|
482 # 1x32 configuration, 1 device with a 32-bit interface
483 device_bus_width = 32
484
485 # LPDDR3 is a BL8 device
486 burst_length = 8
487
488 # Each device has a page (row buffer) size of 4KB
489 device_rowbuffer_size = '4kB'
490
491 # 1x32 configuration, so 1 device
492 devices_per_rank = 1
493
| 641 # 1x32 configuration, 1 device with a 32-bit interface
642 device_bus_width = 32
643
644 # LPDDR3 is a BL8 device
645 burst_length = 8
646
647 # Each device has a page (row buffer) size of 4KB
648 device_rowbuffer_size = '4kB'
649
650 # 1x32 configuration, so 1 device
651 devices_per_rank = 1
652
|
494 # Use a single rank
| 653 # Technically the datasheet is a dual-rank package, but for
654 # comparison with the LPDDR2 config we stick to a single rank
|
495 ranks_per_channel = 1
496
497 # LPDDR3 has 8 banks in all configurations
498 banks_per_rank = 8
499
500 # 800 MHz
501 tCK = '1.25ns'
502
| 655 ranks_per_channel = 1
656
657 # LPDDR3 has 8 banks in all configurations
658 banks_per_rank = 8
659
660 # 800 MHz
661 tCK = '1.25ns'
662
|
503 # Fixed at 15 ns
504 tRCD = '15ns'
| 663 tRCD = '18ns'
|
505
506 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
507 tCL = '15ns'
508
509 tRAS = '42ns'
510 tWR = '15ns'
511
512 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
513 tRTP = '7.5ns'
514
| 664
665 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
666 tCL = '15ns'
667
668 tRAS = '42ns'
669 tWR = '15ns'
670
671 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
672 tRTP = '7.5ns'
673
|
515 # Pre-charge one bank 15 ns (all banks 18 ns)
516 tRP = '15ns'
| 674 # Pre-charge one bank 18 ns (all banks 21 ns)
675 tRP = '18ns'
|
517
518 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
519 # Note this is a BL8 DDR device.
520 # Requests larger than 32 bytes are broken down into multiple requests
521 # in the controller
522 tBURST = '5ns'
523
524 # LPDDR3, 4 Gb
525 tRFC = '130ns'
526 tREFI = '3.9us'
527
528 # Irrespective of speed grade, tWTR is 7.5 ns
529 tWTR = '7.5ns'
530
531 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
532 tRTW = '2.5ns'
533
534 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
535 tCS = '2.5ns'
536
537 # Activate to activate irrespective of density and speed grade
538 tRRD = '10.0ns'
539
540 # Irrespective of size, tFAW is 50 ns
541 tXAW = '50ns'
542 activation_limit = 4
| 676
677 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
678 # Note this is a BL8 DDR device.
679 # Requests larger than 32 bytes are broken down into multiple requests
680 # in the controller
681 tBURST = '5ns'
682
683 # LPDDR3, 4 Gb
684 tRFC = '130ns'
685 tREFI = '3.9us'
686
687 # Irrespective of speed grade, tWTR is 7.5 ns
688 tWTR = '7.5ns'
689
690 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
691 tRTW = '2.5ns'
692
693 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
694 tCS = '2.5ns'
695
696 # Activate to activate irrespective of density and speed grade
697 tRRD = '10.0ns'
698
699 # Irrespective of size, tFAW is 50 ns
700 tXAW = '50ns'
701 activation_limit = 4
|
| 702
703 # Current values from datasheet
704 IDD0 = '8mA'
705 IDD02 = '60mA'
706 IDD2N = '0.8mA'
707 IDD2N2 = '26mA'
708 IDD3N = '2mA'
709 IDD3N2 = '34mA'
710 IDD4W = '2mA'
711 IDD4W2 = '190mA'
712 IDD4R = '2mA'
713 IDD4R2 = '230mA'
714 IDD5 = '28mA'
715 IDD52 = '150mA'
716 VDD = '1.8V'
717 VDD2 = '1.2V'
|
| |