1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2013 Amin Farmahini-Farahani
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Andreas Hansson
40# Ani Udipi
41
42from m5.params import *
43from AbstractMemory import *
44
45# Enum for memory scheduling algorithms, currently First-Come
46# First-Served and a First-Row Hit then First-Come First-Served
47class MemSched(Enum): vals = ['fcfs', 'frfcfs']
48
49# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
50# channel, rank, bank, row and column, respectively, and going from
51# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
52# suitable for an open-page policy, optimising for sequential accesses
53# hitting in the open row. For a closed-page policy, RoCoRaBaCh
54# maximises parallelism.
55class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
56
57# Enum for the page policy, either open, open_adaptive, close, or
58# close_adaptive.
59class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
60 'close_adaptive']
61
62# DRAMCtrl is a single-channel single-ported DRAM controller model
63# that aims to model the most important system-level performance
64# effects of a DRAM without getting into too much detail of the DRAM
65# itself.
66class DRAMCtrl(AbstractMemory):
67 type = 'DRAMCtrl'
68 cxx_header = "mem/dram_ctrl.hh"
69
70 # single-ported on the system interface side, instantiate with a
71 # bus in front of the controller for multiple ports
72 port = SlavePort("Slave port")
73
74 # the basic configuration of the controller architecture
75 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
76 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
77
78 # threshold in percent for when to forcefully trigger writes and
79 # start emptying the write buffer
80 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
81
82 # threshold in percentage for when to start writes if the read
83 # queue is empty
84 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
85
86 # minimum write bursts to schedule before switching back to reads
87 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
88 "switching to reads")
89
90 # scheduler, address map and page policy
91 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
92 addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy")
93 page_policy = Param.PageManage('open_adaptive', "Page management policy")
94
95 # enforce a limit on the number of accesses per row
96 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
97 "closing");
98
99 # pipeline latency of the controller and PHY, split into a
100 # frontend part and a backend part, with reads and writes serviced
101 # by the queues only seeing the frontend contribution, and reads
102 # serviced by the memory seeing the sum of the two
103 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
104 static_backend_latency = Param.Latency("10ns", "Static backend latency")
105
106 # the physical organisation of the DRAM
107 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
108 "device/chip")
109 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
110 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
111 "device/chip")
112 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
113 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
114 banks_per_rank = Param.Unsigned("Number of banks per rank")
115 # only used for the address mapping as the controller by
116 # construction is a single channel and multiple controllers have
117 # to be instantiated for a multi-channel configuration
118 channels = Param.Unsigned(1, "Number of channels")
119
120 # timing behaviour and constraints - all in nanoseconds
121
122 # the amount of time in nanoseconds from issuing an activate command
123 # to the data being available in the row buffer for a read/write
124 tRCD = Param.Latency("RAS to CAS delay")
125
126 # the time from issuing a read/write command to seeing the actual data
127 tCL = Param.Latency("CAS latency")
128
129 # minimum time between a precharge and subsequent activate
130 tRP = Param.Latency("Row precharge time")
131
132 # minimum time between an activate and a precharge to the same row
133 tRAS = Param.Latency("ACT to PRE delay")
134
| 1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2013 Amin Farmahini-Farahani
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Andreas Hansson
40# Ani Udipi
41
42from m5.params import *
43from AbstractMemory import *
44
45# Enum for memory scheduling algorithms, currently First-Come
46# First-Served and a First-Row Hit then First-Come First-Served
47class MemSched(Enum): vals = ['fcfs', 'frfcfs']
48
49# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
50# channel, rank, bank, row and column, respectively, and going from
51# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
52# suitable for an open-page policy, optimising for sequential accesses
53# hitting in the open row. For a closed-page policy, RoCoRaBaCh
54# maximises parallelism.
55class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
56
57# Enum for the page policy, either open, open_adaptive, close, or
58# close_adaptive.
59class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
60 'close_adaptive']
61
62# DRAMCtrl is a single-channel single-ported DRAM controller model
63# that aims to model the most important system-level performance
64# effects of a DRAM without getting into too much detail of the DRAM
65# itself.
66class DRAMCtrl(AbstractMemory):
67 type = 'DRAMCtrl'
68 cxx_header = "mem/dram_ctrl.hh"
69
70 # single-ported on the system interface side, instantiate with a
71 # bus in front of the controller for multiple ports
72 port = SlavePort("Slave port")
73
74 # the basic configuration of the controller architecture
75 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
76 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
77
78 # threshold in percent for when to forcefully trigger writes and
79 # start emptying the write buffer
80 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
81
82 # threshold in percentage for when to start writes if the read
83 # queue is empty
84 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
85
86 # minimum write bursts to schedule before switching back to reads
87 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
88 "switching to reads")
89
90 # scheduler, address map and page policy
91 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
92 addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy")
93 page_policy = Param.PageManage('open_adaptive', "Page management policy")
94
95 # enforce a limit on the number of accesses per row
96 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
97 "closing");
98
99 # pipeline latency of the controller and PHY, split into a
100 # frontend part and a backend part, with reads and writes serviced
101 # by the queues only seeing the frontend contribution, and reads
102 # serviced by the memory seeing the sum of the two
103 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
104 static_backend_latency = Param.Latency("10ns", "Static backend latency")
105
106 # the physical organisation of the DRAM
107 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
108 "device/chip")
109 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
110 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
111 "device/chip")
112 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
113 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
114 banks_per_rank = Param.Unsigned("Number of banks per rank")
115 # only used for the address mapping as the controller by
116 # construction is a single channel and multiple controllers have
117 # to be instantiated for a multi-channel configuration
118 channels = Param.Unsigned(1, "Number of channels")
119
120 # timing behaviour and constraints - all in nanoseconds
121
122 # the amount of time in nanoseconds from issuing an activate command
123 # to the data being available in the row buffer for a read/write
124 tRCD = Param.Latency("RAS to CAS delay")
125
126 # the time from issuing a read/write command to seeing the actual data
127 tCL = Param.Latency("CAS latency")
128
129 # minimum time between a precharge and subsequent activate
130 tRP = Param.Latency("Row precharge time")
131
132 # minimum time between an activate and a precharge to the same row
133 tRAS = Param.Latency("ACT to PRE delay")
134
|
| 135 # minimum time between a write data transfer and a precharge
136 tWR = Param.Latency("Write recovery time")
137
|
135 # time to complete a burst transfer, typically the burst length
136 # divided by two due to the DDR bus, but by making it a parameter
137 # it is easier to also evaluate SDR memories like WideIO.
138 # This parameter has to account for burst length.
139 # Read/Write requests with data size larger than one full burst are broken
140 # down into multiple requests in the controller
141 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
142
143 # time taken to complete one refresh cycle (N rows in all banks)
144 tRFC = Param.Latency("Refresh cycle time")
145
146 # refresh command interval, how often a "ref" command needs
147 # to be sent. It is 7.8 us for a 64ms refresh requirement
148 tREFI = Param.Latency("Refresh command interval")
149
150 # write-to-read turn around penalty
151 tWTR = Param.Latency("Write to read switching time")
152
153 # read-to-write turn around penalty, bus turnaround delay
154 tRTW = Param.Latency("Read to write switching time")
155
156 # minimum row activate to row activate delay time
157 tRRD = Param.Latency("ACT to ACT delay")
158
159 # time window in which a maximum number of activates are allowed
160 # to take place, set to 0 to disable
161 tXAW = Param.Latency("X activation window")
162 activation_limit = Param.Unsigned("Max number of activates in window")
163
164 # Currently rolled into other params
165 ######################################################################
166
167 # tRC - assumed to be tRAS + tRP
168
169# A single DDR3 x64 interface (one command and address bus), with
170# default timings based on DDR3-1600 4 Gbit parts in an 8x8
171# configuration, which would amount to 4 Gbyte of memory.
172class DDR3_1600_x64(DRAMCtrl):
173 # 8x8 configuration, 8 devices each with an 8-bit interface
174 device_bus_width = 8
175
176 # DDR3 is a BL8 device
177 burst_length = 8
178
179 # Each device has a page (row buffer) size of 1KB
180 # (this depends on the memory density)
181 device_rowbuffer_size = '1kB'
182
183 # 8x8 configuration, so 8 devices
184 devices_per_rank = 8
185
186 # Use two ranks
187 ranks_per_channel = 2
188
189 # DDR3 has 8 banks in all configurations
190 banks_per_rank = 8
191
192 # DDR3-1600 11-11-11-28
193 tRCD = '13.75ns'
194 tCL = '13.75ns'
195 tRP = '13.75ns'
196 tRAS = '35ns'
| 138 # time to complete a burst transfer, typically the burst length
139 # divided by two due to the DDR bus, but by making it a parameter
140 # it is easier to also evaluate SDR memories like WideIO.
141 # This parameter has to account for burst length.
142 # Read/Write requests with data size larger than one full burst are broken
143 # down into multiple requests in the controller
144 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
145
146 # time taken to complete one refresh cycle (N rows in all banks)
147 tRFC = Param.Latency("Refresh cycle time")
148
149 # refresh command interval, how often a "ref" command needs
150 # to be sent. It is 7.8 us for a 64ms refresh requirement
151 tREFI = Param.Latency("Refresh command interval")
152
153 # write-to-read turn around penalty
154 tWTR = Param.Latency("Write to read switching time")
155
156 # read-to-write turn around penalty, bus turnaround delay
157 tRTW = Param.Latency("Read to write switching time")
158
159 # minimum row activate to row activate delay time
160 tRRD = Param.Latency("ACT to ACT delay")
161
162 # time window in which a maximum number of activates are allowed
163 # to take place, set to 0 to disable
164 tXAW = Param.Latency("X activation window")
165 activation_limit = Param.Unsigned("Max number of activates in window")
166
167 # Currently rolled into other params
168 ######################################################################
169
170 # tRC - assumed to be tRAS + tRP
171
172# A single DDR3 x64 interface (one command and address bus), with
173# default timings based on DDR3-1600 4 Gbit parts in an 8x8
174# configuration, which would amount to 4 Gbyte of memory.
175class DDR3_1600_x64(DRAMCtrl):
176 # 8x8 configuration, 8 devices each with an 8-bit interface
177 device_bus_width = 8
178
179 # DDR3 is a BL8 device
180 burst_length = 8
181
182 # Each device has a page (row buffer) size of 1KB
183 # (this depends on the memory density)
184 device_rowbuffer_size = '1kB'
185
186 # 8x8 configuration, so 8 devices
187 devices_per_rank = 8
188
189 # Use two ranks
190 ranks_per_channel = 2
191
192 # DDR3 has 8 banks in all configurations
193 banks_per_rank = 8
194
195 # DDR3-1600 11-11-11-28
196 tRCD = '13.75ns'
197 tCL = '13.75ns'
198 tRP = '13.75ns'
199 tRAS = '35ns'
|
| 200 tWR = '15ns'
|
197
198 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz.
199 # Note this is a BL8 DDR device.
200 tBURST = '5ns'
201
202 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns
203 tRFC = '300ns'
204
205 # DDR3, <=85C, half for >85C
206 tREFI = '7.8us'
207
208 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
209 tWTR = '7.5ns'
210
211 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
212 tRTW = '2.5ns'
213
214 # Assume 5 CK for activate to activate for different banks
215 tRRD = '6.25ns'
216
217 # With a 2kbyte page size, DDR3-1600 lands around 40 ns
218 tXAW = '40ns'
219 activation_limit = 4
220
221
222# A single DDR3 x64 interface (one command and address bus), with
223# default timings based on DDR3-1333 4 Gbit parts in an 8x8
224# configuration, which would amount to 4 GByte of memory. This
225# configuration is primarily for comparing with DRAMSim2, and all the
226# parameters except ranks_per_channel are based on the DRAMSim2 config
227# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has
228# to be manually set, depending on size of the memory to be
229# simulated. By default DRAMSim2 has 2048MB of memory with a single
230# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2
231class DDR3_1333_x64_DRAMSim2(DRAMCtrl):
232 # 8x8 configuration, 8 devices each with an 8-bit interface
233 device_bus_width = 8
234
235 # DDR3 is a BL8 device
236 burst_length = 8
237
238 # Each device has a page (row buffer) size of 1KB
239 # (this depends on the memory density)
240 device_rowbuffer_size = '1kB'
241
242 # 8x8 configuration, so 8 devices
243 devices_per_rank = 8
244
245 # Use two ranks
246 ranks_per_channel = 2
247
248 # DDR3 has 8 banks in all configurations
249 banks_per_rank = 8
250
251 tRCD = '15ns'
252 tCL = '15ns'
253 tRP = '15ns'
254 tRAS = '36ns'
| 201
202 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz.
203 # Note this is a BL8 DDR device.
204 tBURST = '5ns'
205
206 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns
207 tRFC = '300ns'
208
209 # DDR3, <=85C, half for >85C
210 tREFI = '7.8us'
211
212 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
213 tWTR = '7.5ns'
214
215 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
216 tRTW = '2.5ns'
217
218 # Assume 5 CK for activate to activate for different banks
219 tRRD = '6.25ns'
220
221 # With a 2kbyte page size, DDR3-1600 lands around 40 ns
222 tXAW = '40ns'
223 activation_limit = 4
224
225
226# A single DDR3 x64 interface (one command and address bus), with
227# default timings based on DDR3-1333 4 Gbit parts in an 8x8
228# configuration, which would amount to 4 GByte of memory. This
229# configuration is primarily for comparing with DRAMSim2, and all the
230# parameters except ranks_per_channel are based on the DRAMSim2 config
231# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has
232# to be manually set, depending on size of the memory to be
233# simulated. By default DRAMSim2 has 2048MB of memory with a single
234# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2
235class DDR3_1333_x64_DRAMSim2(DRAMCtrl):
236 # 8x8 configuration, 8 devices each with an 8-bit interface
237 device_bus_width = 8
238
239 # DDR3 is a BL8 device
240 burst_length = 8
241
242 # Each device has a page (row buffer) size of 1KB
243 # (this depends on the memory density)
244 device_rowbuffer_size = '1kB'
245
246 # 8x8 configuration, so 8 devices
247 devices_per_rank = 8
248
249 # Use two ranks
250 ranks_per_channel = 2
251
252 # DDR3 has 8 banks in all configurations
253 banks_per_rank = 8
254
255 tRCD = '15ns'
256 tCL = '15ns'
257 tRP = '15ns'
258 tRAS = '36ns'
|
| 259 tWR = '15ns'
|
255
256 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz.
257 # Note this is a BL8 DDR device.
258 tBURST = '6ns'
259
260 tRFC = '160ns'
261
262 # DDR3, <=85C, half for >85C
263 tREFI = '7.8us'
264
265 # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns
266 tWTR = '7.5ns'
267
268 # Default read-to-write bus around to 2 CK, @666.66 MHz = 3 ns
269 tRTW = '3ns'
270
271 tRRD = '6.0ns'
272
273 tXAW = '30ns'
274 activation_limit = 4
275
276
277# A single LPDDR2-S4 x32 interface (one command/address bus), with
278# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32
279# configuration.
280class LPDDR2_S4_1066_x32(DRAMCtrl):
281 # 1x32 configuration, 1 device with a 32-bit interface
282 device_bus_width = 32
283
284 # LPDDR2_S4 is a BL4 and BL8 device
285 burst_length = 8
286
287 # Each device has a page (row buffer) size of 1KB
288 # (this depends on the memory density)
289 device_rowbuffer_size = '1kB'
290
291 # 1x32 configuration, so 1 device
292 devices_per_rank = 1
293
294 # Use a single rank
295 ranks_per_channel = 1
296
297 # LPDDR2-S4 has 8 banks in all configurations
298 banks_per_rank = 8
299
300 # Fixed at 15 ns
301 tRCD = '15ns'
302
303 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
304 tCL = '15ns'
305
306 # Pre-charge one bank 15 ns (all banks 18 ns)
307 tRP = '15ns'
308
309 tRAS = '42ns'
| 260
261 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz.
262 # Note this is a BL8 DDR device.
263 tBURST = '6ns'
264
265 tRFC = '160ns'
266
267 # DDR3, <=85C, half for >85C
268 tREFI = '7.8us'
269
270 # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns
271 tWTR = '7.5ns'
272
273 # Default read-to-write bus around to 2 CK, @666.66 MHz = 3 ns
274 tRTW = '3ns'
275
276 tRRD = '6.0ns'
277
278 tXAW = '30ns'
279 activation_limit = 4
280
281
282# A single LPDDR2-S4 x32 interface (one command/address bus), with
283# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32
284# configuration.
285class LPDDR2_S4_1066_x32(DRAMCtrl):
286 # 1x32 configuration, 1 device with a 32-bit interface
287 device_bus_width = 32
288
289 # LPDDR2_S4 is a BL4 and BL8 device
290 burst_length = 8
291
292 # Each device has a page (row buffer) size of 1KB
293 # (this depends on the memory density)
294 device_rowbuffer_size = '1kB'
295
296 # 1x32 configuration, so 1 device
297 devices_per_rank = 1
298
299 # Use a single rank
300 ranks_per_channel = 1
301
302 # LPDDR2-S4 has 8 banks in all configurations
303 banks_per_rank = 8
304
305 # Fixed at 15 ns
306 tRCD = '15ns'
307
308 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
309 tCL = '15ns'
310
311 # Pre-charge one bank 15 ns (all banks 18 ns)
312 tRP = '15ns'
313
314 tRAS = '42ns'
|
| 315 tWR = '15ns'
|
310
311 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
312 # Note this is a BL8 DDR device.
313 # Requests larger than 32 bytes are broken down into multiple requests
314 # in the controller
315 tBURST = '7.5ns'
316
317 # LPDDR2-S4, 4 Gbit
318 tRFC = '130ns'
319 tREFI = '3.9us'
320
321 # Irrespective of speed grade, tWTR is 7.5 ns
322 tWTR = '7.5ns'
323
324 # Default read-to-write bus around to 2 CK, @533 MHz = 3.75 ns
325 tRTW = '3.75ns'
326
327 # Activate to activate irrespective of density and speed grade
328 tRRD = '10.0ns'
329
330 # Irrespective of density, tFAW is 50 ns
331 tXAW = '50ns'
332 activation_limit = 4
333
334# A single WideIO x128 interface (one command and address bus), with
335# default timings based on an estimated WIO-200 8 Gbit part.
336class WideIO_200_x128(DRAMCtrl):
337 # 1x128 configuration, 1 device with a 128-bit interface
338 device_bus_width = 128
339
340 # This is a BL4 device
341 burst_length = 4
342
343 # Each device has a page (row buffer) size of 4KB
344 # (this depends on the memory density)
345 device_rowbuffer_size = '4kB'
346
347 # 1x128 configuration, so 1 device
348 devices_per_rank = 1
349
350 # Use one rank for a one-high die stack
351 ranks_per_channel = 1
352
353 # WideIO has 4 banks in all configurations
354 banks_per_rank = 4
355
356 # WIO-200
357 tRCD = '18ns'
358 tCL = '18ns'
359 tRP = '18ns'
360 tRAS = '42ns'
| 316
317 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
318 # Note this is a BL8 DDR device.
319 # Requests larger than 32 bytes are broken down into multiple requests
320 # in the controller
321 tBURST = '7.5ns'
322
323 # LPDDR2-S4, 4 Gbit
324 tRFC = '130ns'
325 tREFI = '3.9us'
326
327 # Irrespective of speed grade, tWTR is 7.5 ns
328 tWTR = '7.5ns'
329
330 # Default read-to-write bus around to 2 CK, @533 MHz = 3.75 ns
331 tRTW = '3.75ns'
332
333 # Activate to activate irrespective of density and speed grade
334 tRRD = '10.0ns'
335
336 # Irrespective of density, tFAW is 50 ns
337 tXAW = '50ns'
338 activation_limit = 4
339
340# A single WideIO x128 interface (one command and address bus), with
341# default timings based on an estimated WIO-200 8 Gbit part.
342class WideIO_200_x128(DRAMCtrl):
343 # 1x128 configuration, 1 device with a 128-bit interface
344 device_bus_width = 128
345
346 # This is a BL4 device
347 burst_length = 4
348
349 # Each device has a page (row buffer) size of 4KB
350 # (this depends on the memory density)
351 device_rowbuffer_size = '4kB'
352
353 # 1x128 configuration, so 1 device
354 devices_per_rank = 1
355
356 # Use one rank for a one-high die stack
357 ranks_per_channel = 1
358
359 # WideIO has 4 banks in all configurations
360 banks_per_rank = 4
361
362 # WIO-200
363 tRCD = '18ns'
364 tCL = '18ns'
365 tRP = '18ns'
366 tRAS = '42ns'
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| 367 tWR = '15ns'
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361
362 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
363 # Note this is a BL4 SDR device.
364 tBURST = '20ns'
365
366 # WIO 8 Gb
367 tRFC = '210ns'
368
369 # WIO 8 Gb, <=85C, half for >85C
370 tREFI = '3.9us'
371
372 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
373 tWTR = '15ns'
374
375 # Default read-to-write bus around to 2 CK, @200 MHz = 10 ns
376 tRTW = '10ns'
377
378 # Activate to activate irrespective of density and speed grade
379 tRRD = '10.0ns'
380
381 # Two instead of four activation window
382 tXAW = '50ns'
383 activation_limit = 2
384
385# A single LPDDR3 x32 interface (one command/address bus), with
386# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32
387# configuration
388class LPDDR3_1600_x32(DRAMCtrl):
389 # 1x32 configuration, 1 device with a 32-bit interface
390 device_bus_width = 32
391
392 # LPDDR3 is a BL8 device
393 burst_length = 8
394
395 # Each device has a page (row buffer) size of 4KB
396 device_rowbuffer_size = '4kB'
397
398 # 1x32 configuration, so 1 device
399 devices_per_rank = 1
400
401 # Use a single rank
402 ranks_per_channel = 1
403
404 # LPDDR3 has 8 banks in all configurations
405 banks_per_rank = 8
406
407 # Fixed at 15 ns
408 tRCD = '15ns'
409
410 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
411 tCL = '15ns'
412
413 tRAS = '42ns'
| 368
369 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
370 # Note this is a BL4 SDR device.
371 tBURST = '20ns'
372
373 # WIO 8 Gb
374 tRFC = '210ns'
375
376 # WIO 8 Gb, <=85C, half for >85C
377 tREFI = '3.9us'
378
379 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
380 tWTR = '15ns'
381
382 # Default read-to-write bus around to 2 CK, @200 MHz = 10 ns
383 tRTW = '10ns'
384
385 # Activate to activate irrespective of density and speed grade
386 tRRD = '10.0ns'
387
388 # Two instead of four activation window
389 tXAW = '50ns'
390 activation_limit = 2
391
392# A single LPDDR3 x32 interface (one command/address bus), with
393# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32
394# configuration
395class LPDDR3_1600_x32(DRAMCtrl):
396 # 1x32 configuration, 1 device with a 32-bit interface
397 device_bus_width = 32
398
399 # LPDDR3 is a BL8 device
400 burst_length = 8
401
402 # Each device has a page (row buffer) size of 4KB
403 device_rowbuffer_size = '4kB'
404
405 # 1x32 configuration, so 1 device
406 devices_per_rank = 1
407
408 # Use a single rank
409 ranks_per_channel = 1
410
411 # LPDDR3 has 8 banks in all configurations
412 banks_per_rank = 8
413
414 # Fixed at 15 ns
415 tRCD = '15ns'
416
417 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
418 tCL = '15ns'
419
420 tRAS = '42ns'
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| 421 tWR = '15ns'
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414
415 # Pre-charge one bank 15 ns (all banks 18 ns)
416 tRP = '15ns'
417
418 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
419 # Note this is a BL8 DDR device.
420 # Requests larger than 32 bytes are broken down into multiple requests
421 # in the controller
422 tBURST = '5ns'
423
424 # LPDDR3, 4 Gb
425 tRFC = '130ns'
426 tREFI = '3.9us'
427
428 # Irrespective of speed grade, tWTR is 7.5 ns
429 tWTR = '7.5ns'
430
431 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
432 tRTW = '2.5ns'
433
434 # Activate to activate irrespective of density and speed grade
435 tRRD = '10.0ns'
436
437 # Irrespective of size, tFAW is 50 ns
438 tXAW = '50ns'
439 activation_limit = 4
| 422
423 # Pre-charge one bank 15 ns (all banks 18 ns)
424 tRP = '15ns'
425
426 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
427 # Note this is a BL8 DDR device.
428 # Requests larger than 32 bytes are broken down into multiple requests
429 # in the controller
430 tBURST = '5ns'
431
432 # LPDDR3, 4 Gb
433 tRFC = '130ns'
434 tREFI = '3.9us'
435
436 # Irrespective of speed grade, tWTR is 7.5 ns
437 tWTR = '7.5ns'
438
439 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
440 tRTW = '2.5ns'
441
442 # Activate to activate irrespective of density and speed grade
443 tRRD = '10.0ns'
444
445 # Irrespective of size, tFAW is 50 ns
446 tXAW = '50ns'
447 activation_limit = 4
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