DRAMCtrl.py (11679:4aa51b4a2f24) | DRAMCtrl.py (11837:17b37f38944a) |
---|---|
1# Copyright (c) 2012-2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 301 unchanged lines hidden (view full) --- 310 VDD = Param.Voltage("0V", "Main Voltage Range") 311 312 # Second voltage range defined by some DRAMs 313 VDD2 = Param.Voltage("0V", "2nd Voltage Range") 314 315# A single DDR3-1600 x64 channel (one command and address bus), with 316# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in 317# an 8x8 configuration. | 1# Copyright (c) 2012-2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 301 unchanged lines hidden (view full) --- 310 VDD = Param.Voltage("0V", "Main Voltage Range") 311 312 # Second voltage range defined by some DRAMs 313 VDD2 = Param.Voltage("0V", "2nd Voltage Range") 314 315# A single DDR3-1600 x64 channel (one command and address bus), with 316# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in 317# an 8x8 configuration. |
318class DDR3_1600_x64(DRAMCtrl): | 318class DDR3_1600_8x8(DRAMCtrl): |
319 # size of device in bytes 320 device_size = '512MB' 321 322 # 8x8 configuration, 8 devices each with an 8-bit interface 323 device_bus_width = 8 324 325 # DDR3 is a BL8 device 326 burst_length = 8 --- 78 unchanged lines hidden (view full) --- 405# device_size (DDR) => size of a single layer in a vault 406# ranks per channel (DDR) => number of layers 407# banks per rank (DDR) => banks per layer 408# devices per rank (DDR) => devices per layer ( 1 for HMC). 409# The parameters for which no input is available are inherited from the DDR3 410# configuration. 411# This configuration includes the latencies from the DRAM to the logic layer 412# of the HMC | 319 # size of device in bytes 320 device_size = '512MB' 321 322 # 8x8 configuration, 8 devices each with an 8-bit interface 323 device_bus_width = 8 324 325 # DDR3 is a BL8 device 326 burst_length = 8 --- 78 unchanged lines hidden (view full) --- 405# device_size (DDR) => size of a single layer in a vault 406# ranks per channel (DDR) => number of layers 407# banks per rank (DDR) => banks per layer 408# devices per rank (DDR) => devices per layer ( 1 for HMC). 409# The parameters for which no input is available are inherited from the DDR3 410# configuration. 411# This configuration includes the latencies from the DRAM to the logic layer 412# of the HMC |
413class HMC_2500_x32(DDR3_1600_x64): | 413class HMC_2500_1x32(DDR3_1600_8x8): |
414 # size of device 415 # two banks per device with each bank 4MB [2] 416 device_size = '8MB' 417 418 # 1x32 configuration, 1 device with 32 TSVs [2] 419 device_bus_width = 32 420 421 # HMC is a BL8 device [2] --- 65 unchanged lines hidden (view full) --- 487 # than a full DRAM channel controller 488 static_backend_latency='4ns' 489 static_frontend_latency='4ns' 490 491# A single DDR3-2133 x64 channel refining a selected subset of the 492# options for the DDR-1600 configuration, based on the same DDR3-1600 493# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 494# consistent across the two configurations. | 414 # size of device 415 # two banks per device with each bank 4MB [2] 416 device_size = '8MB' 417 418 # 1x32 configuration, 1 device with 32 TSVs [2] 419 device_bus_width = 32 420 421 # HMC is a BL8 device [2] --- 65 unchanged lines hidden (view full) --- 487 # than a full DRAM channel controller 488 static_backend_latency='4ns' 489 static_frontend_latency='4ns' 490 491# A single DDR3-2133 x64 channel refining a selected subset of the 492# options for the DDR-1600 configuration, based on the same DDR3-1600 493# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 494# consistent across the two configurations. |
495class DDR3_2133_x64(DDR3_1600_x64): | 495class DDR3_2133_8x8(DDR3_1600_8x8): |
496 # 1066 MHz 497 tCK = '0.938ns' 498 499 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz 500 tBURST = '3.752ns' 501 502 # DDR3-2133 14-14-14 503 tRCD = '13.09ns' --- 11 unchanged lines hidden (view full) --- 515 IDD4R = '191mA' 516 IDD5 = '250mA' 517 IDD3P1 = '44mA' 518 IDD2P1 = '43mA' 519 IDD6 ='20mA' 520 VDD = '1.5V' 521 522# A single DDR4-2400 x64 channel (one command and address bus), with | 496 # 1066 MHz 497 tCK = '0.938ns' 498 499 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz 500 tBURST = '3.752ns' 501 502 # DDR3-2133 14-14-14 503 tRCD = '13.09ns' --- 11 unchanged lines hidden (view full) --- 515 IDD4R = '191mA' 516 IDD5 = '250mA' 517 IDD3P1 = '44mA' 518 IDD2P1 = '43mA' 519 IDD6 ='20mA' 520 VDD = '1.5V' 521 522# A single DDR4-2400 x64 channel (one command and address bus), with |
523# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M16) 524# in an 4x16 configuration. 525class DDR4_2400_x64(DRAMCtrl): | 523# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4) 524# in an 16x4 configuration. 525# Total channel capacity is 32GB 526# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel 527class DDR4_2400_16x4(DRAMCtrl): |
526 # size of device | 528 # size of device |
527 device_size = '512MB' | 529 device_size = '1GB' |
528 | 530 |
529 # 4x16 configuration, 4 devices each with an 16-bit interface 530 device_bus_width = 16 | 531 # 16x4 configuration, 16 devices each with a 4-bit interface 532 device_bus_width = 4 |
531 532 # DDR4 is a BL8 device 533 burst_length = 8 534 | 533 534 # DDR4 is a BL8 device 535 burst_length = 8 536 |
535 # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16) 536 device_rowbuffer_size = '2kB' | 537 # Each device has a page (row buffer) size of 512 byte (1K columns x4) 538 device_rowbuffer_size = '512B' |
537 | 539 |
538 # 4x16 configuration, so 4 devices 539 devices_per_rank = 4 | 540 # 16x4 configuration, so 16 devices 541 devices_per_rank = 16 |
540 541 # Match our DDR3 configurations which is dual rank 542 ranks_per_channel = 2 543 544 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups | 542 543 # Match our DDR3 configurations which is dual rank 544 ranks_per_channel = 2 545 546 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups |
545 # Set to 2 for x16 case 546 bank_groups_per_rank = 2 | 547 # Set to 4 for x4 case 548 bank_groups_per_rank = 4 |
547 548 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all 549 # configurations). Currently we do not capture the additional 550 # constraints incurred by the bank groups | 549 550 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all 551 # configurations). Currently we do not capture the additional 552 # constraints incurred by the bank groups |
551 banks_per_rank = 8 | 553 banks_per_rank = 16 |
552 553 # override the default buffer sizes and go for something larger to 554 # accommodate the larger bank count 555 write_buffer_size = 128 556 read_buffer_size = 64 557 558 # 1200 MHz 559 tCK = '0.833ns' 560 561 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz 562 # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 563 # With bank group architectures, tBURST represents the CAS-to-CAS 564 # delay for bursts to different bank groups (tCCD_S) | 554 555 # override the default buffer sizes and go for something larger to 556 # accommodate the larger bank count 557 write_buffer_size = 128 558 read_buffer_size = 64 559 560 # 1200 MHz 561 tCK = '0.833ns' 562 563 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz 564 # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 565 # With bank group architectures, tBURST represents the CAS-to-CAS 566 # delay for bursts to different bank groups (tCCD_S) |
565 tBURST = '3.333ns' | 567 tBURST = '3.332ns' |
566 567 # @2400 data rate, tCCD_L is 6 CK 568 # CAS-to-CAS delay for bursts to the same bank group 569 # tBURST is equivalent to tCCD_S; no explicit parameter required 570 # for CAS-to-CAS delay for bursts to different bank groups 571 tCCD_L = '5ns'; 572 | 568 569 # @2400 data rate, tCCD_L is 6 CK 570 # CAS-to-CAS delay for bursts to the same bank group 571 # tBURST is equivalent to tCCD_S; no explicit parameter required 572 # for CAS-to-CAS delay for bursts to different bank groups 573 tCCD_L = '5ns'; 574 |
573 # DDR4-2400 16-16-16 574 tRCD = '13.32ns' 575 tCL = '13.32ns' 576 tRP = '13.32ns' 577 tRAS = '35ns' | 575 # DDR4-2400 17-17-17 576 tRCD = '14.16ns' 577 tCL = '14.16ns' 578 tRP = '14.16ns' 579 tRAS = '32ns' |
578 | 580 |
579 # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns) 580 tRRD = '5.3ns' | 581 # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns) 582 tRRD = '3.332ns' |
581 | 583 |
582 # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns) 583 tRRD_L = '6.4ns'; | 584 # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns) 585 tRRD_L = '4.9ns'; |
584 | 586 |
585 tXAW = '30ns' | 587 # tFAW for 512B page is MAX(16 CK, 13ns) 588 tXAW = '13.328ns' |
586 activation_limit = 4 | 589 activation_limit = 4 |
587 tRFC = '260ns' | 590 # tRFC is 350ns 591 tRFC = '350ns' |
588 589 tWR = '15ns' 590 591 # Here using the average of WTR_S and WTR_L 592 tWTR = '5ns' 593 594 # Greater of 4 CK or 7.5 ns 595 tRTP = '7.5ns' --- 6 unchanged lines hidden (view full) --- 602 603 # <=85C, half for >85C 604 tREFI = '7.8us' 605 606 # active powerdown and precharge powerdown exit time 607 tXP = '6ns' 608 609 # self refresh exit time | 592 593 tWR = '15ns' 594 595 # Here using the average of WTR_S and WTR_L 596 tWTR = '5ns' 597 598 # Greater of 4 CK or 7.5 ns 599 tRTP = '7.5ns' --- 6 unchanged lines hidden (view full) --- 606 607 # <=85C, half for >85C 608 tREFI = '7.8us' 609 610 # active powerdown and precharge powerdown exit time 611 tXP = '6ns' 612 613 # self refresh exit time |
610 tXS = '120ns' | 614 # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is: 615 # tRFC + 10ns = 340ns 616 tXS = '340ns' |
611 612 # Current values from datasheet | 617 618 # Current values from datasheet |
613 IDD0 = '70mA' 614 IDD02 = '4.6mA' 615 IDD2N = '50mA' 616 IDD3N = '67mA' | 619 IDD0 = '43mA' 620 IDD02 = '3mA' 621 IDD2N = '34mA' 622 IDD3N = '38mA' |
617 IDD3N2 = '3mA' | 623 IDD3N2 = '3mA' |
618 IDD4W = '302mA' 619 IDD4R = '230mA' 620 IDD5 = '192mA' 621 IDD3P1 = '44mA' 622 IDD2P1 = '32mA' 623 IDD6 = '20mA' | 624 IDD4W = '103mA' 625 IDD4R = '110mA' 626 IDD5 = '250mA' 627 IDD3P1 = '32mA' 628 IDD2P1 = '25mA' 629 IDD6 = '30mA' |
624 VDD = '1.2V' 625 VDD2 = '2.5V' 626 | 630 VDD = '1.2V' 631 VDD2 = '2.5V' 632 |
633# A single DDR4-2400 x64 channel (one command and address bus), with 634# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8) 635# in an 8x8 configuration. 636# Total channel capacity is 16GB 637# 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel 638class DDR4_2400_8x8(DDR4_2400_16x4): 639 # 8x8 configuration, 8 devices each with an 8-bit interface 640 device_bus_width = 8 641 642 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 643 device_rowbuffer_size = '1kB' 644 645 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns) 646 tRRD_L = '4.9ns'; 647 648 tXAW = '21ns' 649 650 # Current values from datasheet 651 IDD0 = '48mA' 652 IDD3N = '43mA' 653 IDD4W = '123mA' 654 IDD4R = '135mA' 655 IDD3P1 = '37mA' 656 657# A single DDR4-2400 x64 channel (one command and address bus), with 658# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16) 659# in an 4x16 configuration. 660# Total channel capacity is 4GB 661# 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel 662class DDR4_2400_4x16(DDR4_2400_16x4): 663 # 4x16 configuration, 4 devices each with an 16-bit interface 664 device_bus_width = 16 665 666 # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16) 667 device_rowbuffer_size = '2kB' 668 669 # 4x16 configuration, so 4 devices 670 devices_per_rank = 4 671 672 # Single rank for x16 673 ranks_per_channel = 1 674 675 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups 676 # Set to 2 for x16 case 677 bank_groups_per_rank = 2 678 679 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all 680 # configurations). Currently we do not capture the additional 681 # constraints incurred by the bank groups 682 banks_per_rank = 8 683 684 # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns) 685 tRRD = '5.3ns' 686 687 # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns) 688 tRRD_L = '6.4ns'; 689 690 tXAW = '30ns' 691 692 # Current values from datasheet 693 IDD0 = '80mA' 694 IDD02 = '4mA' 695 IDD2N = '34mA' 696 IDD3N = '47mA' 697 IDD4W = '228mA' 698 IDD4R = '243mA' 699 IDD5 = '280mA' 700 IDD3P1 = '41mA' 701 |
|
627# A single LPDDR2-S4 x32 interface (one command/address bus), with 628# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1) 629# in a 1x32 configuration. | 702# A single LPDDR2-S4 x32 interface (one command/address bus), with 703# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1) 704# in a 1x32 configuration. |
630class LPDDR2_S4_1066_x32(DRAMCtrl): | 705class LPDDR2_S4_1066_1x32(DRAMCtrl): |
631 # No DLL in LPDDR2 632 dll = False 633 634 # size of device 635 device_size = '512MB' 636 637 # 1x32 configuration, 1 device with a 32-bit interface 638 device_bus_width = 32 --- 82 unchanged lines hidden (view full) --- 721 IDD2P12 = '0.8mA' 722 IDD6 = '1mA' 723 IDD62 = '3.2mA' 724 VDD = '1.8V' 725 VDD2 = '1.2V' 726 727# A single WideIO x128 interface (one command and address bus), with 728# default timings based on an estimated WIO-200 8 Gbit part. | 706 # No DLL in LPDDR2 707 dll = False 708 709 # size of device 710 device_size = '512MB' 711 712 # 1x32 configuration, 1 device with a 32-bit interface 713 device_bus_width = 32 --- 82 unchanged lines hidden (view full) --- 796 IDD2P12 = '0.8mA' 797 IDD6 = '1mA' 798 IDD62 = '3.2mA' 799 VDD = '1.8V' 800 VDD2 = '1.2V' 801 802# A single WideIO x128 interface (one command and address bus), with 803# default timings based on an estimated WIO-200 8 Gbit part. |
729class WideIO_200_x128(DRAMCtrl): | 804class WideIO_200_1x128(DRAMCtrl): |
730 # No DLL for WideIO 731 dll = False 732 733 # size of device 734 device_size = '1024MB' 735 736 # 1x128 configuration, 1 device with a 128-bit interface 737 device_bus_width = 128 --- 52 unchanged lines hidden (view full) --- 790 tXAW = '50ns' 791 activation_limit = 2 792 793 # The WideIO specification does not provide current information 794 795# A single LPDDR3 x32 interface (one command/address bus), with 796# default timings based on a LPDDR3-1600 4 Gbit part (Micron 797# EDF8132A1MC) in a 1x32 configuration. | 805 # No DLL for WideIO 806 dll = False 807 808 # size of device 809 device_size = '1024MB' 810 811 # 1x128 configuration, 1 device with a 128-bit interface 812 device_bus_width = 128 --- 52 unchanged lines hidden (view full) --- 865 tXAW = '50ns' 866 activation_limit = 2 867 868 # The WideIO specification does not provide current information 869 870# A single LPDDR3 x32 interface (one command/address bus), with 871# default timings based on a LPDDR3-1600 4 Gbit part (Micron 872# EDF8132A1MC) in a 1x32 configuration. |
798class LPDDR3_1600_x32(DRAMCtrl): | 873class LPDDR3_1600_1x32(DRAMCtrl): |
799 # No DLL for LPDDR3 800 dll = False 801 802 # size of device 803 device_size = '512MB' 804 805 # 1x32 configuration, 1 device with a 32-bit interface 806 device_bus_width = 32 --- 83 unchanged lines hidden (view full) --- 890 IDD6 = '0.5mA' 891 IDD62 = '1.8mA' 892 VDD = '1.8V' 893 VDD2 = '1.2V' 894 895# A single GDDR5 x64 interface, with 896# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix 897# H5GQ1H24AFR) in a 2x32 configuration. | 874 # No DLL for LPDDR3 875 dll = False 876 877 # size of device 878 device_size = '512MB' 879 880 # 1x32 configuration, 1 device with a 32-bit interface 881 device_bus_width = 32 --- 83 unchanged lines hidden (view full) --- 965 IDD6 = '0.5mA' 966 IDD62 = '1.8mA' 967 VDD = '1.8V' 968 VDD2 = '1.2V' 969 970# A single GDDR5 x64 interface, with 971# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix 972# H5GQ1H24AFR) in a 2x32 configuration. |
898class GDDR5_4000_x64(DRAMCtrl): | 973class GDDR5_4000_2x32(DRAMCtrl): |
899 # size of device 900 device_size = '128MB' 901 902 # 2x32 configuration, 1 device with a 32-bit interface 903 device_bus_width = 32 904 905 # GDDR5 is a BL8 device 906 burst_length = 8 --- 67 unchanged lines hidden (view full) --- 974 tRTW = '2ns' 975 976# A single HBM x128 interface (one command and address bus), with 977# default timings based on data publically released 978# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014), 979# IDD measurement values, and by extrapolating data from other classes. 980# Architecture values based on published HBM spec 981# A 4H stack is defined, 2Gb per die for a total of 1GB of memory. | 974 # size of device 975 device_size = '128MB' 976 977 # 2x32 configuration, 1 device with a 32-bit interface 978 device_bus_width = 32 979 980 # GDDR5 is a BL8 device 981 burst_length = 8 --- 67 unchanged lines hidden (view full) --- 1049 tRTW = '2ns' 1050 1051# A single HBM x128 interface (one command and address bus), with 1052# default timings based on data publically released 1053# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014), 1054# IDD measurement values, and by extrapolating data from other classes. 1055# Architecture values based on published HBM spec 1056# A 4H stack is defined, 2Gb per die for a total of 1GB of memory. |
982class HBM_1000_4H_x128(DRAMCtrl): | 1057class HBM_1000_4H_1x128(DRAMCtrl): |
983 # HBM gen1 supports up to 8 128-bit physical channels 984 # Configuration defines a single channel, with the capacity 985 # set to (full_ stack_capacity / 8) based on 2Gb dies 986 # To use all 8 channels, set 'channels' parameter to 8 in 987 # system configuration 988 989 # 128-bit interface legacy mode 990 device_bus_width = 128 --- 72 unchanged lines hidden (view full) --- 1063 1064# A single HBM x64 interface (one command and address bus), with 1065# default timings based on HBM gen1 and data publically released 1066# A 4H stack is defined, 8Gb per die for a total of 4GB of memory. 1067# Note: This defines a pseudo-channel with a unique controller 1068# instantiated per pseudo-channel 1069# Stay at same IO rate (1Gbps) to maintain timing relationship with 1070# HBM gen1 class (HBM_1000_4H_x128) where possible | 1058 # HBM gen1 supports up to 8 128-bit physical channels 1059 # Configuration defines a single channel, with the capacity 1060 # set to (full_ stack_capacity / 8) based on 2Gb dies 1061 # To use all 8 channels, set 'channels' parameter to 8 in 1062 # system configuration 1063 1064 # 128-bit interface legacy mode 1065 device_bus_width = 128 --- 72 unchanged lines hidden (view full) --- 1138 1139# A single HBM x64 interface (one command and address bus), with 1140# default timings based on HBM gen1 and data publically released 1141# A 4H stack is defined, 8Gb per die for a total of 4GB of memory. 1142# Note: This defines a pseudo-channel with a unique controller 1143# instantiated per pseudo-channel 1144# Stay at same IO rate (1Gbps) to maintain timing relationship with 1145# HBM gen1 class (HBM_1000_4H_x128) where possible |
1071class HBM_1000_4H_x64(HBM_1000_4H_x128): | 1146class HBM_1000_4H_1x64(HBM_1000_4H_1x128): |
1072 # For HBM gen2 with pseudo-channel mode, configure 2X channels. 1073 # Configuration defines a single pseudo channel, with the capacity 1074 # set to (full_ stack_capacity / 16) based on 8Gb dies 1075 # To use all 16 pseudo channels, set 'channels' parameter to 16 in 1076 # system configuration 1077 1078 # 64-bit pseudo-channle interface 1079 device_bus_width = 64 --- 31 unchanged lines hidden --- | 1147 # For HBM gen2 with pseudo-channel mode, configure 2X channels. 1148 # Configuration defines a single pseudo channel, with the capacity 1149 # set to (full_ stack_capacity / 16) based on 8Gb dies 1150 # To use all 16 pseudo channels, set 'channels' parameter to 16 in 1151 # system configuration 1152 1153 # 64-bit pseudo-channle interface 1154 device_bus_width = 64 --- 31 unchanged lines hidden --- |