DRAMCtrl.py (11120:eef83ecab5bf) | DRAMCtrl.py (11186:2d1d51615e0e) |
---|---|
1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2013 Amin Farmahini-Farahani 14# Copyright (c) 2015 University of Kaiserslautern | 1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2013 Amin Farmahini-Farahani 14# Copyright (c) 2015 University of Kaiserslautern |
15# Copyright (c) 2015 The University of Bologna |
|
15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the --- 13 unchanged lines hidden (view full) --- 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Andreas Hansson 41# Ani Udipi 42# Omar Naji 43# Matthias Jung | 16# All rights reserved. 17# 18# Redistribution and use in source and binary forms, with or without 19# modification, are permitted provided that the following conditions are 20# met: redistributions of source code must retain the above copyright 21# notice, this list of conditions and the following disclaimer; 22# redistributions in binary form must reproduce the above copyright 23# notice, this list of conditions and the following disclaimer in the --- 13 unchanged lines hidden (view full) --- 37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40# 41# Authors: Andreas Hansson 42# Ani Udipi 43# Omar Naji 44# Matthias Jung |
45# Erfan Azarkhish |
|
44 45from m5.params import * 46from AbstractMemory import * 47 48# Enum for memory scheduling algorithms, currently First-Come 49# First-Served and a First-Row Hit then First-Come First-Served 50class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 51 --- 325 unchanged lines hidden (view full) --- 377 IDD5 = '220mA' 378 VDD = '1.5V' 379 380# A single HMC-2500 x32 model based on: 381# [1] DRAMSpec: a high-level DRAM bank modelling tool 382# developed at the University of Kaiserslautern. This high level tool 383# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to 384# estimate the DRAM bank latency and power numbers. | 46 47from m5.params import * 48from AbstractMemory import * 49 50# Enum for memory scheduling algorithms, currently First-Come 51# First-Served and a First-Row Hit then First-Come First-Served 52class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 53 --- 325 unchanged lines hidden (view full) --- 379 IDD5 = '220mA' 380 VDD = '1.5V' 381 382# A single HMC-2500 x32 model based on: 383# [1] DRAMSpec: a high-level DRAM bank modelling tool 384# developed at the University of Kaiserslautern. This high level tool 385# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to 386# estimate the DRAM bank latency and power numbers. |
385# [2] A Logic-base Interconnect for Supporting Near Memory Computation in the 386# Hybrid Memory Cube (E. Azarkhish et. al) | 387# [2] High performance AXI-4.0 based interconnect for extensible smart memory 388# cubes (E. Azarkhish et. al) |
387# Assumed for the HMC model is a 30 nm technology node. 388# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4 389# layers). 390# Each layer has 16 vaults and each vault consists of 2 banks per layer. 391# In order to be able to use the same controller used for 2D DRAM generations 392# for HMC, the following analogy is done: 393# Channel (DDR) => Vault (HMC) 394# device_size (DDR) => size of a single layer in a vault 395# ranks per channel (DDR) => number of layers 396# banks per rank (DDR) => banks per layer 397# devices per rank (DDR) => devices per layer ( 1 for HMC). 398# The parameters for which no input is available are inherited from the DDR3 399# configuration. | 389# Assumed for the HMC model is a 30 nm technology node. 390# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4 391# layers). 392# Each layer has 16 vaults and each vault consists of 2 banks per layer. 393# In order to be able to use the same controller used for 2D DRAM generations 394# for HMC, the following analogy is done: 395# Channel (DDR) => Vault (HMC) 396# device_size (DDR) => size of a single layer in a vault 397# ranks per channel (DDR) => number of layers 398# banks per rank (DDR) => banks per layer 399# devices per rank (DDR) => devices per layer ( 1 for HMC). 400# The parameters for which no input is available are inherited from the DDR3 401# configuration. |
400# This configuration includes the latencies from the DRAM to the logic layer of 401# the HMC | 402# This configuration includes the latencies from the DRAM to the logic layer 403# of the HMC |
402class HMC_2500_x32(DDR3_1600_x64): 403 # size of device 404 # two banks per device with each bank 4MB [2] 405 device_size = '8MB' 406 407 # 1x32 configuration, 1 device with 32 TSVs [2] 408 device_bus_width = 32 409 --- 26 unchanged lines hidden (view full) --- 436 tRP = '7.7ns' 437 tRAS = '21.6ns' 438 439 # tRRD depends on the power supply network for each vendor. 440 # We assume a tRRD of a double bank approach to be equal to 4 clock 441 # cycles (Assumption) 442 tRRD = '3.2ns' 443 | 404class HMC_2500_x32(DDR3_1600_x64): 405 # size of device 406 # two banks per device with each bank 4MB [2] 407 device_size = '8MB' 408 409 # 1x32 configuration, 1 device with 32 TSVs [2] 410 device_bus_width = 32 411 --- 26 unchanged lines hidden (view full) --- 438 tRP = '7.7ns' 439 tRAS = '21.6ns' 440 441 # tRRD depends on the power supply network for each vendor. 442 # We assume a tRRD of a double bank approach to be equal to 4 clock 443 # cycles (Assumption) 444 tRRD = '3.2ns' 445 |
444 # activation limit is set to 0 since there are only 2 banks per vault layer. | 446 # activation limit is set to 0 since there are only 2 banks per vault 447 # layer. |
445 activation_limit = 0 446 447 # Values using DRAMSpec HMC model [1] 448 tRFC = '59ns' 449 tWR = '8ns' 450 tRTP = '4.9ns' 451 | 448 activation_limit = 0 449 450 # Values using DRAMSpec HMC model [1] 451 tRFC = '59ns' 452 tWR = '8ns' 453 tRTP = '4.9ns' 454 |
452 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz = 0.8 453 # ns (Assumption) | 455 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz = 456 # 0.8 ns (Assumption) |
454 tCS = '0.8ns' 455 456 # Value using DRAMSpec HMC model [1] 457 tREFI = '3.9us' 458 | 457 tCS = '0.8ns' 458 459 # Value using DRAMSpec HMC model [1] 460 tREFI = '3.9us' 461 |
459 # Set default controller parameters 460 page_policy = 'close' 461 write_buffer_size = 8 462 read_buffer_size = 8 | 462 # The default page policy in the vault controllers is simple closed page 463 # [2] nevertheless 'close' policy opens and closes the row multiple times 464 # for bursts largers than 32Bytes. For this reason we use 'close_adaptive' 465 page_policy = 'close_adaptive' 466 467 # RoCoRaBaCh resembles the default address mapping in HMC |
463 addr_mapping = 'RoCoRaBaCh' 464 min_writes_per_switch = 8 465 | 468 addr_mapping = 'RoCoRaBaCh' 469 min_writes_per_switch = 8 470 |
471 # These parameters do not directly correlate with buffer_size in real 472 # hardware. Nevertheless, their value has been tuned to achieve a 473 # bandwidth similar to the cycle-accurate model in [2] 474 write_buffer_size = 32 475 read_buffer_size = 32 476 477 # The static latency of the vault controllers is estimated to be smaller 478 # than a full DRAM channel controller 479 static_backend_latency='4ns' 480 static_frontend_latency='4ns' 481 |
|
466# A single DDR3-2133 x64 channel refining a selected subset of the 467# options for the DDR-1600 configuration, based on the same DDR3-1600 468# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 469# consistent across the two configurations. 470class DDR3_2133_x64(DDR3_1600_x64): 471 # 1066 MHz 472 tCK = '0.938ns' 473 --- 570 unchanged lines hidden --- | 482# A single DDR3-2133 x64 channel refining a selected subset of the 483# options for the DDR-1600 configuration, based on the same DDR3-1600 484# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 485# consistent across the two configurations. 486class DDR3_2133_x64(DDR3_1600_x64): 487 # 1066 MHz 488 tCK = '0.938ns' 489 --- 570 unchanged lines hidden --- |