DRAMCtrl.py (10675:bb7cd7193edc) | DRAMCtrl.py (10864:83cec4049505) |
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1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2013 Amin Farmahini-Farahani | 1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2013 Amin Farmahini-Farahani |
14# Copyright (c) 2015 University of Kaiserslautern |
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14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the --- 11 unchanged lines hidden (view full) --- 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Andreas Hansson 40# Ani Udipi | 15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the --- 11 unchanged lines hidden (view full) --- 34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Andreas Hansson 41# Ani Udipi |
42# Omar Naji 43# Matthias Jung |
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41 42from m5.params import * 43from AbstractMemory import * 44 45# Enum for memory scheduling algorithms, currently First-Come 46# First-Served and a First-Row Hit then First-Come First-Served 47class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 48 --- 320 unchanged lines hidden (view full) --- 369 IDD0 = '75mA' 370 IDD2N = '50mA' 371 IDD3N = '57mA' 372 IDD4W = '165mA' 373 IDD4R = '187mA' 374 IDD5 = '220mA' 375 VDD = '1.5V' 376 | 44 45from m5.params import * 46from AbstractMemory import * 47 48# Enum for memory scheduling algorithms, currently First-Come 49# First-Served and a First-Row Hit then First-Come First-Served 50class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 51 --- 320 unchanged lines hidden (view full) --- 372 IDD0 = '75mA' 373 IDD2N = '50mA' 374 IDD3N = '57mA' 375 IDD4W = '165mA' 376 IDD4R = '187mA' 377 IDD5 = '220mA' 378 VDD = '1.5V' 379 |
380# A single HMC-2500 x32 model based on: 381# [1] DRAMSpec: a high-level DRAM bank modelling tool 382# developed at the University of Kaiserslautern. This high level tool 383# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to 384# estimate the DRAM bank latency and power numbers. 385# [2] A Logic-base Interconnect for Supporting Near Memory Computation in the 386# Hybrid Memory Cube (E. Azarkhish et. al) 387# Assumed for the HMC model is a 30 nm technology node. 388# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4 389# layers). 390# Each layer has 16 vaults and each vault consists of 2 banks per layer. 391# In order to be able to use the same controller used for 2D DRAM generations 392# for HMC, the following analogy is done: 393# Channel (DDR) => Vault (HMC) 394# device_size (DDR) => size of a single layer in a vault 395# ranks per channel (DDR) => number of layers 396# banks per rank (DDR) => banks per layer 397# devices per rank (DDR) => devices per layer ( 1 for HMC). 398# The parameters for which no input is available are inherited from the DDR3 399# configuration. 400# This configuration includes the latencies from the DRAM to the logic layer of 401# the HMC 402class HMC_2500_x32(DDR3_1600_x64): 403 # size of device 404 # two banks per device with each bank 4MB [2] 405 device_size = '8MB' 406 407 # 1x32 configuration, 1 device with 32 TSVs [2] 408 device_bus_width = 32 409 410 # HMC is a BL8 device [2] 411 burst_length = 8 412 413 # Each device has a page (row buffer) size of 256 bytes [2] 414 device_rowbuffer_size = '256B' 415 416 # 1x32 configuration, so 1 device [2] 417 devices_per_rank = 1 418 419 # 4 layers so 4 ranks [2] 420 ranks_per_channel = 4 421 422 # HMC has 2 banks per layer [2] 423 # Each layer represents a rank. With 4 layers and 8 banks in total, each 424 # layer has 2 banks; thus 2 banks per rank. 425 banks_per_rank = 2 426 427 # 1250 MHz [2] 428 tCK = '0.8ns' 429 430 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz 431 tBURST = '3.2ns' 432 433 # Values using DRAMSpec HMC model [1] 434 tRCD = '10.2ns' 435 tCL = '9.9ns' 436 tRP = '7.7ns' 437 tRAS = '21.6ns' 438 439 # tRRD depends on the power supply network for each vendor. 440 # We assume a tRRD of a double bank approach to be equal to 4 clock 441 # cycles (Assumption) 442 tRRD = '3.2ns' 443 444 # activation limit is set to 0 since there are only 2 banks per vault layer. 445 activation_limit = 0 446 447 # Values using DRAMSpec HMC model [1] 448 tRFC = '59ns' 449 tWR = '8ns' 450 tRTP = '4.9ns' 451 452 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz = 0.8 453 # ns (Assumption) 454 tCS = '0.8ns' 455 456 # Value using DRAMSpec HMC model [1] 457 tREFI = '3.9us' 458 459 # Set default controller parameters 460 page_policy = 'close' 461 write_buffer_size = 8 462 read_buffer_size = 8 463 addr_mapping = 'RoCoRaBaCh' 464 min_writes_per_switch = 8 465 |
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377# A single DDR3-2133 x64 channel refining a selected subset of the 378# options for the DDR-1600 configuration, based on the same DDR3-1600 379# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 380# consistent across the two configurations. 381class DDR3_2133_x64(DDR3_1600_x64): 382 # 1066 MHz 383 tCK = '0.938ns' 384 --- 439 unchanged lines hidden --- | 466# A single DDR3-2133 x64 channel refining a selected subset of the 467# options for the DDR-1600 configuration, based on the same DDR3-1600 468# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 469# consistent across the two configurations. 470class DDR3_2133_x64(DDR3_1600_x64): 471 # 1066 MHz 472 tCK = '0.938ns' 473 --- 439 unchanged lines hidden --- |