1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2013 Amin Farmahini-Farahani
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Andreas Hansson
40# Ani Udipi
41
42from m5.params import *
43from AbstractMemory import *
44
45# Enum for memory scheduling algorithms, currently First-Come
46# First-Served and a First-Row Hit then First-Come First-Served
47class MemSched(Enum): vals = ['fcfs', 'frfcfs']
48
49# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
50# channel, rank, bank, row and column, respectively, and going from
51# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
52# suitable for an open-page policy, optimising for sequential accesses
53# hitting in the open row. For a closed-page policy, RoCoRaBaCh
54# maximises parallelism.
55class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
56
57# Enum for the page policy, either open, open_adaptive, close, or
58# close_adaptive.
59class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
60 'close_adaptive']
61
62# DRAMCtrl is a single-channel single-ported DRAM controller model
63# that aims to model the most important system-level performance
64# effects of a DRAM without getting into too much detail of the DRAM
65# itself.
66class DRAMCtrl(AbstractMemory):
67 type = 'DRAMCtrl'
68 cxx_header = "mem/dram_ctrl.hh"
69
70 # single-ported on the system interface side, instantiate with a
71 # bus in front of the controller for multiple ports
72 port = SlavePort("Slave port")
73
74 # the basic configuration of the controller architecture
75 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
76 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
77
78 # threshold in percent for when to forcefully trigger writes and
79 # start emptying the write buffer
80 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
81
82 # threshold in percentage for when to start writes if the read
83 # queue is empty
84 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
85
86 # minimum write bursts to schedule before switching back to reads
87 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
88 "switching to reads")
89
90 # scheduler, address map and page policy
91 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
92 addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy")
93 page_policy = Param.PageManage('open_adaptive', "Page management policy")
94
95 # enforce a limit on the number of accesses per row
96 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
97 "closing");
98
99 # pipeline latency of the controller and PHY, split into a
100 # frontend part and a backend part, with reads and writes serviced
101 # by the queues only seeing the frontend contribution, and reads
102 # serviced by the memory seeing the sum of the two
103 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
104 static_backend_latency = Param.Latency("10ns", "Static backend latency")
105
106 # the physical organisation of the DRAM
107 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
108 "device/chip")
109 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
110 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
111 "device/chip")
112 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
113 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
114 banks_per_rank = Param.Unsigned("Number of banks per rank")
115 # only used for the address mapping as the controller by
116 # construction is a single channel and multiple controllers have
117 # to be instantiated for a multi-channel configuration
118 channels = Param.Unsigned(1, "Number of channels")
119
120 # timing behaviour and constraints - all in nanoseconds
121
122 # the base clock period of the DRAM
123 tCK = Param.Latency("Clock period")
124
125 # the amount of time in nanoseconds from issuing an activate command
126 # to the data being available in the row buffer for a read/write
127 tRCD = Param.Latency("RAS to CAS delay")
128
129 # the time from issuing a read/write command to seeing the actual data
130 tCL = Param.Latency("CAS latency")
131
132 # minimum time between a precharge and subsequent activate
133 tRP = Param.Latency("Row precharge time")
134
135 # minimum time between an activate and a precharge to the same row
136 tRAS = Param.Latency("ACT to PRE delay")
137
138 # minimum time between a write data transfer and a precharge
139 tWR = Param.Latency("Write recovery time")
140
141 # minimum time between a read and precharge command
142 tRTP = Param.Latency("Read to precharge")
143
144 # time to complete a burst transfer, typically the burst length
145 # divided by two due to the DDR bus, but by making it a parameter
146 # it is easier to also evaluate SDR memories like WideIO.
147 # This parameter has to account for burst length.
148 # Read/Write requests with data size larger than one full burst are broken
149 # down into multiple requests in the controller
150 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
151
152 # time taken to complete one refresh cycle (N rows in all banks)
153 tRFC = Param.Latency("Refresh cycle time")
154
155 # refresh command interval, how often a "ref" command needs
156 # to be sent. It is 7.8 us for a 64ms refresh requirement
157 tREFI = Param.Latency("Refresh command interval")
158
159 # write-to-read turn around penalty
160 tWTR = Param.Latency("Write to read switching time")
161
162 # read-to-write turn around penalty, bus turnaround delay
163 tRTW = Param.Latency("Read to write switching time")
164
165 # minimum row activate to row activate delay time
166 tRRD = Param.Latency("ACT to ACT delay")
167
168 # time window in which a maximum number of activates are allowed
169 # to take place, set to 0 to disable
170 tXAW = Param.Latency("X activation window")
171 activation_limit = Param.Unsigned("Max number of activates in window")
172
173 # Currently rolled into other params
174 ######################################################################
175
176 # tRC - assumed to be tRAS + tRP
177
178# A single DDR3 x64 interface (one command and address bus), with
179# default timings based on DDR3-1600 4 Gbit parts in an 8x8
180# configuration, which would amount to 4 Gbyte of memory.
181class DDR3_1600_x64(DRAMCtrl):
182 # 8x8 configuration, 8 devices each with an 8-bit interface
183 device_bus_width = 8
184
185 # DDR3 is a BL8 device
186 burst_length = 8
187
188 # Each device has a page (row buffer) size of 1KB
189 # (this depends on the memory density)
190 device_rowbuffer_size = '1kB'
191
192 # 8x8 configuration, so 8 devices
193 devices_per_rank = 8
194
195 # Use two ranks
196 ranks_per_channel = 2
197
198 # DDR3 has 8 banks in all configurations
199 banks_per_rank = 8
200
201 # 800 MHz
202 tCK = '1.25ns'
203
204 # DDR3-1600 11-11-11-28
205 tRCD = '13.75ns'
206 tCL = '13.75ns'
207 tRP = '13.75ns'
208 tRAS = '35ns'
209 tWR = '15ns'
210 tRTP = '7.5ns'
211
212 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz.
213 # Note this is a BL8 DDR device.
214 tBURST = '5ns'
215
216 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns
217 tRFC = '300ns'
218
219 # DDR3, <=85C, half for >85C
220 tREFI = '7.8us'
221
222 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
223 tWTR = '7.5ns'
224
225 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
226 tRTW = '2.5ns'
227
228 # Assume 5 CK for activate to activate for different banks
229 tRRD = '6.25ns'
230
231 # With a 2kbyte page size, DDR3-1600 lands around 40 ns
232 tXAW = '40ns'
233 activation_limit = 4
234
235
236# A single DDR3 x64 interface (one command and address bus), with
237# default timings based on DDR3-1333 4 Gbit parts in an 8x8
238# configuration, which would amount to 4 GByte of memory. This
239# configuration is primarily for comparing with DRAMSim2, and all the
240# parameters except ranks_per_channel are based on the DRAMSim2 config
241# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has
242# to be manually set, depending on size of the memory to be
243# simulated. By default DRAMSim2 has 2048MB of memory with a single
244# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2
245class DDR3_1333_x64_DRAMSim2(DRAMCtrl):
246 # 8x8 configuration, 8 devices each with an 8-bit interface
247 device_bus_width = 8
248
249 # DDR3 is a BL8 device
250 burst_length = 8
251
252 # Each device has a page (row buffer) size of 1KB
253 # (this depends on the memory density)
254 device_rowbuffer_size = '1kB'
255
256 # 8x8 configuration, so 8 devices
257 devices_per_rank = 8
258
259 # Use two ranks
260 ranks_per_channel = 2
261
262 # DDR3 has 8 banks in all configurations
263 banks_per_rank = 8
264
265 # 666 MHs
266 tCK = '1.5ns'
267
268 tRCD = '15ns'
269 tCL = '15ns'
270 tRP = '15ns'
271 tRAS = '36ns'
272 tWR = '15ns'
273 tRTP = '7.5ns'
274
275 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz.
276 # Note this is a BL8 DDR device.
277 tBURST = '6ns'
278
279 tRFC = '160ns'
280
281 # DDR3, <=85C, half for >85C
282 tREFI = '7.8us'
283
284 # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns
285 tWTR = '7.5ns'
286
287 # Default read-to-write bus around to 2 CK, @666.66 MHz = 3 ns
288 tRTW = '3ns'
289
290 tRRD = '6.0ns'
291
292 tXAW = '30ns'
293 activation_limit = 4
294
295
296# A single LPDDR2-S4 x32 interface (one command/address bus), with
297# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32
298# configuration.
299class LPDDR2_S4_1066_x32(DRAMCtrl):
300 # 1x32 configuration, 1 device with a 32-bit interface
301 device_bus_width = 32
302
303 # LPDDR2_S4 is a BL4 and BL8 device
304 burst_length = 8
305
306 # Each device has a page (row buffer) size of 1KB
307 # (this depends on the memory density)
308 device_rowbuffer_size = '1kB'
309
310 # 1x32 configuration, so 1 device
311 devices_per_rank = 1
312
313 # Use a single rank
314 ranks_per_channel = 1
315
316 # LPDDR2-S4 has 8 banks in all configurations
317 banks_per_rank = 8
318
319 # 533 MHz
320 tCK = '1.876ns'
321
322 # Fixed at 15 ns
323 tRCD = '15ns'
324
325 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
326 tCL = '15ns'
327
328 # Pre-charge one bank 15 ns (all banks 18 ns)
329 tRP = '15ns'
330
331 tRAS = '42ns'
332 tWR = '15ns'
333
334 # 6 CK read to precharge delay
335 tRTP = '11.256ns'
336
337 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
338 # Note this is a BL8 DDR device.
339 # Requests larger than 32 bytes are broken down into multiple requests
340 # in the controller
341 tBURST = '7.5ns'
342
343 # LPDDR2-S4, 4 Gbit
344 tRFC = '130ns'
345 tREFI = '3.9us'
346
347 # Irrespective of speed grade, tWTR is 7.5 ns
348 tWTR = '7.5ns'
349
350 # Default read-to-write bus around to 2 CK, @533 MHz = 3.75 ns
351 tRTW = '3.75ns'
352
353 # Activate to activate irrespective of density and speed grade
354 tRRD = '10.0ns'
355
356 # Irrespective of density, tFAW is 50 ns
357 tXAW = '50ns'
358 activation_limit = 4
359
360# A single WideIO x128 interface (one command and address bus), with
361# default timings based on an estimated WIO-200 8 Gbit part.
362class WideIO_200_x128(DRAMCtrl):
363 # 1x128 configuration, 1 device with a 128-bit interface
364 device_bus_width = 128
365
366 # This is a BL4 device
367 burst_length = 4
368
369 # Each device has a page (row buffer) size of 4KB
370 # (this depends on the memory density)
371 device_rowbuffer_size = '4kB'
372
373 # 1x128 configuration, so 1 device
374 devices_per_rank = 1
375
376 # Use one rank for a one-high die stack
377 ranks_per_channel = 1
378
379 # WideIO has 4 banks in all configurations
380 banks_per_rank = 4
381
382 # 200 MHz
383 tCK = '5ns'
384
385 # WIO-200
386 tRCD = '18ns'
387 tCL = '18ns'
388 tRP = '18ns'
389 tRAS = '42ns'
390 tWR = '15ns'
391 # Read to precharge is same as the burst
392 tRTP = '20ns'
393
394 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
395 # Note this is a BL4 SDR device.
396 tBURST = '20ns'
397
398 # WIO 8 Gb
399 tRFC = '210ns'
400
401 # WIO 8 Gb, <=85C, half for >85C
402 tREFI = '3.9us'
403
404 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
405 tWTR = '15ns'
406
407 # Default read-to-write bus around to 2 CK, @200 MHz = 10 ns
408 tRTW = '10ns'
409
410 # Activate to activate irrespective of density and speed grade
411 tRRD = '10.0ns'
412
413 # Two instead of four activation window
414 tXAW = '50ns'
415 activation_limit = 2
416
417# A single LPDDR3 x32 interface (one command/address bus), with
418# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32
419# configuration
420class LPDDR3_1600_x32(DRAMCtrl):
421 # 1x32 configuration, 1 device with a 32-bit interface
422 device_bus_width = 32
423
424 # LPDDR3 is a BL8 device
425 burst_length = 8
426
427 # Each device has a page (row buffer) size of 4KB
428 device_rowbuffer_size = '4kB'
429
430 # 1x32 configuration, so 1 device
431 devices_per_rank = 1
432
433 # Use a single rank
434 ranks_per_channel = 1
435
436 # LPDDR3 has 8 banks in all configurations
437 banks_per_rank = 8
438
439 # 800 MHz
440 tCK = '1.25ns'
441
442 # Fixed at 15 ns
443 tRCD = '15ns'
444
445 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
446 tCL = '15ns'
447
448 tRAS = '42ns'
449 tWR = '15ns'
450
451 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
452 tRTP = '7.5ns'
453
454 # Pre-charge one bank 15 ns (all banks 18 ns)
455 tRP = '15ns'
456
457 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
458 # Note this is a BL8 DDR device.
459 # Requests larger than 32 bytes are broken down into multiple requests
460 # in the controller
461 tBURST = '5ns'
462
463 # LPDDR3, 4 Gb
464 tRFC = '130ns'
465 tREFI = '3.9us'
466
467 # Irrespective of speed grade, tWTR is 7.5 ns
468 tWTR = '7.5ns'
469
470 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
471 tRTW = '2.5ns'
472
473 # Activate to activate irrespective of density and speed grade
474 tRRD = '10.0ns'
475
476 # Irrespective of size, tFAW is 50 ns
477 tXAW = '50ns'
478 activation_limit = 4
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2013 Amin Farmahini-Farahani
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Andreas Hansson
40# Ani Udipi
41
42from m5.params import *
43from AbstractMemory import *
44
45# Enum for memory scheduling algorithms, currently First-Come
46# First-Served and a First-Row Hit then First-Come First-Served
47class MemSched(Enum): vals = ['fcfs', 'frfcfs']
48
49# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
50# channel, rank, bank, row and column, respectively, and going from
51# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
52# suitable for an open-page policy, optimising for sequential accesses
53# hitting in the open row. For a closed-page policy, RoCoRaBaCh
54# maximises parallelism.
55class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
56
57# Enum for the page policy, either open, open_adaptive, close, or
58# close_adaptive.
59class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
60 'close_adaptive']
61
62# DRAMCtrl is a single-channel single-ported DRAM controller model
63# that aims to model the most important system-level performance
64# effects of a DRAM without getting into too much detail of the DRAM
65# itself.
66class DRAMCtrl(AbstractMemory):
67 type = 'DRAMCtrl'
68 cxx_header = "mem/dram_ctrl.hh"
69
70 # single-ported on the system interface side, instantiate with a
71 # bus in front of the controller for multiple ports
72 port = SlavePort("Slave port")
73
74 # the basic configuration of the controller architecture
75 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
76 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
77
78 # threshold in percent for when to forcefully trigger writes and
79 # start emptying the write buffer
80 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
81
82 # threshold in percentage for when to start writes if the read
83 # queue is empty
84 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
85
86 # minimum write bursts to schedule before switching back to reads
87 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
88 "switching to reads")
89
90 # scheduler, address map and page policy
91 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
92 addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy")
93 page_policy = Param.PageManage('open_adaptive', "Page management policy")
94
95 # enforce a limit on the number of accesses per row
96 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
97 "closing");
98
99 # pipeline latency of the controller and PHY, split into a
100 # frontend part and a backend part, with reads and writes serviced
101 # by the queues only seeing the frontend contribution, and reads
102 # serviced by the memory seeing the sum of the two
103 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
104 static_backend_latency = Param.Latency("10ns", "Static backend latency")
105
106 # the physical organisation of the DRAM
107 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
108 "device/chip")
109 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
110 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
111 "device/chip")
112 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
113 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
114 banks_per_rank = Param.Unsigned("Number of banks per rank")
115 # only used for the address mapping as the controller by
116 # construction is a single channel and multiple controllers have
117 # to be instantiated for a multi-channel configuration
118 channels = Param.Unsigned(1, "Number of channels")
119
120 # timing behaviour and constraints - all in nanoseconds
121
122 # the base clock period of the DRAM
123 tCK = Param.Latency("Clock period")
124
125 # the amount of time in nanoseconds from issuing an activate command
126 # to the data being available in the row buffer for a read/write
127 tRCD = Param.Latency("RAS to CAS delay")
128
129 # the time from issuing a read/write command to seeing the actual data
130 tCL = Param.Latency("CAS latency")
131
132 # minimum time between a precharge and subsequent activate
133 tRP = Param.Latency("Row precharge time")
134
135 # minimum time between an activate and a precharge to the same row
136 tRAS = Param.Latency("ACT to PRE delay")
137
138 # minimum time between a write data transfer and a precharge
139 tWR = Param.Latency("Write recovery time")
140
141 # minimum time between a read and precharge command
142 tRTP = Param.Latency("Read to precharge")
143
144 # time to complete a burst transfer, typically the burst length
145 # divided by two due to the DDR bus, but by making it a parameter
146 # it is easier to also evaluate SDR memories like WideIO.
147 # This parameter has to account for burst length.
148 # Read/Write requests with data size larger than one full burst are broken
149 # down into multiple requests in the controller
150 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
151
152 # time taken to complete one refresh cycle (N rows in all banks)
153 tRFC = Param.Latency("Refresh cycle time")
154
155 # refresh command interval, how often a "ref" command needs
156 # to be sent. It is 7.8 us for a 64ms refresh requirement
157 tREFI = Param.Latency("Refresh command interval")
158
159 # write-to-read turn around penalty
160 tWTR = Param.Latency("Write to read switching time")
161
162 # read-to-write turn around penalty, bus turnaround delay
163 tRTW = Param.Latency("Read to write switching time")
164
165 # minimum row activate to row activate delay time
166 tRRD = Param.Latency("ACT to ACT delay")
167
168 # time window in which a maximum number of activates are allowed
169 # to take place, set to 0 to disable
170 tXAW = Param.Latency("X activation window")
171 activation_limit = Param.Unsigned("Max number of activates in window")
172
173 # Currently rolled into other params
174 ######################################################################
175
176 # tRC - assumed to be tRAS + tRP
177
178# A single DDR3 x64 interface (one command and address bus), with
179# default timings based on DDR3-1600 4 Gbit parts in an 8x8
180# configuration, which would amount to 4 Gbyte of memory.
181class DDR3_1600_x64(DRAMCtrl):
182 # 8x8 configuration, 8 devices each with an 8-bit interface
183 device_bus_width = 8
184
185 # DDR3 is a BL8 device
186 burst_length = 8
187
188 # Each device has a page (row buffer) size of 1KB
189 # (this depends on the memory density)
190 device_rowbuffer_size = '1kB'
191
192 # 8x8 configuration, so 8 devices
193 devices_per_rank = 8
194
195 # Use two ranks
196 ranks_per_channel = 2
197
198 # DDR3 has 8 banks in all configurations
199 banks_per_rank = 8
200
201 # 800 MHz
202 tCK = '1.25ns'
203
204 # DDR3-1600 11-11-11-28
205 tRCD = '13.75ns'
206 tCL = '13.75ns'
207 tRP = '13.75ns'
208 tRAS = '35ns'
209 tWR = '15ns'
210 tRTP = '7.5ns'
211
212 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz.
213 # Note this is a BL8 DDR device.
214 tBURST = '5ns'
215
216 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns
217 tRFC = '300ns'
218
219 # DDR3, <=85C, half for >85C
220 tREFI = '7.8us'
221
222 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
223 tWTR = '7.5ns'
224
225 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
226 tRTW = '2.5ns'
227
228 # Assume 5 CK for activate to activate for different banks
229 tRRD = '6.25ns'
230
231 # With a 2kbyte page size, DDR3-1600 lands around 40 ns
232 tXAW = '40ns'
233 activation_limit = 4
234
235
236# A single DDR3 x64 interface (one command and address bus), with
237# default timings based on DDR3-1333 4 Gbit parts in an 8x8
238# configuration, which would amount to 4 GByte of memory. This
239# configuration is primarily for comparing with DRAMSim2, and all the
240# parameters except ranks_per_channel are based on the DRAMSim2 config
241# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has
242# to be manually set, depending on size of the memory to be
243# simulated. By default DRAMSim2 has 2048MB of memory with a single
244# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2
245class DDR3_1333_x64_DRAMSim2(DRAMCtrl):
246 # 8x8 configuration, 8 devices each with an 8-bit interface
247 device_bus_width = 8
248
249 # DDR3 is a BL8 device
250 burst_length = 8
251
252 # Each device has a page (row buffer) size of 1KB
253 # (this depends on the memory density)
254 device_rowbuffer_size = '1kB'
255
256 # 8x8 configuration, so 8 devices
257 devices_per_rank = 8
258
259 # Use two ranks
260 ranks_per_channel = 2
261
262 # DDR3 has 8 banks in all configurations
263 banks_per_rank = 8
264
265 # 666 MHs
266 tCK = '1.5ns'
267
268 tRCD = '15ns'
269 tCL = '15ns'
270 tRP = '15ns'
271 tRAS = '36ns'
272 tWR = '15ns'
273 tRTP = '7.5ns'
274
275 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz.
276 # Note this is a BL8 DDR device.
277 tBURST = '6ns'
278
279 tRFC = '160ns'
280
281 # DDR3, <=85C, half for >85C
282 tREFI = '7.8us'
283
284 # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns
285 tWTR = '7.5ns'
286
287 # Default read-to-write bus around to 2 CK, @666.66 MHz = 3 ns
288 tRTW = '3ns'
289
290 tRRD = '6.0ns'
291
292 tXAW = '30ns'
293 activation_limit = 4
294
295
296# A single LPDDR2-S4 x32 interface (one command/address bus), with
297# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32
298# configuration.
299class LPDDR2_S4_1066_x32(DRAMCtrl):
300 # 1x32 configuration, 1 device with a 32-bit interface
301 device_bus_width = 32
302
303 # LPDDR2_S4 is a BL4 and BL8 device
304 burst_length = 8
305
306 # Each device has a page (row buffer) size of 1KB
307 # (this depends on the memory density)
308 device_rowbuffer_size = '1kB'
309
310 # 1x32 configuration, so 1 device
311 devices_per_rank = 1
312
313 # Use a single rank
314 ranks_per_channel = 1
315
316 # LPDDR2-S4 has 8 banks in all configurations
317 banks_per_rank = 8
318
319 # 533 MHz
320 tCK = '1.876ns'
321
322 # Fixed at 15 ns
323 tRCD = '15ns'
324
325 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
326 tCL = '15ns'
327
328 # Pre-charge one bank 15 ns (all banks 18 ns)
329 tRP = '15ns'
330
331 tRAS = '42ns'
332 tWR = '15ns'
333
334 # 6 CK read to precharge delay
335 tRTP = '11.256ns'
336
337 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
338 # Note this is a BL8 DDR device.
339 # Requests larger than 32 bytes are broken down into multiple requests
340 # in the controller
341 tBURST = '7.5ns'
342
343 # LPDDR2-S4, 4 Gbit
344 tRFC = '130ns'
345 tREFI = '3.9us'
346
347 # Irrespective of speed grade, tWTR is 7.5 ns
348 tWTR = '7.5ns'
349
350 # Default read-to-write bus around to 2 CK, @533 MHz = 3.75 ns
351 tRTW = '3.75ns'
352
353 # Activate to activate irrespective of density and speed grade
354 tRRD = '10.0ns'
355
356 # Irrespective of density, tFAW is 50 ns
357 tXAW = '50ns'
358 activation_limit = 4
359
360# A single WideIO x128 interface (one command and address bus), with
361# default timings based on an estimated WIO-200 8 Gbit part.
362class WideIO_200_x128(DRAMCtrl):
363 # 1x128 configuration, 1 device with a 128-bit interface
364 device_bus_width = 128
365
366 # This is a BL4 device
367 burst_length = 4
368
369 # Each device has a page (row buffer) size of 4KB
370 # (this depends on the memory density)
371 device_rowbuffer_size = '4kB'
372
373 # 1x128 configuration, so 1 device
374 devices_per_rank = 1
375
376 # Use one rank for a one-high die stack
377 ranks_per_channel = 1
378
379 # WideIO has 4 banks in all configurations
380 banks_per_rank = 4
381
382 # 200 MHz
383 tCK = '5ns'
384
385 # WIO-200
386 tRCD = '18ns'
387 tCL = '18ns'
388 tRP = '18ns'
389 tRAS = '42ns'
390 tWR = '15ns'
391 # Read to precharge is same as the burst
392 tRTP = '20ns'
393
394 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
395 # Note this is a BL4 SDR device.
396 tBURST = '20ns'
397
398 # WIO 8 Gb
399 tRFC = '210ns'
400
401 # WIO 8 Gb, <=85C, half for >85C
402 tREFI = '3.9us'
403
404 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
405 tWTR = '15ns'
406
407 # Default read-to-write bus around to 2 CK, @200 MHz = 10 ns
408 tRTW = '10ns'
409
410 # Activate to activate irrespective of density and speed grade
411 tRRD = '10.0ns'
412
413 # Two instead of four activation window
414 tXAW = '50ns'
415 activation_limit = 2
416
417# A single LPDDR3 x32 interface (one command/address bus), with
418# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32
419# configuration
420class LPDDR3_1600_x32(DRAMCtrl):
421 # 1x32 configuration, 1 device with a 32-bit interface
422 device_bus_width = 32
423
424 # LPDDR3 is a BL8 device
425 burst_length = 8
426
427 # Each device has a page (row buffer) size of 4KB
428 device_rowbuffer_size = '4kB'
429
430 # 1x32 configuration, so 1 device
431 devices_per_rank = 1
432
433 # Use a single rank
434 ranks_per_channel = 1
435
436 # LPDDR3 has 8 banks in all configurations
437 banks_per_rank = 8
438
439 # 800 MHz
440 tCK = '1.25ns'
441
442 # Fixed at 15 ns
443 tRCD = '15ns'
444
445 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
446 tCL = '15ns'
447
448 tRAS = '42ns'
449 tWR = '15ns'
450
451 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
452 tRTP = '7.5ns'
453
454 # Pre-charge one bank 15 ns (all banks 18 ns)
455 tRP = '15ns'
456
457 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
458 # Note this is a BL8 DDR device.
459 # Requests larger than 32 bytes are broken down into multiple requests
460 # in the controller
461 tBURST = '5ns'
462
463 # LPDDR3, 4 Gb
464 tRFC = '130ns'
465 tREFI = '3.9us'
466
467 # Irrespective of speed grade, tWTR is 7.5 ns
468 tWTR = '7.5ns'
469
470 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
471 tRTW = '2.5ns'
472
473 # Activate to activate irrespective of density and speed grade
474 tRRD = '10.0ns'
475
476 # Irrespective of size, tFAW is 50 ns
477 tXAW = '50ns'
478 activation_limit = 4