1# Copyright (c) 2012-2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
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310 VDD = Param.Voltage("0V", "Main Voltage Range")
311
312 # Second voltage range defined by some DRAMs
313 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
314
315# A single DDR3-1600 x64 channel (one command and address bus), with
316# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
317# an 8x8 configuration.
318class DDR3_1600_x64(DRAMCtrl):
319 # size of device in bytes
320 device_size = '512MB'
321
322 # 8x8 configuration, 8 devices each with an 8-bit interface
323 device_bus_width = 8
324
325 # DDR3 is a BL8 device
326 burst_length = 8
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405# device_size (DDR) => size of a single layer in a vault
406# ranks per channel (DDR) => number of layers
407# banks per rank (DDR) => banks per layer
408# devices per rank (DDR) => devices per layer ( 1 for HMC).
409# The parameters for which no input is available are inherited from the DDR3
410# configuration.
411# This configuration includes the latencies from the DRAM to the logic layer
412# of the HMC
413class HMC_2500_x32(DDR3_1600_x64):
414 # size of device
415 # two banks per device with each bank 4MB [2]
416 device_size = '8MB'
417
418 # 1x32 configuration, 1 device with 32 TSVs [2]
419 device_bus_width = 32
420
421 # HMC is a BL8 device [2]
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487 # than a full DRAM channel controller
488 static_backend_latency='4ns'
489 static_frontend_latency='4ns'
490
491# A single DDR3-2133 x64 channel refining a selected subset of the
492# options for the DDR-1600 configuration, based on the same DDR3-1600
493# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
494# consistent across the two configurations.
495class DDR3_2133_x64(DDR3_1600_x64):
496 # 1066 MHz
497 tCK = '0.938ns'
498
499 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
500 tBURST = '3.752ns'
501
502 # DDR3-2133 14-14-14
503 tRCD = '13.09ns'
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515 IDD4R = '191mA'
516 IDD5 = '250mA'
517 IDD3P1 = '44mA'
518 IDD2P1 = '43mA'
519 IDD6 ='20mA'
520 VDD = '1.5V'
521
522# A single DDR4-2400 x64 channel (one command and address bus), with
523# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M16)
524# in an 4x16 configuration.
525class DDR4_2400_x64(DRAMCtrl):
526 # size of device
527 device_size = '512MB'
528
529 # 4x16 configuration, 4 devices each with an 16-bit interface
530 device_bus_width = 16
531
532 # DDR4 is a BL8 device
533 burst_length = 8
534
535 # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
536 device_rowbuffer_size = '2kB'
537
538 # 4x16 configuration, so 4 devices
539 devices_per_rank = 4
540
541 # Match our DDR3 configurations which is dual rank
542 ranks_per_channel = 2
543
544 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
545 # Set to 2 for x16 case
546 bank_groups_per_rank = 2
547
548 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
549 # configurations). Currently we do not capture the additional
550 # constraints incurred by the bank groups
551 banks_per_rank = 8
552
553 # override the default buffer sizes and go for something larger to
554 # accommodate the larger bank count
555 write_buffer_size = 128
556 read_buffer_size = 64
557
558 # 1200 MHz
559 tCK = '0.833ns'
560
561 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
562 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
563 # With bank group architectures, tBURST represents the CAS-to-CAS
564 # delay for bursts to different bank groups (tCCD_S)
565 tBURST = '3.333ns'
566
567 # @2400 data rate, tCCD_L is 6 CK
568 # CAS-to-CAS delay for bursts to the same bank group
569 # tBURST is equivalent to tCCD_S; no explicit parameter required
570 # for CAS-to-CAS delay for bursts to different bank groups
571 tCCD_L = '5ns';
572
573 # DDR4-2400 16-16-16
574 tRCD = '13.32ns'
575 tCL = '13.32ns'
576 tRP = '13.32ns'
577 tRAS = '35ns'
578
579 # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
580 tRRD = '5.3ns'
581
582 # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
583 tRRD_L = '6.4ns';
584
585 tXAW = '30ns'
586 activation_limit = 4
587 tRFC = '260ns'
588
589 tWR = '15ns'
590
591 # Here using the average of WTR_S and WTR_L
592 tWTR = '5ns'
593
594 # Greater of 4 CK or 7.5 ns
595 tRTP = '7.5ns'
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602
603 # <=85C, half for >85C
604 tREFI = '7.8us'
605
606 # active powerdown and precharge powerdown exit time
607 tXP = '6ns'
608
609 # self refresh exit time
610 tXS = '120ns'
611
612 # Current values from datasheet
613 IDD0 = '70mA'
614 IDD02 = '4.6mA'
615 IDD2N = '50mA'
616 IDD3N = '67mA'
617 IDD3N2 = '3mA'
618 IDD4W = '302mA'
619 IDD4R = '230mA'
620 IDD5 = '192mA'
621 IDD3P1 = '44mA'
622 IDD2P1 = '32mA'
623 IDD6 = '20mA'
624 VDD = '1.2V'
625 VDD2 = '2.5V'
626
627# A single LPDDR2-S4 x32 interface (one command/address bus), with
628# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
629# in a 1x32 configuration.
630class LPDDR2_S4_1066_x32(DRAMCtrl):
631 # No DLL in LPDDR2
632 dll = False
633
634 # size of device
635 device_size = '512MB'
636
637 # 1x32 configuration, 1 device with a 32-bit interface
638 device_bus_width = 32
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721 IDD2P12 = '0.8mA'
722 IDD6 = '1mA'
723 IDD62 = '3.2mA'
724 VDD = '1.8V'
725 VDD2 = '1.2V'
726
727# A single WideIO x128 interface (one command and address bus), with
728# default timings based on an estimated WIO-200 8 Gbit part.
729class WideIO_200_x128(DRAMCtrl):
730 # No DLL for WideIO
731 dll = False
732
733 # size of device
734 device_size = '1024MB'
735
736 # 1x128 configuration, 1 device with a 128-bit interface
737 device_bus_width = 128
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790 tXAW = '50ns'
791 activation_limit = 2
792
793 # The WideIO specification does not provide current information
794
795# A single LPDDR3 x32 interface (one command/address bus), with
796# default timings based on a LPDDR3-1600 4 Gbit part (Micron
797# EDF8132A1MC) in a 1x32 configuration.
798class LPDDR3_1600_x32(DRAMCtrl):
799 # No DLL for LPDDR3
800 dll = False
801
802 # size of device
803 device_size = '512MB'
804
805 # 1x32 configuration, 1 device with a 32-bit interface
806 device_bus_width = 32
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890 IDD6 = '0.5mA'
891 IDD62 = '1.8mA'
892 VDD = '1.8V'
893 VDD2 = '1.2V'
894
895# A single GDDR5 x64 interface, with
896# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
897# H5GQ1H24AFR) in a 2x32 configuration.
898class GDDR5_4000_x64(DRAMCtrl):
899 # size of device
900 device_size = '128MB'
901
902 # 2x32 configuration, 1 device with a 32-bit interface
903 device_bus_width = 32
904
905 # GDDR5 is a BL8 device
906 burst_length = 8
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974 tRTW = '2ns'
975
976# A single HBM x128 interface (one command and address bus), with
977# default timings based on data publically released
978# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
979# IDD measurement values, and by extrapolating data from other classes.
980# Architecture values based on published HBM spec
981# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
982class HBM_1000_4H_x128(DRAMCtrl):
983 # HBM gen1 supports up to 8 128-bit physical channels
984 # Configuration defines a single channel, with the capacity
985 # set to (full_ stack_capacity / 8) based on 2Gb dies
986 # To use all 8 channels, set 'channels' parameter to 8 in
987 # system configuration
988
989 # 128-bit interface legacy mode
990 device_bus_width = 128
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1063
1064# A single HBM x64 interface (one command and address bus), with
1065# default timings based on HBM gen1 and data publically released
1066# A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1067# Note: This defines a pseudo-channel with a unique controller
1068# instantiated per pseudo-channel
1069# Stay at same IO rate (1Gbps) to maintain timing relationship with
1070# HBM gen1 class (HBM_1000_4H_x128) where possible
1071class HBM_1000_4H_x64(HBM_1000_4H_x128):
1072 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1073 # Configuration defines a single pseudo channel, with the capacity
1074 # set to (full_ stack_capacity / 16) based on 8Gb dies
1075 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1076 # system configuration
1077
1078 # 64-bit pseudo-channle interface
1079 device_bus_width = 64
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2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
--- 301 unchanged lines hidden (view full) ---
310 VDD = Param.Voltage("0V", "Main Voltage Range")
311
312 # Second voltage range defined by some DRAMs
313 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
314
315# A single DDR3-1600 x64 channel (one command and address bus), with
316# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
317# an 8x8 configuration.
318class DDR3_1600_x64(DRAMCtrl):
319 # size of device in bytes
320 device_size = '512MB'
321
322 # 8x8 configuration, 8 devices each with an 8-bit interface
323 device_bus_width = 8
324
325 # DDR3 is a BL8 device
326 burst_length = 8
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405# device_size (DDR) => size of a single layer in a vault
406# ranks per channel (DDR) => number of layers
407# banks per rank (DDR) => banks per layer
408# devices per rank (DDR) => devices per layer ( 1 for HMC).
409# The parameters for which no input is available are inherited from the DDR3
410# configuration.
411# This configuration includes the latencies from the DRAM to the logic layer
412# of the HMC
413class HMC_2500_x32(DDR3_1600_x64):
414 # size of device
415 # two banks per device with each bank 4MB [2]
416 device_size = '8MB'
417
418 # 1x32 configuration, 1 device with 32 TSVs [2]
419 device_bus_width = 32
420
421 # HMC is a BL8 device [2]
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487 # than a full DRAM channel controller
488 static_backend_latency='4ns'
489 static_frontend_latency='4ns'
490
491# A single DDR3-2133 x64 channel refining a selected subset of the
492# options for the DDR-1600 configuration, based on the same DDR3-1600
493# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
494# consistent across the two configurations.
495class DDR3_2133_x64(DDR3_1600_x64):
496 # 1066 MHz
497 tCK = '0.938ns'
498
499 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
500 tBURST = '3.752ns'
501
502 # DDR3-2133 14-14-14
503 tRCD = '13.09ns'
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515 IDD4R = '191mA'
516 IDD5 = '250mA'
517 IDD3P1 = '44mA'
518 IDD2P1 = '43mA'
519 IDD6 ='20mA'
520 VDD = '1.5V'
521
522# A single DDR4-2400 x64 channel (one command and address bus), with
523# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M16)
524# in an 4x16 configuration.
525class DDR4_2400_x64(DRAMCtrl):
526 # size of device
527 device_size = '512MB'
528
529 # 4x16 configuration, 4 devices each with an 16-bit interface
530 device_bus_width = 16
531
532 # DDR4 is a BL8 device
533 burst_length = 8
534
535 # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
536 device_rowbuffer_size = '2kB'
537
538 # 4x16 configuration, so 4 devices
539 devices_per_rank = 4
540
541 # Match our DDR3 configurations which is dual rank
542 ranks_per_channel = 2
543
544 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
545 # Set to 2 for x16 case
546 bank_groups_per_rank = 2
547
548 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
549 # configurations). Currently we do not capture the additional
550 # constraints incurred by the bank groups
551 banks_per_rank = 8
552
553 # override the default buffer sizes and go for something larger to
554 # accommodate the larger bank count
555 write_buffer_size = 128
556 read_buffer_size = 64
557
558 # 1200 MHz
559 tCK = '0.833ns'
560
561 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
562 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
563 # With bank group architectures, tBURST represents the CAS-to-CAS
564 # delay for bursts to different bank groups (tCCD_S)
565 tBURST = '3.333ns'
566
567 # @2400 data rate, tCCD_L is 6 CK
568 # CAS-to-CAS delay for bursts to the same bank group
569 # tBURST is equivalent to tCCD_S; no explicit parameter required
570 # for CAS-to-CAS delay for bursts to different bank groups
571 tCCD_L = '5ns';
572
573 # DDR4-2400 16-16-16
574 tRCD = '13.32ns'
575 tCL = '13.32ns'
576 tRP = '13.32ns'
577 tRAS = '35ns'
578
579 # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
580 tRRD = '5.3ns'
581
582 # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
583 tRRD_L = '6.4ns';
584
585 tXAW = '30ns'
586 activation_limit = 4
587 tRFC = '260ns'
588
589 tWR = '15ns'
590
591 # Here using the average of WTR_S and WTR_L
592 tWTR = '5ns'
593
594 # Greater of 4 CK or 7.5 ns
595 tRTP = '7.5ns'
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602
603 # <=85C, half for >85C
604 tREFI = '7.8us'
605
606 # active powerdown and precharge powerdown exit time
607 tXP = '6ns'
608
609 # self refresh exit time
610 tXS = '120ns'
611
612 # Current values from datasheet
613 IDD0 = '70mA'
614 IDD02 = '4.6mA'
615 IDD2N = '50mA'
616 IDD3N = '67mA'
617 IDD3N2 = '3mA'
618 IDD4W = '302mA'
619 IDD4R = '230mA'
620 IDD5 = '192mA'
621 IDD3P1 = '44mA'
622 IDD2P1 = '32mA'
623 IDD6 = '20mA'
624 VDD = '1.2V'
625 VDD2 = '2.5V'
626
627# A single LPDDR2-S4 x32 interface (one command/address bus), with
628# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
629# in a 1x32 configuration.
630class LPDDR2_S4_1066_x32(DRAMCtrl):
631 # No DLL in LPDDR2
632 dll = False
633
634 # size of device
635 device_size = '512MB'
636
637 # 1x32 configuration, 1 device with a 32-bit interface
638 device_bus_width = 32
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721 IDD2P12 = '0.8mA'
722 IDD6 = '1mA'
723 IDD62 = '3.2mA'
724 VDD = '1.8V'
725 VDD2 = '1.2V'
726
727# A single WideIO x128 interface (one command and address bus), with
728# default timings based on an estimated WIO-200 8 Gbit part.
729class WideIO_200_x128(DRAMCtrl):
730 # No DLL for WideIO
731 dll = False
732
733 # size of device
734 device_size = '1024MB'
735
736 # 1x128 configuration, 1 device with a 128-bit interface
737 device_bus_width = 128
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790 tXAW = '50ns'
791 activation_limit = 2
792
793 # The WideIO specification does not provide current information
794
795# A single LPDDR3 x32 interface (one command/address bus), with
796# default timings based on a LPDDR3-1600 4 Gbit part (Micron
797# EDF8132A1MC) in a 1x32 configuration.
798class LPDDR3_1600_x32(DRAMCtrl):
799 # No DLL for LPDDR3
800 dll = False
801
802 # size of device
803 device_size = '512MB'
804
805 # 1x32 configuration, 1 device with a 32-bit interface
806 device_bus_width = 32
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890 IDD6 = '0.5mA'
891 IDD62 = '1.8mA'
892 VDD = '1.8V'
893 VDD2 = '1.2V'
894
895# A single GDDR5 x64 interface, with
896# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
897# H5GQ1H24AFR) in a 2x32 configuration.
898class GDDR5_4000_x64(DRAMCtrl):
899 # size of device
900 device_size = '128MB'
901
902 # 2x32 configuration, 1 device with a 32-bit interface
903 device_bus_width = 32
904
905 # GDDR5 is a BL8 device
906 burst_length = 8
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974 tRTW = '2ns'
975
976# A single HBM x128 interface (one command and address bus), with
977# default timings based on data publically released
978# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
979# IDD measurement values, and by extrapolating data from other classes.
980# Architecture values based on published HBM spec
981# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
982class HBM_1000_4H_x128(DRAMCtrl):
983 # HBM gen1 supports up to 8 128-bit physical channels
984 # Configuration defines a single channel, with the capacity
985 # set to (full_ stack_capacity / 8) based on 2Gb dies
986 # To use all 8 channels, set 'channels' parameter to 8 in
987 # system configuration
988
989 # 128-bit interface legacy mode
990 device_bus_width = 128
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1063
1064# A single HBM x64 interface (one command and address bus), with
1065# default timings based on HBM gen1 and data publically released
1066# A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1067# Note: This defines a pseudo-channel with a unique controller
1068# instantiated per pseudo-channel
1069# Stay at same IO rate (1Gbps) to maintain timing relationship with
1070# HBM gen1 class (HBM_1000_4H_x128) where possible
1071class HBM_1000_4H_x64(HBM_1000_4H_x128):
1072 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1073 # Configuration defines a single pseudo channel, with the capacity
1074 # set to (full_ stack_capacity / 16) based on 8Gb dies
1075 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1076 # system configuration
1077
1078 # 64-bit pseudo-channle interface
1079 device_bus_width = 64
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