1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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91 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
92 addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy")
93 page_policy = Param.PageManage('open_adaptive', "Page management policy")
94
95 # enforce a limit on the number of accesses per row
96 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
97 "closing");
98
99 # pipeline latency of the controller and PHY, split into a
100 # frontend part and a backend part, with reads and writes serviced
101 # by the queues only seeing the frontend contribution, and reads
102 # serviced by the memory seeing the sum of the two
103 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
104 static_backend_latency = Param.Latency("10ns", "Static backend latency")
105
106 # the physical organisation of the DRAM

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300
301 # Second voltage range defined by some DRAMs
302 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
303
304# A single DDR3-1600 x64 channel (one command and address bus), with
305# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
306# an 8x8 configuration.
307class DDR3_1600_x64(DRAMCtrl):
308 # 8x8 configuration, 8 devices each with an 8-bit interface
309 device_bus_width = 8
310
311 # DDR3 is a BL8 device
312 burst_length = 8
313
314 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
315 device_rowbuffer_size = '1kB'

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392 IDD4R = '191mA'
393 IDD5 = '250mA'
394 VDD = '1.5V'
395
396# A single DDR4-2400 x64 channel (one command and address bus), with
397# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8)
398# in an 8x8 configuration.
399class DDR4_2400_x64(DRAMCtrl):
400 # 8x8 configuration, 8 devices each with an 8-bit interface
401 device_bus_width = 8
402
403 # DDR4 is a BL8 device
404 burst_length = 8
405
406 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
407 device_rowbuffer_size = '1kB'

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483
484# A single LPDDR2-S4 x32 interface (one command/address bus), with
485# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
486# in a 1x32 configuration.
487class LPDDR2_S4_1066_x32(DRAMCtrl):
488 # No DLL in LPDDR2
489 dll = False
490
491 # 1x32 configuration, 1 device with a 32-bit interface
492 device_bus_width = 32
493
494 # LPDDR2_S4 is a BL4 and BL8 device
495 burst_length = 8
496
497 # Each device has a page (row buffer) size of 1KB
498 # (this depends on the memory density)

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567 VDD2 = '1.2V'
568
569# A single WideIO x128 interface (one command and address bus), with
570# default timings based on an estimated WIO-200 8 Gbit part.
571class WideIO_200_x128(DRAMCtrl):
572 # No DLL for WideIO
573 dll = False
574
575 # 1x128 configuration, 1 device with a 128-bit interface
576 device_bus_width = 128
577
578 # This is a BL4 device
579 burst_length = 4
580
581 # Each device has a page (row buffer) size of 4KB
582 # (this depends on the memory density)

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633
634# A single LPDDR3 x32 interface (one command/address bus), with
635# default timings based on a LPDDR3-1600 4 Gbit part (Micron
636# EDF8132A1MC) in a 1x32 configuration.
637class LPDDR3_1600_x32(DRAMCtrl):
638 # No DLL for LPDDR3
639 dll = False
640
641 # 1x32 configuration, 1 device with a 32-bit interface
642 device_bus_width = 32
643
644 # LPDDR3 is a BL8 device
645 burst_length = 8
646
647 # Each device has a page (row buffer) size of 4KB
648 device_rowbuffer_size = '4kB'

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