1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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151
152 # time taken to complete one refresh cycle (N rows in all banks)
153 tRFC = Param.Latency("Refresh cycle time")
154
155 # refresh command interval, how often a "ref" command needs
156 # to be sent. It is 7.8 us for a 64ms refresh requirement
157 tREFI = Param.Latency("Refresh command interval")
158
159 # write-to-read turn around penalty
160 tWTR = Param.Latency("Write to read switching time")
161
162 # read-to-write turn around penalty, bus turnaround delay
163 tRTW = Param.Latency("Read to write switching time")
164
165 # minimum row activate to row activate delay time
166 tRRD = Param.Latency("ACT to ACT delay")
167
168 # time window in which a maximum number of activates are allowed
169 # to take place, set to 0 to disable
170 tXAW = Param.Latency("X activation window")
171 activation_limit = Param.Unsigned("Max number of activates in window")
172

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216 tWR = '15ns'
217
218 # Greater of 4 CK or 7.5 ns
219 tWTR = '7.5ns'
220
221 # Greater of 4 CK or 7.5 ns
222 tRTP = '7.5ns'
223
224 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
225 tRTW = '2.5ns'
226
227 # <=85C, half for >85C
228 tREFI = '7.8us'
229
230# A single DDR3-2133 x64 channel refining a selected subset of the
231# options for the DDR-1600 configuration, based on the same DDR3-1600
232# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
233# consistent across the two configurations.
234class DDR3_2133_x64(DDR3_1600_x64):

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291 tWR = '15ns'
292
293 # Here using the average of WTR_S and WTR_L
294 tWTR = '5ns'
295
296 # Greater of 4 CK or 7.5 ns
297 tRTP = '7.5ns'
298
299 # Default read-to-write bus around to 2 CK, @1200 MHz = 1.666 ns
300 tRTW = '1.666ns'
301
302 # <=85C, half for >85C
303 tREFI = '7.8us'
304
305# A single DDR3 x64 interface (one command and address bus), with
306# default timings based on DDR3-1333 4 Gbit parts in an 8x8
307# configuration, which would amount to 4 GByte of memory. This
308# configuration is primarily for comparing with DRAMSim2, and all the
309# parameters except ranks_per_channel are based on the DRAMSim2 config

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348 tRFC = '160ns'
349
350 # DDR3, <=85C, half for >85C
351 tREFI = '7.8us'
352
353 # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns
354 tWTR = '7.5ns'
355
356 # Default read-to-write bus around to 2 CK, @666.66 MHz = 3 ns
357 tRTW = '3ns'
358
359 tRRD = '6.0ns'
360
361 tXAW = '30ns'
362 activation_limit = 4
363
364
365# A single LPDDR2-S4 x32 interface (one command/address bus), with
366# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32

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411
412 # LPDDR2-S4, 4 Gbit
413 tRFC = '130ns'
414 tREFI = '3.9us'
415
416 # Irrespective of speed grade, tWTR is 7.5 ns
417 tWTR = '7.5ns'
418
419 # Default read-to-write bus around to 2 CK, @533 MHz = 3.75 ns
420 tRTW = '3.75ns'
421
422 # Activate to activate irrespective of density and speed grade
423 tRRD = '10.0ns'
424
425 # Irrespective of density, tFAW is 50 ns
426 tXAW = '50ns'
427 activation_limit = 4
428
429# A single WideIO x128 interface (one command and address bus), with

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468 tRFC = '210ns'
469
470 # WIO 8 Gb, <=85C, half for >85C
471 tREFI = '3.9us'
472
473 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
474 tWTR = '15ns'
475
476 # Default read-to-write bus around to 2 CK, @200 MHz = 10 ns
477 tRTW = '10ns'
478
479 # Activate to activate irrespective of density and speed grade
480 tRRD = '10.0ns'
481
482 # Two instead of four activation window
483 tXAW = '50ns'
484 activation_limit = 2
485
486# A single LPDDR3 x32 interface (one command/address bus), with

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531
532 # LPDDR3, 4 Gb
533 tRFC = '130ns'
534 tREFI = '3.9us'
535
536 # Irrespective of speed grade, tWTR is 7.5 ns
537 tWTR = '7.5ns'
538
539 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
540 tRTW = '2.5ns'
541
542 # Activate to activate irrespective of density and speed grade
543 tRRD = '10.0ns'
544
545 # Irrespective of size, tFAW is 50 ns
546 tXAW = '50ns'
547 activation_limit = 4