1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
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170 tXAW = Param.Latency("X activation window")
171 activation_limit = Param.Unsigned("Max number of activates in window")
172
173 # Currently rolled into other params
174 ######################################################################
175
176 # tRC - assumed to be tRAS + tRP
177
178# A single DDR3 x64 interface (one command and address bus), with
179# default timings based on DDR3-1600 4 Gbit parts in an 8x8
180# configuration, which would amount to 4 Gbyte of memory.
181class DDR3_1600_x64(DRAMCtrl):
182 # 8x8 configuration, 8 devices each with an 8-bit interface
183 device_bus_width = 8
184
185 # DDR3 is a BL8 device
186 burst_length = 8
187
188 # Each device has a page (row buffer) size of 1KB
189 # (this depends on the memory density)
190 device_rowbuffer_size = '1kB'
191
192 # 8x8 configuration, so 8 devices
193 devices_per_rank = 8
194
195 # Use two ranks
196 ranks_per_channel = 2
197
198 # DDR3 has 8 banks in all configurations
199 banks_per_rank = 8
200
201 # 800 MHz
202 tCK = '1.25ns'
203
204 # DDR3-1600 11-11-11-28
205 tRCD = '13.75ns'
206 tCL = '13.75ns'
207 tRP = '13.75ns'
208 tRAS = '35ns'
209 tWR = '15ns'
210 tRTP = '7.5ns'
211
212 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz.
213 # Note this is a BL8 DDR device.
214 tBURST = '5ns'
215
216 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns
217 tRFC = '300ns'
218
219 # DDR3, <=85C, half for >85C
220 tREFI = '7.8us'
221
222 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
223 tWTR = '7.5ns'
224
225 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
226 tRTW = '2.5ns'
227
228 # Assume 5 CK for activate to activate for different banks
229 tRRD = '6.25ns'
230
231 # With a 2kbyte page size, DDR3-1600 lands around 40 ns
232 tXAW = '40ns'
233 activation_limit = 4
234
235
236# A single DDR3 x64 interface (one command and address bus), with
237# default timings based on DDR3-1333 4 Gbit parts in an 8x8
238# configuration, which would amount to 4 GByte of memory. This
239# configuration is primarily for comparing with DRAMSim2, and all the
240# parameters except ranks_per_channel are based on the DRAMSim2 config
241# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has
242# to be manually set, depending on size of the memory to be
243# simulated. By default DRAMSim2 has 2048MB of memory with a single
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2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
--- 161 unchanged lines hidden (view full) ---
170 tXAW = Param.Latency("X activation window")
171 activation_limit = Param.Unsigned("Max number of activates in window")
172
173 # Currently rolled into other params
174 ######################################################################
175
176 # tRC - assumed to be tRAS + tRP
177
178# A single DDR3 x64 interface (one command and address bus), with
179# default timings based on DDR3-1600 4 Gbit parts in an 8x8
180# configuration, which would amount to 4 Gbyte of memory.
181class DDR3_1600_x64(DRAMCtrl):
182 # 8x8 configuration, 8 devices each with an 8-bit interface
183 device_bus_width = 8
184
185 # DDR3 is a BL8 device
186 burst_length = 8
187
188 # Each device has a page (row buffer) size of 1KB
189 # (this depends on the memory density)
190 device_rowbuffer_size = '1kB'
191
192 # 8x8 configuration, so 8 devices
193 devices_per_rank = 8
194
195 # Use two ranks
196 ranks_per_channel = 2
197
198 # DDR3 has 8 banks in all configurations
199 banks_per_rank = 8
200
201 # 800 MHz
202 tCK = '1.25ns'
203
204 # DDR3-1600 11-11-11-28
205 tRCD = '13.75ns'
206 tCL = '13.75ns'
207 tRP = '13.75ns'
208 tRAS = '35ns'
209 tWR = '15ns'
210 tRTP = '7.5ns'
211
212 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz.
213 # Note this is a BL8 DDR device.
214 tBURST = '5ns'
215
216 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns
217 tRFC = '300ns'
218
219 # DDR3, <=85C, half for >85C
220 tREFI = '7.8us'
221
222 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
223 tWTR = '7.5ns'
224
225 # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns
226 tRTW = '2.5ns'
227
228 # Assume 5 CK for activate to activate for different banks
229 tRRD = '6.25ns'
230
231 # With a 2kbyte page size, DDR3-1600 lands around 40 ns
232 tXAW = '40ns'
233 activation_limit = 4
234
235
236# A single DDR3 x64 interface (one command and address bus), with
237# default timings based on DDR3-1333 4 Gbit parts in an 8x8
238# configuration, which would amount to 4 GByte of memory. This
239# configuration is primarily for comparing with DRAMSim2, and all the
240# parameters except ranks_per_channel are based on the DRAMSim2 config
241# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has
242# to be manually set, depending on size of the memory to be
243# simulated. By default DRAMSim2 has 2048MB of memory with a single
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