1# Copyright (c) 2012-2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2013 Amin Farmahini-Farahani
14# Copyright (c) 2015 University of Kaiserslautern
15# Copyright (c) 2015 The University of Bologna
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
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27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Andreas Hansson
42# Ani Udipi
43# Omar Naji
44# Matthias Jung
45# Erfan Azarkhish
46
47from m5.params import *
48from AbstractMemory import *
49
50# Enum for memory scheduling algorithms, currently First-Come
51# First-Served and a First-Row Hit then First-Come First-Served
52class MemSched(Enum): vals = ['fcfs', 'frfcfs']
53
54# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
55# channel, rank, bank, row and column, respectively, and going from
56# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
57# suitable for an open-page policy, optimising for sequential accesses
58# hitting in the open row. For a closed-page policy, RoCoRaBaCh
59# maximises parallelism.
60class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
61
62# Enum for the page policy, either open, open_adaptive, close, or
63# close_adaptive.
64class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
65 'close_adaptive']
66
67# DRAMCtrl is a single-channel single-ported DRAM controller model
68# that aims to model the most important system-level performance
69# effects of a DRAM without getting into too much detail of the DRAM
70# itself.
71class DRAMCtrl(AbstractMemory):
72 type = 'DRAMCtrl'
73 cxx_header = "mem/dram_ctrl.hh"
74
75 # single-ported on the system interface side, instantiate with a
76 # bus in front of the controller for multiple ports
77 port = SlavePort("Slave port")
78
79 # the basic configuration of the controller architecture, note
80 # that each entry corresponds to a burst for the specific DRAM
81 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
82 # the cacheline size or request/packet size
83 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
84 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
85
86 # threshold in percent for when to forcefully trigger writes and
87 # start emptying the write buffer
88 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
89
90 # threshold in percentage for when to start writes if the read
91 # queue is empty
92 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
93
94 # minimum write bursts to schedule before switching back to reads
95 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
96 "switching to reads")
97
98 # scheduler, address map and page policy
99 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
100 addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
101 page_policy = Param.PageManage('open_adaptive', "Page management policy")
102
103 # enforce a limit on the number of accesses per row
104 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
105 "closing");
106
107 # size of DRAM Chip in Bytes
108 device_size = Param.MemorySize("Size of DRAM chip")
109
110 # pipeline latency of the controller and PHY, split into a
111 # frontend part and a backend part, with reads and writes serviced
112 # by the queues only seeing the frontend contribution, and reads
113 # serviced by the memory seeing the sum of the two
114 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
115 static_backend_latency = Param.Latency("10ns", "Static backend latency")
116
117 # the physical organisation of the DRAM
118 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
119 "device/chip")
120 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
121 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
122 "device/chip")
123 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
124 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
125
126 # default to 0 bank groups per rank, indicating bank group architecture
127 # is not used
128 # update per memory class when bank group architecture is supported
129 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
130 banks_per_rank = Param.Unsigned("Number of banks per rank")
131 # only used for the address mapping as the controller by
132 # construction is a single channel and multiple controllers have
133 # to be instantiated for a multi-channel configuration
134 channels = Param.Unsigned(1, "Number of channels")
135
136 # For power modelling we need to know if the DRAM has a DLL or not
137 dll = Param.Bool(True, "DRAM has DLL or not")
138
139 # DRAMPower provides in addition to the core power, the possibility to
140 # include RD/WR termination and IO power. This calculation assumes some
141 # default values. The integration of DRAMPower with gem5 does not include
142 # IO and RD/WR termination power by default. This might be added as an
143 # additional feature in the future.
144
145 # timing behaviour and constraints - all in nanoseconds
146
147 # the base clock period of the DRAM
148 tCK = Param.Latency("Clock period")
149
150 # the amount of time in nanoseconds from issuing an activate command
151 # to the data being available in the row buffer for a read/write
152 tRCD = Param.Latency("RAS to CAS delay")
153
154 # the time from issuing a read/write command to seeing the actual data
155 tCL = Param.Latency("CAS latency")
156
157 # minimum time between a precharge and subsequent activate
158 tRP = Param.Latency("Row precharge time")
159
160 # minimum time between an activate and a precharge to the same row
161 tRAS = Param.Latency("ACT to PRE delay")
162
163 # minimum time between a write data transfer and a precharge
164 tWR = Param.Latency("Write recovery time")
165
166 # minimum time between a read and precharge command
167 tRTP = Param.Latency("Read to precharge")
168
169 # time to complete a burst transfer, typically the burst length
170 # divided by two due to the DDR bus, but by making it a parameter
171 # it is easier to also evaluate SDR memories like WideIO.
172 # This parameter has to account for burst length.
173 # Read/Write requests with data size larger than one full burst are broken
174 # down into multiple requests in the controller
175 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
176 # With bank group architectures, tBURST represents the CAS-to-CAS
177 # delay for bursts to different bank groups (tCCD_S)
178 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
179
180 # CAS-to-CAS delay for bursts to the same bank group
181 # only utilized with bank group architectures; set to 0 for default case
182 # tBURST is equivalent to tCCD_S; no explicit parameter required
183 # for CAS-to-CAS delay for bursts to different bank groups
184 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
185
186 # time taken to complete one refresh cycle (N rows in all banks)
187 tRFC = Param.Latency("Refresh cycle time")
188
189 # refresh command interval, how often a "ref" command needs
190 # to be sent. It is 7.8 us for a 64ms refresh requirement
191 tREFI = Param.Latency("Refresh command interval")
192
193 # write-to-read, same rank turnaround penalty
194 tWTR = Param.Latency("Write to read, same rank switching time")
195
196 # read-to-write, same rank turnaround penalty
197 tRTW = Param.Latency("Read to write, same rank switching time")
198
199 # rank-to-rank bus delay penalty
200 # this does not correlate to a memory timing parameter and encompasses:
201 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
202 # different rank bus delay
203 tCS = Param.Latency("Rank to rank switching time")
204
205 # minimum row activate to row activate delay time
206 tRRD = Param.Latency("ACT to ACT delay")
207
208 # only utilized with bank group architectures; set to 0 for default case
209 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
210
211 # time window in which a maximum number of activates are allowed
212 # to take place, set to 0 to disable
213 tXAW = Param.Latency("X activation window")
214 activation_limit = Param.Unsigned("Max number of activates in window")
215
216 # time to exit power-down mode
217 # Exit power-down to next valid command delay
218 tXP = Param.Latency("0ns", "Power-up Delay")
219
220 # Exit Powerdown to commands requiring a locked DLL
221 tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
222
223 # time to exit self-refresh mode
224 tXS = Param.Latency("0ns", "Self-refresh exit latency")
225
226 # time to exit self-refresh mode with locked DLL
227 tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
228
229 # Currently rolled into other params
230 ######################################################################
231
232 # tRC - assumed to be tRAS + tRP
233
234 # Power Behaviour and Constraints
235 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
236 # defined as VDD and VDD2. Each current is defined for each voltage domain
237 # separately. For example, current IDD0 is active-precharge current for
238 # voltage domain VDD and current IDD02 is active-precharge current for
239 # voltage domain VDD2.
240 # By default all currents are set to 0mA. Users who are only interested in
241 # the performance of DRAMs can leave them at 0.
242
243 # Operating 1 Bank Active-Precharge current
244 IDD0 = Param.Current("0mA", "Active precharge current")
245
246 # Operating 1 Bank Active-Precharge current multiple voltage Range
247 IDD02 = Param.Current("0mA", "Active precharge current VDD2")
248
249 # Precharge Power-down Current: Slow exit
250 IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
251
252 # Precharge Power-down Current: Slow exit multiple voltage Range
253 IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
254
255 # Precharge Power-down Current: Fast exit
256 IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
257
258 # Precharge Power-down Current: Fast exit multiple voltage Range
259 IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
260
261 # Precharge Standby current
262 IDD2N = Param.Current("0mA", "Precharge Standby current")
263
264 # Precharge Standby current multiple voltage range
265 IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
266
267 # Active Power-down current: slow exit
268 IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
269
270 # Active Power-down current: slow exit multiple voltage range
271 IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
272
273 # Active Power-down current : fast exit
274 IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
275
276 # Active Power-down current : fast exit multiple voltage range
277 IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
278
279 # Active Standby current
280 IDD3N = Param.Current("0mA", "Active Standby current")
281
282 # Active Standby current multiple voltage range
283 IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
284
285 # Burst Read Operating Current
286 IDD4R = Param.Current("0mA", "READ current")
287
288 # Burst Read Operating Current multiple voltage range
289 IDD4R2 = Param.Current("0mA", "READ current VDD2")
290
291 # Burst Write Operating Current
292 IDD4W = Param.Current("0mA", "WRITE current")
293
294 # Burst Write Operating Current multiple voltage range
295 IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
296
297 # Refresh Current
298 IDD5 = Param.Current("0mA", "Refresh current")
299
300 # Refresh Current multiple voltage range
301 IDD52 = Param.Current("0mA", "Refresh current VDD2")
302
303 # Self-Refresh Current
304 IDD6 = Param.Current("0mA", "Self-refresh Current")
305
306 # Self-Refresh Current multiple voltage range
307 IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
308
309 # Main voltage range of the DRAM
310 VDD = Param.Voltage("0V", "Main Voltage Range")
311
312 # Second voltage range defined by some DRAMs
313 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
314
315# A single DDR3-1600 x64 channel (one command and address bus), with
316# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
317# an 8x8 configuration.
318class DDR3_1600_8x8(DRAMCtrl):
319 # size of device in bytes
320 device_size = '512MB'
321
322 # 8x8 configuration, 8 devices each with an 8-bit interface
323 device_bus_width = 8
324
325 # DDR3 is a BL8 device
326 burst_length = 8
327
328 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
329 device_rowbuffer_size = '1kB'
330
331 # 8x8 configuration, so 8 devices
332 devices_per_rank = 8
333
334 # Use two ranks
335 ranks_per_channel = 2
336
337 # DDR3 has 8 banks in all configurations
338 banks_per_rank = 8
339
340 # 800 MHz
341 tCK = '1.25ns'
342
343 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
344 tBURST = '5ns'
345
346 # DDR3-1600 11-11-11
347 tRCD = '13.75ns'
348 tCL = '13.75ns'
349 tRP = '13.75ns'
350 tRAS = '35ns'
351 tRRD = '6ns'
352 tXAW = '30ns'
353 activation_limit = 4
354 tRFC = '260ns'
355
356 tWR = '15ns'
357
358 # Greater of 4 CK or 7.5 ns
359 tWTR = '7.5ns'
360
361 # Greater of 4 CK or 7.5 ns
362 tRTP = '7.5ns'
363
364 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
365 tRTW = '2.5ns'
366
367 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
368 tCS = '2.5ns'
369
370 # <=85C, half for >85C
371 tREFI = '7.8us'
372
373 # active powerdown and precharge powerdown exit time
374 tXP = '6ns'
375
376 # self refresh exit time
377 tXS = '270ns'
378
379 # Current values from datasheet Die Rev E,J
380 IDD0 = '55mA'
381 IDD2N = '32mA'
382 IDD3N = '38mA'
383 IDD4W = '125mA'
384 IDD4R = '157mA'
385 IDD5 = '235mA'
386 IDD3P1 = '38mA'
387 IDD2P1 = '32mA'
388 IDD6 = '20mA'
389 VDD = '1.5V'
390
391# A single HMC-2500 x32 model based on:
392# [1] DRAMSpec: a high-level DRAM bank modelling tool
393# developed at the University of Kaiserslautern. This high level tool
394# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
395# estimate the DRAM bank latency and power numbers.
396# [2] High performance AXI-4.0 based interconnect for extensible smart memory
397# cubes (E. Azarkhish et. al)
398# Assumed for the HMC model is a 30 nm technology node.
399# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
400# layers).
401# Each layer has 16 vaults and each vault consists of 2 banks per layer.
402# In order to be able to use the same controller used for 2D DRAM generations
403# for HMC, the following analogy is done:
404# Channel (DDR) => Vault (HMC)
405# device_size (DDR) => size of a single layer in a vault
406# ranks per channel (DDR) => number of layers
407# banks per rank (DDR) => banks per layer
408# devices per rank (DDR) => devices per layer ( 1 for HMC).
409# The parameters for which no input is available are inherited from the DDR3
410# configuration.
411# This configuration includes the latencies from the DRAM to the logic layer
412# of the HMC
413class HMC_2500_1x32(DDR3_1600_8x8):
414 # size of device
415 # two banks per device with each bank 4MB [2]
416 device_size = '8MB'
417
418 # 1x32 configuration, 1 device with 32 TSVs [2]
419 device_bus_width = 32
420
421 # HMC is a BL8 device [2]
422 burst_length = 8
423
424 # Each device has a page (row buffer) size of 256 bytes [2]
425 device_rowbuffer_size = '256B'
426
427 # 1x32 configuration, so 1 device [2]
428 devices_per_rank = 1
429
430 # 4 layers so 4 ranks [2]
431 ranks_per_channel = 4
432
433 # HMC has 2 banks per layer [2]
434 # Each layer represents a rank. With 4 layers and 8 banks in total, each
435 # layer has 2 banks; thus 2 banks per rank.
436 banks_per_rank = 2
437
438 # 1250 MHz [2]
439 tCK = '0.8ns'
440
441 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
442 tBURST = '3.2ns'
443
444 # Values using DRAMSpec HMC model [1]
445 tRCD = '10.2ns'
446 tCL = '9.9ns'
447 tRP = '7.7ns'
448 tRAS = '21.6ns'
449
450 # tRRD depends on the power supply network for each vendor.
451 # We assume a tRRD of a double bank approach to be equal to 4 clock
452 # cycles (Assumption)
453 tRRD = '3.2ns'
454
455 # activation limit is set to 0 since there are only 2 banks per vault
456 # layer.
457 activation_limit = 0
458
459 # Values using DRAMSpec HMC model [1]
460 tRFC = '59ns'
461 tWR = '8ns'
462 tRTP = '4.9ns'
463
464 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
465 # 0.8 ns (Assumption)
466 tCS = '0.8ns'
467
468 # Value using DRAMSpec HMC model [1]
469 tREFI = '3.9us'
470
471 # The default page policy in the vault controllers is simple closed page
472 # [2] nevertheless 'close' policy opens and closes the row multiple times
473 # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
474 page_policy = 'close_adaptive'
475
476 # RoCoRaBaCh resembles the default address mapping in HMC
477 addr_mapping = 'RoCoRaBaCh'
478 min_writes_per_switch = 8
479
480 # These parameters do not directly correlate with buffer_size in real
481 # hardware. Nevertheless, their value has been tuned to achieve a
482 # bandwidth similar to the cycle-accurate model in [2]
483 write_buffer_size = 32
484 read_buffer_size = 32
485
486 # The static latency of the vault controllers is estimated to be smaller
487 # than a full DRAM channel controller
488 static_backend_latency='4ns'
489 static_frontend_latency='4ns'
490
491# A single DDR3-2133 x64 channel refining a selected subset of the
492# options for the DDR-1600 configuration, based on the same DDR3-1600
493# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
494# consistent across the two configurations.
495class DDR3_2133_8x8(DDR3_1600_8x8):
496 # 1066 MHz
497 tCK = '0.938ns'
498
499 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
500 tBURST = '3.752ns'
501
502 # DDR3-2133 14-14-14
503 tRCD = '13.09ns'
504 tCL = '13.09ns'
505 tRP = '13.09ns'
506 tRAS = '33ns'
507 tRRD = '5ns'
508 tXAW = '25ns'
509
510 # Current values from datasheet
511 IDD0 = '70mA'
512 IDD2N = '37mA'
513 IDD3N = '44mA'
514 IDD4W = '157mA'
515 IDD4R = '191mA'
516 IDD5 = '250mA'
517 IDD3P1 = '44mA'
518 IDD2P1 = '43mA'
519 IDD6 ='20mA'
520 VDD = '1.5V'
521
522# A single DDR4-2400 x64 channel (one command and address bus), with
523# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
524# in an 16x4 configuration.
525# Total channel capacity is 32GB
526# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
527class DDR4_2400_16x4(DRAMCtrl):
528 # size of device
529 device_size = '1GB'
530
531 # 16x4 configuration, 16 devices each with a 4-bit interface
532 device_bus_width = 4
533
534 # DDR4 is a BL8 device
535 burst_length = 8
536
537 # Each device has a page (row buffer) size of 512 byte (1K columns x4)
538 device_rowbuffer_size = '512B'
539
540 # 16x4 configuration, so 16 devices
541 devices_per_rank = 16
542
543 # Match our DDR3 configurations which is dual rank
544 ranks_per_channel = 2
545
546 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
547 # Set to 4 for x4 case
548 bank_groups_per_rank = 4
549
550 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
551 # configurations). Currently we do not capture the additional
552 # constraints incurred by the bank groups
553 banks_per_rank = 16
554
555 # override the default buffer sizes and go for something larger to
556 # accommodate the larger bank count
557 write_buffer_size = 128
558 read_buffer_size = 64
559
560 # 1200 MHz
561 tCK = '0.833ns'
562
563 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
564 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
565 # With bank group architectures, tBURST represents the CAS-to-CAS
566 # delay for bursts to different bank groups (tCCD_S)
567 tBURST = '3.332ns'
568
569 # @2400 data rate, tCCD_L is 6 CK
570 # CAS-to-CAS delay for bursts to the same bank group
571 # tBURST is equivalent to tCCD_S; no explicit parameter required
572 # for CAS-to-CAS delay for bursts to different bank groups
573 tCCD_L = '5ns';
574
575 # DDR4-2400 17-17-17
576 tRCD = '14.16ns'
577 tCL = '14.16ns'
578 tRP = '14.16ns'
579 tRAS = '32ns'
580
581 # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
582 tRRD = '3.332ns'
583
584 # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
585 tRRD_L = '4.9ns';
586
587 # tFAW for 512B page is MAX(16 CK, 13ns)
588 tXAW = '13.328ns'
589 activation_limit = 4
590 # tRFC is 350ns
591 tRFC = '350ns'
592
593 tWR = '15ns'
594
595 # Here using the average of WTR_S and WTR_L
596 tWTR = '5ns'
597
598 # Greater of 4 CK or 7.5 ns
599 tRTP = '7.5ns'
600
601 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
602 tRTW = '1.666ns'
603
604 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
605 tCS = '1.666ns'
606
607 # <=85C, half for >85C
608 tREFI = '7.8us'
609
610 # active powerdown and precharge powerdown exit time
611 tXP = '6ns'
612
613 # self refresh exit time
614 # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
615 # tRFC + 10ns = 340ns
616 tXS = '340ns'
617
618 # Current values from datasheet
619 IDD0 = '43mA'
620 IDD02 = '3mA'
621 IDD2N = '34mA'
622 IDD3N = '38mA'
623 IDD3N2 = '3mA'
624 IDD4W = '103mA'
625 IDD4R = '110mA'
626 IDD5 = '250mA'
627 IDD3P1 = '32mA'
628 IDD2P1 = '25mA'
629 IDD6 = '30mA'
630 VDD = '1.2V'
631 VDD2 = '2.5V'
632
633# A single DDR4-2400 x64 channel (one command and address bus), with
634# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
635# in an 8x8 configuration.
636# Total channel capacity is 16GB
637# 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
638class DDR4_2400_8x8(DDR4_2400_16x4):
639 # 8x8 configuration, 8 devices each with an 8-bit interface
640 device_bus_width = 8
641
642 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
643 device_rowbuffer_size = '1kB'
644
645 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
646 tRRD_L = '4.9ns';
647
648 tXAW = '21ns'
649
650 # Current values from datasheet
651 IDD0 = '48mA'
652 IDD3N = '43mA'
653 IDD4W = '123mA'
654 IDD4R = '135mA'
655 IDD3P1 = '37mA'
656
657# A single DDR4-2400 x64 channel (one command and address bus), with
658# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
659# in an 4x16 configuration.
660# Total channel capacity is 4GB
661# 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
662class DDR4_2400_4x16(DDR4_2400_16x4):
663 # 4x16 configuration, 4 devices each with an 16-bit interface
664 device_bus_width = 16
665
666 # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
667 device_rowbuffer_size = '2kB'
668
669 # 4x16 configuration, so 4 devices
670 devices_per_rank = 4
671
672 # Single rank for x16
673 ranks_per_channel = 1
674
675 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
676 # Set to 2 for x16 case
677 bank_groups_per_rank = 2
678
679 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
680 # configurations). Currently we do not capture the additional
681 # constraints incurred by the bank groups
682 banks_per_rank = 8
683
684 # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
685 tRRD = '5.3ns'
686
687 # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
688 tRRD_L = '6.4ns';
689
690 tXAW = '30ns'
691
692 # Current values from datasheet
693 IDD0 = '80mA'
694 IDD02 = '4mA'
695 IDD2N = '34mA'
696 IDD3N = '47mA'
697 IDD4W = '228mA'
698 IDD4R = '243mA'
699 IDD5 = '280mA'
700 IDD3P1 = '41mA'
701
702# A single LPDDR2-S4 x32 interface (one command/address bus), with
703# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
704# in a 1x32 configuration.
705class LPDDR2_S4_1066_1x32(DRAMCtrl):
706 # No DLL in LPDDR2
707 dll = False
708
709 # size of device
710 device_size = '512MB'
711
712 # 1x32 configuration, 1 device with a 32-bit interface
713 device_bus_width = 32
714
715 # LPDDR2_S4 is a BL4 and BL8 device
716 burst_length = 8
717
718 # Each device has a page (row buffer) size of 1KB
719 # (this depends on the memory density)
720 device_rowbuffer_size = '1kB'
721
722 # 1x32 configuration, so 1 device
723 devices_per_rank = 1
724
725 # Use a single rank
726 ranks_per_channel = 1
727
728 # LPDDR2-S4 has 8 banks in all configurations
729 banks_per_rank = 8
730
731 # 533 MHz
732 tCK = '1.876ns'
733
734 # Fixed at 15 ns
735 tRCD = '15ns'
736
737 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
738 tCL = '15ns'
739
740 # Pre-charge one bank 15 ns (all banks 18 ns)
741 tRP = '15ns'
742
743 tRAS = '42ns'
744 tWR = '15ns'
745
746 tRTP = '7.5ns'
747
748 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
749 # Note this is a BL8 DDR device.
750 # Requests larger than 32 bytes are broken down into multiple requests
751 # in the controller
752 tBURST = '7.5ns'
753
754 # LPDDR2-S4, 4 Gbit
755 tRFC = '130ns'
756 tREFI = '3.9us'
757
758 # active powerdown and precharge powerdown exit time
759 tXP = '7.5ns'
760
761 # self refresh exit time
762 tXS = '140ns'
763
764 # Irrespective of speed grade, tWTR is 7.5 ns
765 tWTR = '7.5ns'
766
767 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
768 tRTW = '3.75ns'
769
770 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
771 tCS = '3.75ns'
772
773 # Activate to activate irrespective of density and speed grade
774 tRRD = '10.0ns'
775
776 # Irrespective of density, tFAW is 50 ns
777 tXAW = '50ns'
778 activation_limit = 4
779
780 # Current values from datasheet
781 IDD0 = '15mA'
782 IDD02 = '70mA'
783 IDD2N = '2mA'
784 IDD2N2 = '30mA'
785 IDD3N = '2.5mA'
786 IDD3N2 = '30mA'
787 IDD4W = '10mA'
788 IDD4W2 = '190mA'
789 IDD4R = '3mA'
790 IDD4R2 = '220mA'
791 IDD5 = '40mA'
792 IDD52 = '150mA'
793 IDD3P1 = '1.2mA'
794 IDD3P12 = '8mA'
795 IDD2P1 = '0.6mA'
796 IDD2P12 = '0.8mA'
797 IDD6 = '1mA'
798 IDD62 = '3.2mA'
799 VDD = '1.8V'
800 VDD2 = '1.2V'
801
802# A single WideIO x128 interface (one command and address bus), with
803# default timings based on an estimated WIO-200 8 Gbit part.
804class WideIO_200_1x128(DRAMCtrl):
805 # No DLL for WideIO
806 dll = False
807
808 # size of device
809 device_size = '1024MB'
810
811 # 1x128 configuration, 1 device with a 128-bit interface
812 device_bus_width = 128
813
814 # This is a BL4 device
815 burst_length = 4
816
817 # Each device has a page (row buffer) size of 4KB
818 # (this depends on the memory density)
819 device_rowbuffer_size = '4kB'
820
821 # 1x128 configuration, so 1 device
822 devices_per_rank = 1
823
824 # Use one rank for a one-high die stack
825 ranks_per_channel = 1
826
827 # WideIO has 4 banks in all configurations
828 banks_per_rank = 4
829
830 # 200 MHz
831 tCK = '5ns'
832
833 # WIO-200
834 tRCD = '18ns'
835 tCL = '18ns'
836 tRP = '18ns'
837 tRAS = '42ns'
838 tWR = '15ns'
839 # Read to precharge is same as the burst
840 tRTP = '20ns'
841
842 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
843 # Note this is a BL4 SDR device.
844 tBURST = '20ns'
845
846 # WIO 8 Gb
847 tRFC = '210ns'
848
849 # WIO 8 Gb, <=85C, half for >85C
850 tREFI = '3.9us'
851
852 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
853 tWTR = '15ns'
854
855 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
856 tRTW = '10ns'
857
858 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
859 tCS = '10ns'
860
861 # Activate to activate irrespective of density and speed grade
862 tRRD = '10.0ns'
863
864 # Two instead of four activation window
865 tXAW = '50ns'
866 activation_limit = 2
867
868 # The WideIO specification does not provide current information
869
870# A single LPDDR3 x32 interface (one command/address bus), with
871# default timings based on a LPDDR3-1600 4 Gbit part (Micron
872# EDF8132A1MC) in a 1x32 configuration.
873class LPDDR3_1600_1x32(DRAMCtrl):
874 # No DLL for LPDDR3
875 dll = False
876
877 # size of device
878 device_size = '512MB'
879
880 # 1x32 configuration, 1 device with a 32-bit interface
881 device_bus_width = 32
882
883 # LPDDR3 is a BL8 device
884 burst_length = 8
885
886 # Each device has a page (row buffer) size of 4KB
887 device_rowbuffer_size = '4kB'
888
889 # 1x32 configuration, so 1 device
890 devices_per_rank = 1
891
892 # Technically the datasheet is a dual-rank package, but for
893 # comparison with the LPDDR2 config we stick to a single rank
894 ranks_per_channel = 1
895
896 # LPDDR3 has 8 banks in all configurations
897 banks_per_rank = 8
898
899 # 800 MHz
900 tCK = '1.25ns'
901
902 tRCD = '18ns'
903
904 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
905 tCL = '15ns'
906
907 tRAS = '42ns'
908 tWR = '15ns'
909
910 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
911 tRTP = '7.5ns'
912
913 # Pre-charge one bank 18 ns (all banks 21 ns)
914 tRP = '18ns'
915
916 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
917 # Note this is a BL8 DDR device.
918 # Requests larger than 32 bytes are broken down into multiple requests
919 # in the controller
920 tBURST = '5ns'
921
922 # LPDDR3, 4 Gb
923 tRFC = '130ns'
924 tREFI = '3.9us'
925
926 # active powerdown and precharge powerdown exit time
927 tXP = '7.5ns'
928
929 # self refresh exit time
930 tXS = '140ns'
931
932 # Irrespective of speed grade, tWTR is 7.5 ns
933 tWTR = '7.5ns'
934
935 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
936 tRTW = '2.5ns'
937
938 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
939 tCS = '2.5ns'
940
941 # Activate to activate irrespective of density and speed grade
942 tRRD = '10.0ns'
943
944 # Irrespective of size, tFAW is 50 ns
945 tXAW = '50ns'
946 activation_limit = 4
947
948 # Current values from datasheet
949 IDD0 = '8mA'
950 IDD02 = '60mA'
951 IDD2N = '0.8mA'
952 IDD2N2 = '26mA'
953 IDD3N = '2mA'
954 IDD3N2 = '34mA'
955 IDD4W = '2mA'
956 IDD4W2 = '190mA'
957 IDD4R = '2mA'
958 IDD4R2 = '230mA'
959 IDD5 = '28mA'
960 IDD52 = '150mA'
961 IDD3P1 = '1.4mA'
962 IDD3P12 = '11mA'
963 IDD2P1 = '0.8mA'
964 IDD2P12 = '1.8mA'
965 IDD6 = '0.5mA'
966 IDD62 = '1.8mA'
967 VDD = '1.8V'
968 VDD2 = '1.2V'
969
970# A single GDDR5 x64 interface, with
971# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
972# H5GQ1H24AFR) in a 2x32 configuration.
973class GDDR5_4000_2x32(DRAMCtrl):
974 # size of device
975 device_size = '128MB'
976
977 # 2x32 configuration, 1 device with a 32-bit interface
978 device_bus_width = 32
979
980 # GDDR5 is a BL8 device
981 burst_length = 8
982
983 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
984 device_rowbuffer_size = '256B'
985
986 # 2x32 configuration, so 2 devices
987 devices_per_rank = 2
988
989 # assume single rank
990 ranks_per_channel = 1
991
992 # GDDR5 has 4 bank groups
993 bank_groups_per_rank = 4
994
995 # GDDR5 has 16 banks with 4 bank groups
996 banks_per_rank = 16
997
998 # 1000 MHz
999 tCK = '1ns'
1000
1001 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
1002 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
1003 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
1004 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
1005 # With bank group architectures, tBURST represents the CAS-to-CAS
1006 # delay for bursts to different bank groups (tCCD_S)
1007 tBURST = '2ns'
1008
1009 # @1000MHz data rate, tCCD_L is 3 CK
1010 # CAS-to-CAS delay for bursts to the same bank group
1011 # tBURST is equivalent to tCCD_S; no explicit parameter required
1012 # for CAS-to-CAS delay for bursts to different bank groups
1013 tCCD_L = '3ns';
1014
1015 tRCD = '12ns'
1016
1017 # tCL is not directly found in datasheet and assumed equal tRCD
1018 tCL = '12ns'
1019
1020 tRP = '12ns'
1021 tRAS = '28ns'
1022
1023 # RRD_S (different bank group)
1024 # RRD_S is 5.5 ns in datasheet.
1025 # rounded to the next multiple of tCK
1026 tRRD = '6ns'
1027
1028 # RRD_L (same bank group)
1029 # RRD_L is 5.5 ns in datasheet.
1030 # rounded to the next multiple of tCK
1031 tRRD_L = '6ns'
1032
1033 tXAW = '23ns'
1034
1035 # tXAW < 4 x tRRD.
1036 # Therefore, activation limit is set to 0
1037 activation_limit = 0
1038
1039 tRFC = '65ns'
1040 tWR = '12ns'
1041
1042 # Here using the average of WTR_S and WTR_L
1043 tWTR = '5ns'
1044
1045 # Read-to-Precharge 2 CK
1046 tRTP = '2ns'
1047
1048 # Assume 2 cycles
1049 tRTW = '2ns'
1050
1051# A single HBM x128 interface (one command and address bus), with
1052# default timings based on data publically released
1053# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
1054# IDD measurement values, and by extrapolating data from other classes.
1055# Architecture values based on published HBM spec
1056# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
1057class HBM_1000_4H_1x128(DRAMCtrl):
1058 # HBM gen1 supports up to 8 128-bit physical channels
1059 # Configuration defines a single channel, with the capacity
1060 # set to (full_ stack_capacity / 8) based on 2Gb dies
1061 # To use all 8 channels, set 'channels' parameter to 8 in
1062 # system configuration
1063
1064 # 128-bit interface legacy mode
1065 device_bus_width = 128
1066
1067 # HBM supports BL4 and BL2 (legacy mode only)
1068 burst_length = 4
1069
1070 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
1071 # with 8 channels, 128MB per channel
1072 device_size = '128MB'
1073
1074 device_rowbuffer_size = '2kB'
1075
1076 # 1x128 configuration
1077 devices_per_rank = 1
1078
1079 # HBM does not have a CS pin; set rank to 1
1080 ranks_per_channel = 1
1081
1082 # HBM has 8 or 16 banks depending on capacity
1083 # 2Gb dies have 8 banks
1084 banks_per_rank = 8
1085
1086 # depending on frequency, bank groups may be required
1087 # will always have 4 bank groups when enabled
1088 # current specifications do not define the minimum frequency for
1089 # bank group architecture
1090 # setting bank_groups_per_rank to 0 to disable until range is defined
1091 bank_groups_per_rank = 0
1092
1093 # 500 MHz for 1Gbps DDR data rate
1094 tCK = '2ns'
1095
1096 # use values from IDD measurement in JEDEC spec
1097 # use tRP value for tRCD and tCL similar to other classes
1098 tRP = '15ns'
1099 tRCD = '15ns'
1100 tCL = '15ns'
1101 tRAS = '33ns'
1102
1103 # BL2 and BL4 supported, default to BL4
1104 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
1105 tBURST = '4ns'
1106
1107 # value for 2Gb device from JEDEC spec
1108 tRFC = '160ns'
1109
1110 # value for 2Gb device from JEDEC spec
1111 tREFI = '3.9us'
1112
1113 # extrapolate the following from LPDDR configs, using ns values
1114 # to minimize burst length, prefetch differences
1115 tWR = '18ns'
1116 tRTP = '7.5ns'
1117 tWTR = '10ns'
1118
1119 # start with 2 cycles turnaround, similar to other memory classes
1120 # could be more with variations across the stack
1121 tRTW = '4ns'
1122
1123 # single rank device, set to 0
1124 tCS = '0ns'
1125
1126 # from MemCon example, tRRD is 4ns with 2ns tCK
1127 tRRD = '4ns'
1128
1129 # from MemCon example, tFAW is 30ns with 2ns tCK
1130 tXAW = '30ns'
1131 activation_limit = 4
1132
1133 # 4tCK
1134 tXP = '8ns'
1135
1136 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1137 tXS = '168ns'
1138
1139# A single HBM x64 interface (one command and address bus), with
1140# default timings based on HBM gen1 and data publically released
1141# A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1142# Note: This defines a pseudo-channel with a unique controller
1143# instantiated per pseudo-channel
1144# Stay at same IO rate (1Gbps) to maintain timing relationship with
1145# HBM gen1 class (HBM_1000_4H_x128) where possible
1146class HBM_1000_4H_1x64(HBM_1000_4H_1x128):
1147 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1148 # Configuration defines a single pseudo channel, with the capacity
1149 # set to (full_ stack_capacity / 16) based on 8Gb dies
1150 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1151 # system configuration
1152
1153 # 64-bit pseudo-channle interface
1154 device_bus_width = 64
1155
1156 # HBM pseudo-channel only supports BL4
1157 burst_length = 4
1158
1159 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1160 # with 16 channels, 256MB per channel
1161 device_size = '256MB'
1162
1163 # page size is halved with pseudo-channel; maintaining the same same number
1164 # of rows per pseudo-channel with 2X banks across 2 channels
1165 device_rowbuffer_size = '1kB'
1166
1167 # HBM has 8 or 16 banks depending on capacity
1168 # Starting with 4Gb dies, 16 banks are defined
1169 banks_per_rank = 16
1170
1171 # reset tRFC for larger, 8Gb device
1172 # use HBM1 4Gb value as a starting point
1173 tRFC = '260ns'
1174
1175 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1176 tXS = '268ns'
1177 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1178 tCS = '2ns'
1179 tREFI = '3.9us'
1180
1181 # active powerdown and precharge powerdown exit time
1182 tXP = '10ns'
1183
1184 # self refresh exit time
1185 tXS = '65ns'
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2013 Amin Farmahini-Farahani
14# Copyright (c) 2015 University of Kaiserslautern
15# Copyright (c) 2015 The University of Bologna
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Andreas Hansson
42# Ani Udipi
43# Omar Naji
44# Matthias Jung
45# Erfan Azarkhish
46
47from m5.params import *
48from AbstractMemory import *
49
50# Enum for memory scheduling algorithms, currently First-Come
51# First-Served and a First-Row Hit then First-Come First-Served
52class MemSched(Enum): vals = ['fcfs', 'frfcfs']
53
54# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
55# channel, rank, bank, row and column, respectively, and going from
56# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
57# suitable for an open-page policy, optimising for sequential accesses
58# hitting in the open row. For a closed-page policy, RoCoRaBaCh
59# maximises parallelism.
60class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
61
62# Enum for the page policy, either open, open_adaptive, close, or
63# close_adaptive.
64class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
65 'close_adaptive']
66
67# DRAMCtrl is a single-channel single-ported DRAM controller model
68# that aims to model the most important system-level performance
69# effects of a DRAM without getting into too much detail of the DRAM
70# itself.
71class DRAMCtrl(AbstractMemory):
72 type = 'DRAMCtrl'
73 cxx_header = "mem/dram_ctrl.hh"
74
75 # single-ported on the system interface side, instantiate with a
76 # bus in front of the controller for multiple ports
77 port = SlavePort("Slave port")
78
79 # the basic configuration of the controller architecture, note
80 # that each entry corresponds to a burst for the specific DRAM
81 # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
82 # the cacheline size or request/packet size
83 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
84 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
85
86 # threshold in percent for when to forcefully trigger writes and
87 # start emptying the write buffer
88 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
89
90 # threshold in percentage for when to start writes if the read
91 # queue is empty
92 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
93
94 # minimum write bursts to schedule before switching back to reads
95 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
96 "switching to reads")
97
98 # scheduler, address map and page policy
99 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
100 addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
101 page_policy = Param.PageManage('open_adaptive', "Page management policy")
102
103 # enforce a limit on the number of accesses per row
104 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
105 "closing");
106
107 # size of DRAM Chip in Bytes
108 device_size = Param.MemorySize("Size of DRAM chip")
109
110 # pipeline latency of the controller and PHY, split into a
111 # frontend part and a backend part, with reads and writes serviced
112 # by the queues only seeing the frontend contribution, and reads
113 # serviced by the memory seeing the sum of the two
114 static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
115 static_backend_latency = Param.Latency("10ns", "Static backend latency")
116
117 # the physical organisation of the DRAM
118 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
119 "device/chip")
120 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
121 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
122 "device/chip")
123 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
124 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
125
126 # default to 0 bank groups per rank, indicating bank group architecture
127 # is not used
128 # update per memory class when bank group architecture is supported
129 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
130 banks_per_rank = Param.Unsigned("Number of banks per rank")
131 # only used for the address mapping as the controller by
132 # construction is a single channel and multiple controllers have
133 # to be instantiated for a multi-channel configuration
134 channels = Param.Unsigned(1, "Number of channels")
135
136 # For power modelling we need to know if the DRAM has a DLL or not
137 dll = Param.Bool(True, "DRAM has DLL or not")
138
139 # DRAMPower provides in addition to the core power, the possibility to
140 # include RD/WR termination and IO power. This calculation assumes some
141 # default values. The integration of DRAMPower with gem5 does not include
142 # IO and RD/WR termination power by default. This might be added as an
143 # additional feature in the future.
144
145 # timing behaviour and constraints - all in nanoseconds
146
147 # the base clock period of the DRAM
148 tCK = Param.Latency("Clock period")
149
150 # the amount of time in nanoseconds from issuing an activate command
151 # to the data being available in the row buffer for a read/write
152 tRCD = Param.Latency("RAS to CAS delay")
153
154 # the time from issuing a read/write command to seeing the actual data
155 tCL = Param.Latency("CAS latency")
156
157 # minimum time between a precharge and subsequent activate
158 tRP = Param.Latency("Row precharge time")
159
160 # minimum time between an activate and a precharge to the same row
161 tRAS = Param.Latency("ACT to PRE delay")
162
163 # minimum time between a write data transfer and a precharge
164 tWR = Param.Latency("Write recovery time")
165
166 # minimum time between a read and precharge command
167 tRTP = Param.Latency("Read to precharge")
168
169 # time to complete a burst transfer, typically the burst length
170 # divided by two due to the DDR bus, but by making it a parameter
171 # it is easier to also evaluate SDR memories like WideIO.
172 # This parameter has to account for burst length.
173 # Read/Write requests with data size larger than one full burst are broken
174 # down into multiple requests in the controller
175 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
176 # With bank group architectures, tBURST represents the CAS-to-CAS
177 # delay for bursts to different bank groups (tCCD_S)
178 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
179
180 # CAS-to-CAS delay for bursts to the same bank group
181 # only utilized with bank group architectures; set to 0 for default case
182 # tBURST is equivalent to tCCD_S; no explicit parameter required
183 # for CAS-to-CAS delay for bursts to different bank groups
184 tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
185
186 # time taken to complete one refresh cycle (N rows in all banks)
187 tRFC = Param.Latency("Refresh cycle time")
188
189 # refresh command interval, how often a "ref" command needs
190 # to be sent. It is 7.8 us for a 64ms refresh requirement
191 tREFI = Param.Latency("Refresh command interval")
192
193 # write-to-read, same rank turnaround penalty
194 tWTR = Param.Latency("Write to read, same rank switching time")
195
196 # read-to-write, same rank turnaround penalty
197 tRTW = Param.Latency("Read to write, same rank switching time")
198
199 # rank-to-rank bus delay penalty
200 # this does not correlate to a memory timing parameter and encompasses:
201 # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
202 # different rank bus delay
203 tCS = Param.Latency("Rank to rank switching time")
204
205 # minimum row activate to row activate delay time
206 tRRD = Param.Latency("ACT to ACT delay")
207
208 # only utilized with bank group architectures; set to 0 for default case
209 tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
210
211 # time window in which a maximum number of activates are allowed
212 # to take place, set to 0 to disable
213 tXAW = Param.Latency("X activation window")
214 activation_limit = Param.Unsigned("Max number of activates in window")
215
216 # time to exit power-down mode
217 # Exit power-down to next valid command delay
218 tXP = Param.Latency("0ns", "Power-up Delay")
219
220 # Exit Powerdown to commands requiring a locked DLL
221 tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
222
223 # time to exit self-refresh mode
224 tXS = Param.Latency("0ns", "Self-refresh exit latency")
225
226 # time to exit self-refresh mode with locked DLL
227 tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
228
229 # Currently rolled into other params
230 ######################################################################
231
232 # tRC - assumed to be tRAS + tRP
233
234 # Power Behaviour and Constraints
235 # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
236 # defined as VDD and VDD2. Each current is defined for each voltage domain
237 # separately. For example, current IDD0 is active-precharge current for
238 # voltage domain VDD and current IDD02 is active-precharge current for
239 # voltage domain VDD2.
240 # By default all currents are set to 0mA. Users who are only interested in
241 # the performance of DRAMs can leave them at 0.
242
243 # Operating 1 Bank Active-Precharge current
244 IDD0 = Param.Current("0mA", "Active precharge current")
245
246 # Operating 1 Bank Active-Precharge current multiple voltage Range
247 IDD02 = Param.Current("0mA", "Active precharge current VDD2")
248
249 # Precharge Power-down Current: Slow exit
250 IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
251
252 # Precharge Power-down Current: Slow exit multiple voltage Range
253 IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
254
255 # Precharge Power-down Current: Fast exit
256 IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
257
258 # Precharge Power-down Current: Fast exit multiple voltage Range
259 IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
260
261 # Precharge Standby current
262 IDD2N = Param.Current("0mA", "Precharge Standby current")
263
264 # Precharge Standby current multiple voltage range
265 IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
266
267 # Active Power-down current: slow exit
268 IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
269
270 # Active Power-down current: slow exit multiple voltage range
271 IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
272
273 # Active Power-down current : fast exit
274 IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
275
276 # Active Power-down current : fast exit multiple voltage range
277 IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
278
279 # Active Standby current
280 IDD3N = Param.Current("0mA", "Active Standby current")
281
282 # Active Standby current multiple voltage range
283 IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
284
285 # Burst Read Operating Current
286 IDD4R = Param.Current("0mA", "READ current")
287
288 # Burst Read Operating Current multiple voltage range
289 IDD4R2 = Param.Current("0mA", "READ current VDD2")
290
291 # Burst Write Operating Current
292 IDD4W = Param.Current("0mA", "WRITE current")
293
294 # Burst Write Operating Current multiple voltage range
295 IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
296
297 # Refresh Current
298 IDD5 = Param.Current("0mA", "Refresh current")
299
300 # Refresh Current multiple voltage range
301 IDD52 = Param.Current("0mA", "Refresh current VDD2")
302
303 # Self-Refresh Current
304 IDD6 = Param.Current("0mA", "Self-refresh Current")
305
306 # Self-Refresh Current multiple voltage range
307 IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
308
309 # Main voltage range of the DRAM
310 VDD = Param.Voltage("0V", "Main Voltage Range")
311
312 # Second voltage range defined by some DRAMs
313 VDD2 = Param.Voltage("0V", "2nd Voltage Range")
314
315# A single DDR3-1600 x64 channel (one command and address bus), with
316# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
317# an 8x8 configuration.
318class DDR3_1600_8x8(DRAMCtrl):
319 # size of device in bytes
320 device_size = '512MB'
321
322 # 8x8 configuration, 8 devices each with an 8-bit interface
323 device_bus_width = 8
324
325 # DDR3 is a BL8 device
326 burst_length = 8
327
328 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
329 device_rowbuffer_size = '1kB'
330
331 # 8x8 configuration, so 8 devices
332 devices_per_rank = 8
333
334 # Use two ranks
335 ranks_per_channel = 2
336
337 # DDR3 has 8 banks in all configurations
338 banks_per_rank = 8
339
340 # 800 MHz
341 tCK = '1.25ns'
342
343 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
344 tBURST = '5ns'
345
346 # DDR3-1600 11-11-11
347 tRCD = '13.75ns'
348 tCL = '13.75ns'
349 tRP = '13.75ns'
350 tRAS = '35ns'
351 tRRD = '6ns'
352 tXAW = '30ns'
353 activation_limit = 4
354 tRFC = '260ns'
355
356 tWR = '15ns'
357
358 # Greater of 4 CK or 7.5 ns
359 tWTR = '7.5ns'
360
361 # Greater of 4 CK or 7.5 ns
362 tRTP = '7.5ns'
363
364 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
365 tRTW = '2.5ns'
366
367 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
368 tCS = '2.5ns'
369
370 # <=85C, half for >85C
371 tREFI = '7.8us'
372
373 # active powerdown and precharge powerdown exit time
374 tXP = '6ns'
375
376 # self refresh exit time
377 tXS = '270ns'
378
379 # Current values from datasheet Die Rev E,J
380 IDD0 = '55mA'
381 IDD2N = '32mA'
382 IDD3N = '38mA'
383 IDD4W = '125mA'
384 IDD4R = '157mA'
385 IDD5 = '235mA'
386 IDD3P1 = '38mA'
387 IDD2P1 = '32mA'
388 IDD6 = '20mA'
389 VDD = '1.5V'
390
391# A single HMC-2500 x32 model based on:
392# [1] DRAMSpec: a high-level DRAM bank modelling tool
393# developed at the University of Kaiserslautern. This high level tool
394# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
395# estimate the DRAM bank latency and power numbers.
396# [2] High performance AXI-4.0 based interconnect for extensible smart memory
397# cubes (E. Azarkhish et. al)
398# Assumed for the HMC model is a 30 nm technology node.
399# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
400# layers).
401# Each layer has 16 vaults and each vault consists of 2 banks per layer.
402# In order to be able to use the same controller used for 2D DRAM generations
403# for HMC, the following analogy is done:
404# Channel (DDR) => Vault (HMC)
405# device_size (DDR) => size of a single layer in a vault
406# ranks per channel (DDR) => number of layers
407# banks per rank (DDR) => banks per layer
408# devices per rank (DDR) => devices per layer ( 1 for HMC).
409# The parameters for which no input is available are inherited from the DDR3
410# configuration.
411# This configuration includes the latencies from the DRAM to the logic layer
412# of the HMC
413class HMC_2500_1x32(DDR3_1600_8x8):
414 # size of device
415 # two banks per device with each bank 4MB [2]
416 device_size = '8MB'
417
418 # 1x32 configuration, 1 device with 32 TSVs [2]
419 device_bus_width = 32
420
421 # HMC is a BL8 device [2]
422 burst_length = 8
423
424 # Each device has a page (row buffer) size of 256 bytes [2]
425 device_rowbuffer_size = '256B'
426
427 # 1x32 configuration, so 1 device [2]
428 devices_per_rank = 1
429
430 # 4 layers so 4 ranks [2]
431 ranks_per_channel = 4
432
433 # HMC has 2 banks per layer [2]
434 # Each layer represents a rank. With 4 layers and 8 banks in total, each
435 # layer has 2 banks; thus 2 banks per rank.
436 banks_per_rank = 2
437
438 # 1250 MHz [2]
439 tCK = '0.8ns'
440
441 # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
442 tBURST = '3.2ns'
443
444 # Values using DRAMSpec HMC model [1]
445 tRCD = '10.2ns'
446 tCL = '9.9ns'
447 tRP = '7.7ns'
448 tRAS = '21.6ns'
449
450 # tRRD depends on the power supply network for each vendor.
451 # We assume a tRRD of a double bank approach to be equal to 4 clock
452 # cycles (Assumption)
453 tRRD = '3.2ns'
454
455 # activation limit is set to 0 since there are only 2 banks per vault
456 # layer.
457 activation_limit = 0
458
459 # Values using DRAMSpec HMC model [1]
460 tRFC = '59ns'
461 tWR = '8ns'
462 tRTP = '4.9ns'
463
464 # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
465 # 0.8 ns (Assumption)
466 tCS = '0.8ns'
467
468 # Value using DRAMSpec HMC model [1]
469 tREFI = '3.9us'
470
471 # The default page policy in the vault controllers is simple closed page
472 # [2] nevertheless 'close' policy opens and closes the row multiple times
473 # for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
474 page_policy = 'close_adaptive'
475
476 # RoCoRaBaCh resembles the default address mapping in HMC
477 addr_mapping = 'RoCoRaBaCh'
478 min_writes_per_switch = 8
479
480 # These parameters do not directly correlate with buffer_size in real
481 # hardware. Nevertheless, their value has been tuned to achieve a
482 # bandwidth similar to the cycle-accurate model in [2]
483 write_buffer_size = 32
484 read_buffer_size = 32
485
486 # The static latency of the vault controllers is estimated to be smaller
487 # than a full DRAM channel controller
488 static_backend_latency='4ns'
489 static_frontend_latency='4ns'
490
491# A single DDR3-2133 x64 channel refining a selected subset of the
492# options for the DDR-1600 configuration, based on the same DDR3-1600
493# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
494# consistent across the two configurations.
495class DDR3_2133_8x8(DDR3_1600_8x8):
496 # 1066 MHz
497 tCK = '0.938ns'
498
499 # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
500 tBURST = '3.752ns'
501
502 # DDR3-2133 14-14-14
503 tRCD = '13.09ns'
504 tCL = '13.09ns'
505 tRP = '13.09ns'
506 tRAS = '33ns'
507 tRRD = '5ns'
508 tXAW = '25ns'
509
510 # Current values from datasheet
511 IDD0 = '70mA'
512 IDD2N = '37mA'
513 IDD3N = '44mA'
514 IDD4W = '157mA'
515 IDD4R = '191mA'
516 IDD5 = '250mA'
517 IDD3P1 = '44mA'
518 IDD2P1 = '43mA'
519 IDD6 ='20mA'
520 VDD = '1.5V'
521
522# A single DDR4-2400 x64 channel (one command and address bus), with
523# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
524# in an 16x4 configuration.
525# Total channel capacity is 32GB
526# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
527class DDR4_2400_16x4(DRAMCtrl):
528 # size of device
529 device_size = '1GB'
530
531 # 16x4 configuration, 16 devices each with a 4-bit interface
532 device_bus_width = 4
533
534 # DDR4 is a BL8 device
535 burst_length = 8
536
537 # Each device has a page (row buffer) size of 512 byte (1K columns x4)
538 device_rowbuffer_size = '512B'
539
540 # 16x4 configuration, so 16 devices
541 devices_per_rank = 16
542
543 # Match our DDR3 configurations which is dual rank
544 ranks_per_channel = 2
545
546 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
547 # Set to 4 for x4 case
548 bank_groups_per_rank = 4
549
550 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
551 # configurations). Currently we do not capture the additional
552 # constraints incurred by the bank groups
553 banks_per_rank = 16
554
555 # override the default buffer sizes and go for something larger to
556 # accommodate the larger bank count
557 write_buffer_size = 128
558 read_buffer_size = 64
559
560 # 1200 MHz
561 tCK = '0.833ns'
562
563 # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
564 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
565 # With bank group architectures, tBURST represents the CAS-to-CAS
566 # delay for bursts to different bank groups (tCCD_S)
567 tBURST = '3.332ns'
568
569 # @2400 data rate, tCCD_L is 6 CK
570 # CAS-to-CAS delay for bursts to the same bank group
571 # tBURST is equivalent to tCCD_S; no explicit parameter required
572 # for CAS-to-CAS delay for bursts to different bank groups
573 tCCD_L = '5ns';
574
575 # DDR4-2400 17-17-17
576 tRCD = '14.16ns'
577 tCL = '14.16ns'
578 tRP = '14.16ns'
579 tRAS = '32ns'
580
581 # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
582 tRRD = '3.332ns'
583
584 # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
585 tRRD_L = '4.9ns';
586
587 # tFAW for 512B page is MAX(16 CK, 13ns)
588 tXAW = '13.328ns'
589 activation_limit = 4
590 # tRFC is 350ns
591 tRFC = '350ns'
592
593 tWR = '15ns'
594
595 # Here using the average of WTR_S and WTR_L
596 tWTR = '5ns'
597
598 # Greater of 4 CK or 7.5 ns
599 tRTP = '7.5ns'
600
601 # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
602 tRTW = '1.666ns'
603
604 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
605 tCS = '1.666ns'
606
607 # <=85C, half for >85C
608 tREFI = '7.8us'
609
610 # active powerdown and precharge powerdown exit time
611 tXP = '6ns'
612
613 # self refresh exit time
614 # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
615 # tRFC + 10ns = 340ns
616 tXS = '340ns'
617
618 # Current values from datasheet
619 IDD0 = '43mA'
620 IDD02 = '3mA'
621 IDD2N = '34mA'
622 IDD3N = '38mA'
623 IDD3N2 = '3mA'
624 IDD4W = '103mA'
625 IDD4R = '110mA'
626 IDD5 = '250mA'
627 IDD3P1 = '32mA'
628 IDD2P1 = '25mA'
629 IDD6 = '30mA'
630 VDD = '1.2V'
631 VDD2 = '2.5V'
632
633# A single DDR4-2400 x64 channel (one command and address bus), with
634# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
635# in an 8x8 configuration.
636# Total channel capacity is 16GB
637# 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
638class DDR4_2400_8x8(DDR4_2400_16x4):
639 # 8x8 configuration, 8 devices each with an 8-bit interface
640 device_bus_width = 8
641
642 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
643 device_rowbuffer_size = '1kB'
644
645 # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
646 tRRD_L = '4.9ns';
647
648 tXAW = '21ns'
649
650 # Current values from datasheet
651 IDD0 = '48mA'
652 IDD3N = '43mA'
653 IDD4W = '123mA'
654 IDD4R = '135mA'
655 IDD3P1 = '37mA'
656
657# A single DDR4-2400 x64 channel (one command and address bus), with
658# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
659# in an 4x16 configuration.
660# Total channel capacity is 4GB
661# 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
662class DDR4_2400_4x16(DDR4_2400_16x4):
663 # 4x16 configuration, 4 devices each with an 16-bit interface
664 device_bus_width = 16
665
666 # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
667 device_rowbuffer_size = '2kB'
668
669 # 4x16 configuration, so 4 devices
670 devices_per_rank = 4
671
672 # Single rank for x16
673 ranks_per_channel = 1
674
675 # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
676 # Set to 2 for x16 case
677 bank_groups_per_rank = 2
678
679 # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
680 # configurations). Currently we do not capture the additional
681 # constraints incurred by the bank groups
682 banks_per_rank = 8
683
684 # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
685 tRRD = '5.3ns'
686
687 # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
688 tRRD_L = '6.4ns';
689
690 tXAW = '30ns'
691
692 # Current values from datasheet
693 IDD0 = '80mA'
694 IDD02 = '4mA'
695 IDD2N = '34mA'
696 IDD3N = '47mA'
697 IDD4W = '228mA'
698 IDD4R = '243mA'
699 IDD5 = '280mA'
700 IDD3P1 = '41mA'
701
702# A single LPDDR2-S4 x32 interface (one command/address bus), with
703# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
704# in a 1x32 configuration.
705class LPDDR2_S4_1066_1x32(DRAMCtrl):
706 # No DLL in LPDDR2
707 dll = False
708
709 # size of device
710 device_size = '512MB'
711
712 # 1x32 configuration, 1 device with a 32-bit interface
713 device_bus_width = 32
714
715 # LPDDR2_S4 is a BL4 and BL8 device
716 burst_length = 8
717
718 # Each device has a page (row buffer) size of 1KB
719 # (this depends on the memory density)
720 device_rowbuffer_size = '1kB'
721
722 # 1x32 configuration, so 1 device
723 devices_per_rank = 1
724
725 # Use a single rank
726 ranks_per_channel = 1
727
728 # LPDDR2-S4 has 8 banks in all configurations
729 banks_per_rank = 8
730
731 # 533 MHz
732 tCK = '1.876ns'
733
734 # Fixed at 15 ns
735 tRCD = '15ns'
736
737 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
738 tCL = '15ns'
739
740 # Pre-charge one bank 15 ns (all banks 18 ns)
741 tRP = '15ns'
742
743 tRAS = '42ns'
744 tWR = '15ns'
745
746 tRTP = '7.5ns'
747
748 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
749 # Note this is a BL8 DDR device.
750 # Requests larger than 32 bytes are broken down into multiple requests
751 # in the controller
752 tBURST = '7.5ns'
753
754 # LPDDR2-S4, 4 Gbit
755 tRFC = '130ns'
756 tREFI = '3.9us'
757
758 # active powerdown and precharge powerdown exit time
759 tXP = '7.5ns'
760
761 # self refresh exit time
762 tXS = '140ns'
763
764 # Irrespective of speed grade, tWTR is 7.5 ns
765 tWTR = '7.5ns'
766
767 # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
768 tRTW = '3.75ns'
769
770 # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
771 tCS = '3.75ns'
772
773 # Activate to activate irrespective of density and speed grade
774 tRRD = '10.0ns'
775
776 # Irrespective of density, tFAW is 50 ns
777 tXAW = '50ns'
778 activation_limit = 4
779
780 # Current values from datasheet
781 IDD0 = '15mA'
782 IDD02 = '70mA'
783 IDD2N = '2mA'
784 IDD2N2 = '30mA'
785 IDD3N = '2.5mA'
786 IDD3N2 = '30mA'
787 IDD4W = '10mA'
788 IDD4W2 = '190mA'
789 IDD4R = '3mA'
790 IDD4R2 = '220mA'
791 IDD5 = '40mA'
792 IDD52 = '150mA'
793 IDD3P1 = '1.2mA'
794 IDD3P12 = '8mA'
795 IDD2P1 = '0.6mA'
796 IDD2P12 = '0.8mA'
797 IDD6 = '1mA'
798 IDD62 = '3.2mA'
799 VDD = '1.8V'
800 VDD2 = '1.2V'
801
802# A single WideIO x128 interface (one command and address bus), with
803# default timings based on an estimated WIO-200 8 Gbit part.
804class WideIO_200_1x128(DRAMCtrl):
805 # No DLL for WideIO
806 dll = False
807
808 # size of device
809 device_size = '1024MB'
810
811 # 1x128 configuration, 1 device with a 128-bit interface
812 device_bus_width = 128
813
814 # This is a BL4 device
815 burst_length = 4
816
817 # Each device has a page (row buffer) size of 4KB
818 # (this depends on the memory density)
819 device_rowbuffer_size = '4kB'
820
821 # 1x128 configuration, so 1 device
822 devices_per_rank = 1
823
824 # Use one rank for a one-high die stack
825 ranks_per_channel = 1
826
827 # WideIO has 4 banks in all configurations
828 banks_per_rank = 4
829
830 # 200 MHz
831 tCK = '5ns'
832
833 # WIO-200
834 tRCD = '18ns'
835 tCL = '18ns'
836 tRP = '18ns'
837 tRAS = '42ns'
838 tWR = '15ns'
839 # Read to precharge is same as the burst
840 tRTP = '20ns'
841
842 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
843 # Note this is a BL4 SDR device.
844 tBURST = '20ns'
845
846 # WIO 8 Gb
847 tRFC = '210ns'
848
849 # WIO 8 Gb, <=85C, half for >85C
850 tREFI = '3.9us'
851
852 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
853 tWTR = '15ns'
854
855 # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
856 tRTW = '10ns'
857
858 # Default different rank bus delay to 2 CK, @200 MHz = 10 ns
859 tCS = '10ns'
860
861 # Activate to activate irrespective of density and speed grade
862 tRRD = '10.0ns'
863
864 # Two instead of four activation window
865 tXAW = '50ns'
866 activation_limit = 2
867
868 # The WideIO specification does not provide current information
869
870# A single LPDDR3 x32 interface (one command/address bus), with
871# default timings based on a LPDDR3-1600 4 Gbit part (Micron
872# EDF8132A1MC) in a 1x32 configuration.
873class LPDDR3_1600_1x32(DRAMCtrl):
874 # No DLL for LPDDR3
875 dll = False
876
877 # size of device
878 device_size = '512MB'
879
880 # 1x32 configuration, 1 device with a 32-bit interface
881 device_bus_width = 32
882
883 # LPDDR3 is a BL8 device
884 burst_length = 8
885
886 # Each device has a page (row buffer) size of 4KB
887 device_rowbuffer_size = '4kB'
888
889 # 1x32 configuration, so 1 device
890 devices_per_rank = 1
891
892 # Technically the datasheet is a dual-rank package, but for
893 # comparison with the LPDDR2 config we stick to a single rank
894 ranks_per_channel = 1
895
896 # LPDDR3 has 8 banks in all configurations
897 banks_per_rank = 8
898
899 # 800 MHz
900 tCK = '1.25ns'
901
902 tRCD = '18ns'
903
904 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
905 tCL = '15ns'
906
907 tRAS = '42ns'
908 tWR = '15ns'
909
910 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
911 tRTP = '7.5ns'
912
913 # Pre-charge one bank 18 ns (all banks 21 ns)
914 tRP = '18ns'
915
916 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
917 # Note this is a BL8 DDR device.
918 # Requests larger than 32 bytes are broken down into multiple requests
919 # in the controller
920 tBURST = '5ns'
921
922 # LPDDR3, 4 Gb
923 tRFC = '130ns'
924 tREFI = '3.9us'
925
926 # active powerdown and precharge powerdown exit time
927 tXP = '7.5ns'
928
929 # self refresh exit time
930 tXS = '140ns'
931
932 # Irrespective of speed grade, tWTR is 7.5 ns
933 tWTR = '7.5ns'
934
935 # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
936 tRTW = '2.5ns'
937
938 # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
939 tCS = '2.5ns'
940
941 # Activate to activate irrespective of density and speed grade
942 tRRD = '10.0ns'
943
944 # Irrespective of size, tFAW is 50 ns
945 tXAW = '50ns'
946 activation_limit = 4
947
948 # Current values from datasheet
949 IDD0 = '8mA'
950 IDD02 = '60mA'
951 IDD2N = '0.8mA'
952 IDD2N2 = '26mA'
953 IDD3N = '2mA'
954 IDD3N2 = '34mA'
955 IDD4W = '2mA'
956 IDD4W2 = '190mA'
957 IDD4R = '2mA'
958 IDD4R2 = '230mA'
959 IDD5 = '28mA'
960 IDD52 = '150mA'
961 IDD3P1 = '1.4mA'
962 IDD3P12 = '11mA'
963 IDD2P1 = '0.8mA'
964 IDD2P12 = '1.8mA'
965 IDD6 = '0.5mA'
966 IDD62 = '1.8mA'
967 VDD = '1.8V'
968 VDD2 = '1.2V'
969
970# A single GDDR5 x64 interface, with
971# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
972# H5GQ1H24AFR) in a 2x32 configuration.
973class GDDR5_4000_2x32(DRAMCtrl):
974 # size of device
975 device_size = '128MB'
976
977 # 2x32 configuration, 1 device with a 32-bit interface
978 device_bus_width = 32
979
980 # GDDR5 is a BL8 device
981 burst_length = 8
982
983 # Each device has a page (row buffer) size of 2Kbits (256Bytes)
984 device_rowbuffer_size = '256B'
985
986 # 2x32 configuration, so 2 devices
987 devices_per_rank = 2
988
989 # assume single rank
990 ranks_per_channel = 1
991
992 # GDDR5 has 4 bank groups
993 bank_groups_per_rank = 4
994
995 # GDDR5 has 16 banks with 4 bank groups
996 banks_per_rank = 16
997
998 # 1000 MHz
999 tCK = '1ns'
1000
1001 # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
1002 # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
1003 # 8 beats at 4000 MHz = 2 beats at 1000 MHz
1004 # tBURST is equivalent to the CAS-to-CAS delay (tCCD)
1005 # With bank group architectures, tBURST represents the CAS-to-CAS
1006 # delay for bursts to different bank groups (tCCD_S)
1007 tBURST = '2ns'
1008
1009 # @1000MHz data rate, tCCD_L is 3 CK
1010 # CAS-to-CAS delay for bursts to the same bank group
1011 # tBURST is equivalent to tCCD_S; no explicit parameter required
1012 # for CAS-to-CAS delay for bursts to different bank groups
1013 tCCD_L = '3ns';
1014
1015 tRCD = '12ns'
1016
1017 # tCL is not directly found in datasheet and assumed equal tRCD
1018 tCL = '12ns'
1019
1020 tRP = '12ns'
1021 tRAS = '28ns'
1022
1023 # RRD_S (different bank group)
1024 # RRD_S is 5.5 ns in datasheet.
1025 # rounded to the next multiple of tCK
1026 tRRD = '6ns'
1027
1028 # RRD_L (same bank group)
1029 # RRD_L is 5.5 ns in datasheet.
1030 # rounded to the next multiple of tCK
1031 tRRD_L = '6ns'
1032
1033 tXAW = '23ns'
1034
1035 # tXAW < 4 x tRRD.
1036 # Therefore, activation limit is set to 0
1037 activation_limit = 0
1038
1039 tRFC = '65ns'
1040 tWR = '12ns'
1041
1042 # Here using the average of WTR_S and WTR_L
1043 tWTR = '5ns'
1044
1045 # Read-to-Precharge 2 CK
1046 tRTP = '2ns'
1047
1048 # Assume 2 cycles
1049 tRTW = '2ns'
1050
1051# A single HBM x128 interface (one command and address bus), with
1052# default timings based on data publically released
1053# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
1054# IDD measurement values, and by extrapolating data from other classes.
1055# Architecture values based on published HBM spec
1056# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
1057class HBM_1000_4H_1x128(DRAMCtrl):
1058 # HBM gen1 supports up to 8 128-bit physical channels
1059 # Configuration defines a single channel, with the capacity
1060 # set to (full_ stack_capacity / 8) based on 2Gb dies
1061 # To use all 8 channels, set 'channels' parameter to 8 in
1062 # system configuration
1063
1064 # 128-bit interface legacy mode
1065 device_bus_width = 128
1066
1067 # HBM supports BL4 and BL2 (legacy mode only)
1068 burst_length = 4
1069
1070 # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
1071 # with 8 channels, 128MB per channel
1072 device_size = '128MB'
1073
1074 device_rowbuffer_size = '2kB'
1075
1076 # 1x128 configuration
1077 devices_per_rank = 1
1078
1079 # HBM does not have a CS pin; set rank to 1
1080 ranks_per_channel = 1
1081
1082 # HBM has 8 or 16 banks depending on capacity
1083 # 2Gb dies have 8 banks
1084 banks_per_rank = 8
1085
1086 # depending on frequency, bank groups may be required
1087 # will always have 4 bank groups when enabled
1088 # current specifications do not define the minimum frequency for
1089 # bank group architecture
1090 # setting bank_groups_per_rank to 0 to disable until range is defined
1091 bank_groups_per_rank = 0
1092
1093 # 500 MHz for 1Gbps DDR data rate
1094 tCK = '2ns'
1095
1096 # use values from IDD measurement in JEDEC spec
1097 # use tRP value for tRCD and tCL similar to other classes
1098 tRP = '15ns'
1099 tRCD = '15ns'
1100 tCL = '15ns'
1101 tRAS = '33ns'
1102
1103 # BL2 and BL4 supported, default to BL4
1104 # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
1105 tBURST = '4ns'
1106
1107 # value for 2Gb device from JEDEC spec
1108 tRFC = '160ns'
1109
1110 # value for 2Gb device from JEDEC spec
1111 tREFI = '3.9us'
1112
1113 # extrapolate the following from LPDDR configs, using ns values
1114 # to minimize burst length, prefetch differences
1115 tWR = '18ns'
1116 tRTP = '7.5ns'
1117 tWTR = '10ns'
1118
1119 # start with 2 cycles turnaround, similar to other memory classes
1120 # could be more with variations across the stack
1121 tRTW = '4ns'
1122
1123 # single rank device, set to 0
1124 tCS = '0ns'
1125
1126 # from MemCon example, tRRD is 4ns with 2ns tCK
1127 tRRD = '4ns'
1128
1129 # from MemCon example, tFAW is 30ns with 2ns tCK
1130 tXAW = '30ns'
1131 activation_limit = 4
1132
1133 # 4tCK
1134 tXP = '8ns'
1135
1136 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1137 tXS = '168ns'
1138
1139# A single HBM x64 interface (one command and address bus), with
1140# default timings based on HBM gen1 and data publically released
1141# A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
1142# Note: This defines a pseudo-channel with a unique controller
1143# instantiated per pseudo-channel
1144# Stay at same IO rate (1Gbps) to maintain timing relationship with
1145# HBM gen1 class (HBM_1000_4H_x128) where possible
1146class HBM_1000_4H_1x64(HBM_1000_4H_1x128):
1147 # For HBM gen2 with pseudo-channel mode, configure 2X channels.
1148 # Configuration defines a single pseudo channel, with the capacity
1149 # set to (full_ stack_capacity / 16) based on 8Gb dies
1150 # To use all 16 pseudo channels, set 'channels' parameter to 16 in
1151 # system configuration
1152
1153 # 64-bit pseudo-channle interface
1154 device_bus_width = 64
1155
1156 # HBM pseudo-channel only supports BL4
1157 burst_length = 4
1158
1159 # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
1160 # with 16 channels, 256MB per channel
1161 device_size = '256MB'
1162
1163 # page size is halved with pseudo-channel; maintaining the same same number
1164 # of rows per pseudo-channel with 2X banks across 2 channels
1165 device_rowbuffer_size = '1kB'
1166
1167 # HBM has 8 or 16 banks depending on capacity
1168 # Starting with 4Gb dies, 16 banks are defined
1169 banks_per_rank = 16
1170
1171 # reset tRFC for larger, 8Gb device
1172 # use HBM1 4Gb value as a starting point
1173 tRFC = '260ns'
1174
1175 # start with tRFC + tXP -> 160ns + 8ns = 168ns
1176 tXS = '268ns'
1177 # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
1178 tCS = '2ns'
1179 tREFI = '3.9us'
1180
1181 # active powerdown and precharge powerdown exit time
1182 tXP = '10ns'
1183
1184 # self refresh exit time
1185 tXS = '65ns'