1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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343 tRTW = '1.666ns'
344
345 # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
346 tCS = '1.666ns'
347
348 # <=85C, half for >85C
349 tREFI = '7.8us'
350
351# A single LPDDR2-S4 x32 interface (one command/address bus), with
352# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32
353# configuration.
354class LPDDR2_S4_1066_x32(DRAMCtrl):
355 # 1x32 configuration, 1 device with a 32-bit interface
356 device_bus_width = 32
357
358 # LPDDR2_S4 is a BL4 and BL8 device

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