1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Thomas Grass
37# Andreas Hansson
38
39from m5.params import *
| 1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Thomas Grass
37# Andreas Hansson
38
39from m5.params import *
|
| 40from m5.proxy import *
|
40from MemObject import MemObject
| 41from MemObject import MemObject
|
| 42from System import System
|
41
42# The communication monitor will most typically be used in combination
43# with periodic dumping and resetting of stats using schedStatEvent
44class CommMonitor(MemObject):
45 type = 'CommMonitor'
46 cxx_header = "mem/comm_monitor.hh"
47
| 43
44# The communication monitor will most typically be used in combination
45# with periodic dumping and resetting of stats using schedStatEvent
46class CommMonitor(MemObject):
47 type = 'CommMonitor'
48 cxx_header = "mem/comm_monitor.hh"
49
|
| 50 system = Param.System(Parent.any, "System that the monitor belongs to.")
51
|
48 # one port in each direction
49 master = MasterPort("Master port")
50 slave = SlavePort("Slave port")
51
52 # packet trace output file, disabled by default
53 trace_file = Param.String("", "Packet trace output file")
54
55 # control the sample period window length of this monitor
56 sample_period = Param.Clock("1ms", "Sample period for histograms")
57
58 # for each histogram, set the number of bins and enable the user
59 # to disable the measurement, reads and writes use the same
60 # parameters
61
62 # histogram of burst length of packets (not using sample period)
63 burst_length_bins = Param.Unsigned('20', "# bins in burst length " \
64 "histograms")
65 disable_burst_length_hists = Param.Bool(False, "Disable burst length " \
66 "histograms")
67
68 # bandwidth per sample period
69 bandwidth_bins = Param.Unsigned('20', "# bins in bandwidth histograms")
70 disable_bandwidth_hists = Param.Bool(False, "Disable bandwidth histograms")
71
72 # latency from request to response (not using sample period)
73 latency_bins = Param.Unsigned('20', "# bins in latency histograms")
74 disable_latency_hists = Param.Bool(False, "Disable latency histograms")
75
76 # inter transaction time (ITT) distributions in uniformly sized
77 # bins up to the maximum, independently for read-to-read,
78 # write-to-write and the combined request-to-request that does not
79 # separate read and write requests
80 itt_bins = Param.Unsigned('20', "# bins in ITT distributions")
81 itt_max_bin = Param.Latency('100ns', "Max bin of ITT distributions")
82 disable_itt_dists = Param.Bool(False, "Disable ITT distributions")
83
84 # outstanding requests (that did not yet get a response) per
85 # sample period
86 outstanding_bins = Param.Unsigned('20', "# bins in outstanding " \
87 "requests histograms")
88 disable_outstanding_hists = Param.Bool(False, "Disable outstanding " \
89 "requests histograms")
90
91 # transactions (requests) observed per sample period
92 transaction_bins = Param.Unsigned('20', "# bins in transaction " \
93 "count histograms")
94 disable_transaction_hists = Param.Bool(False, "Disable transaction count " \
95 "histograms")
96
97 # address distributions (heatmaps) with associated address masks
98 # to selectively only look at certain bits of the address
99 read_addr_mask = Param.Addr(MaxAddr, "Address mask for read address")
100 write_addr_mask = Param.Addr(MaxAddr, "Address mask for write address")
101 disable_addr_dists = Param.Bool(True, "Disable address distributions")
| 52 # one port in each direction
53 master = MasterPort("Master port")
54 slave = SlavePort("Slave port")
55
56 # packet trace output file, disabled by default
57 trace_file = Param.String("", "Packet trace output file")
58
59 # control the sample period window length of this monitor
60 sample_period = Param.Clock("1ms", "Sample period for histograms")
61
62 # for each histogram, set the number of bins and enable the user
63 # to disable the measurement, reads and writes use the same
64 # parameters
65
66 # histogram of burst length of packets (not using sample period)
67 burst_length_bins = Param.Unsigned('20', "# bins in burst length " \
68 "histograms")
69 disable_burst_length_hists = Param.Bool(False, "Disable burst length " \
70 "histograms")
71
72 # bandwidth per sample period
73 bandwidth_bins = Param.Unsigned('20', "# bins in bandwidth histograms")
74 disable_bandwidth_hists = Param.Bool(False, "Disable bandwidth histograms")
75
76 # latency from request to response (not using sample period)
77 latency_bins = Param.Unsigned('20', "# bins in latency histograms")
78 disable_latency_hists = Param.Bool(False, "Disable latency histograms")
79
80 # inter transaction time (ITT) distributions in uniformly sized
81 # bins up to the maximum, independently for read-to-read,
82 # write-to-write and the combined request-to-request that does not
83 # separate read and write requests
84 itt_bins = Param.Unsigned('20', "# bins in ITT distributions")
85 itt_max_bin = Param.Latency('100ns', "Max bin of ITT distributions")
86 disable_itt_dists = Param.Bool(False, "Disable ITT distributions")
87
88 # outstanding requests (that did not yet get a response) per
89 # sample period
90 outstanding_bins = Param.Unsigned('20', "# bins in outstanding " \
91 "requests histograms")
92 disable_outstanding_hists = Param.Bool(False, "Disable outstanding " \
93 "requests histograms")
94
95 # transactions (requests) observed per sample period
96 transaction_bins = Param.Unsigned('20', "# bins in transaction " \
97 "count histograms")
98 disable_transaction_hists = Param.Bool(False, "Disable transaction count " \
99 "histograms")
100
101 # address distributions (heatmaps) with associated address masks
102 # to selectively only look at certain bits of the address
103 read_addr_mask = Param.Addr(MaxAddr, "Address mask for read address")
104 write_addr_mask = Param.Addr(MaxAddr, "Address mask for write address")
105 disable_addr_dists = Param.Bool(True, "Disable address distributions")
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