| Bridge.py (13665:9c7fe3811b88) | Bridge.py (13892:0182a0601f66) |
|---|---|
| 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 26 unchanged lines hidden (view full) --- 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Andreas Hansson 41 42from m5.params import * | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 26 unchanged lines hidden (view full) --- 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Andreas Hansson 41 42from m5.params import * |
| 43from m5.objects.MemObject import MemObject | 43from m5.objects.ClockedObject import ClockedObject |
| 44 | 44 |
| 45class Bridge(MemObject): | 45class Bridge(ClockedObject): |
| 46 type = 'Bridge' 47 cxx_header = "mem/bridge.hh" 48 slave = SlavePort('Slave port') 49 master = MasterPort('Master port') 50 req_size = Param.Unsigned(16, "The number of requests to buffer") 51 resp_size = Param.Unsigned(16, "The number of responses to buffer") 52 delay = Param.Latency('0ns', "The latency of this bridge") 53 ranges = VectorParam.AddrRange([AllMemory], 54 "Address ranges to pass through the bridge") | 46 type = 'Bridge' 47 cxx_header = "mem/bridge.hh" 48 slave = SlavePort('Slave port') 49 master = MasterPort('Master port') 50 req_size = Param.Unsigned(16, "The number of requests to buffer") 51 resp_size = Param.Unsigned(16, "The number of responses to buffer") 52 delay = Param.Latency('0ns', "The latency of this bridge") 53 ranges = VectorParam.AddrRange([AllMemory], 54 "Address ranges to pass through the bridge") |