1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 30 unchanged lines hidden (view full) --- 39# Authors: Ali Saidi 40# Andreas Hansson 41 42from m5.params import * 43from MemObject import MemObject 44 45class Bridge(MemObject): 46 type = 'Bridge' |
47 cxx_header = "mem/bridge.hh" |
48 slave = SlavePort('Slave port') 49 master = MasterPort('Master port') 50 req_size = Param.Int(16, "The number of requests to buffer") 51 resp_size = Param.Int(16, "The number of responses to buffer") 52 delay = Param.Latency('0ns', "The latency of this bridge") 53 ranges = VectorParam.AddrRange([AllMemory], 54 "Address ranges to pass through the bridge") |