simple_memobj.cc (12338:ae907b0a57c2) simple_memobj.cc (13784:1941dc118243)
1/*
2 * Copyright (c) 2017 Jason Lowe-Power
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 27 unchanged lines hidden (view full) ---

36 MemObject(params),
37 instPort(params->name + ".inst_port", this),
38 dataPort(params->name + ".data_port", this),
39 memPort(params->name + ".mem_side", this),
40 blocked(false)
41{
42}
43
1/*
2 * Copyright (c) 2017 Jason Lowe-Power
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 27 unchanged lines hidden (view full) ---

36 MemObject(params),
37 instPort(params->name + ".inst_port", this),
38 dataPort(params->name + ".data_port", this),
39 memPort(params->name + ".mem_side", this),
40 blocked(false)
41{
42}
43
44BaseMasterPort&
45SimpleMemobj::getMasterPort(const std::string& if_name, PortID idx)
44Port &
45SimpleMemobj::getPort(const std::string &if_name, PortID idx)
46{
47 panic_if(idx != InvalidPortID, "This object doesn't support vector ports");
48
49 // This is the name from the Python SimObject declaration (SimpleMemobj.py)
50 if (if_name == "mem_side") {
51 return memPort;
46{
47 panic_if(idx != InvalidPortID, "This object doesn't support vector ports");
48
49 // This is the name from the Python SimObject declaration (SimpleMemobj.py)
50 if (if_name == "mem_side") {
51 return memPort;
52 } else {
53 // pass it along to our super class
54 return MemObject::getMasterPort(if_name, idx);
55 }
56}
57
58BaseSlavePort&
59SimpleMemobj::getSlavePort(const std::string& if_name, PortID idx)
60{
61 panic_if(idx != InvalidPortID, "This object doesn't support vector ports");
62
63 // This is the name from the Python SimObject declaration in SimpleCache.py
64 if (if_name == "inst_port") {
52 } else if (if_name == "inst_port") {
65 return instPort;
66 } else if (if_name == "data_port") {
67 return dataPort;
68 } else {
69 // pass it along to our super class
53 return instPort;
54 } else if (if_name == "data_port") {
55 return dataPort;
56 } else {
57 // pass it along to our super class
70 return MemObject::getSlavePort(if_name, idx);
58 return MemObject::getPort(if_name, idx);
71 }
72}
73
74void
75SimpleMemobj::CPUSidePort::sendPacket(PacketPtr pkt)
76{
77 // Note: This flow control is very simple since the memobj is blocking.
78

--- 173 unchanged lines hidden --- 		59 }
60}
61
62void
63SimpleMemobj::CPUSidePort::sendPacket(PacketPtr pkt)
64{
65 // Note: This flow control is very simple since the memobj is blocking.
66

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