simple_cache.hh (13784:1941dc118243) simple_cache.hh (14252:1659a606447f)
1/*
2 * Copyright (c) 2017 Jason Lowe-Power
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Jason Lowe-Power
29 */
30
31#ifndef __LEARNING_GEM5_SIMPLE_CACHE_SIMPLE_CACHE_HH__
32#define __LEARNING_GEM5_SIMPLE_CACHE_SIMPLE_CACHE_HH__
33
34#include <unordered_map>
35
1/*
2 * Copyright (c) 2017 Jason Lowe-Power
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 19 unchanged lines hidden (view full) ---

28 * Authors: Jason Lowe-Power
29 */
30
31#ifndef __LEARNING_GEM5_SIMPLE_CACHE_SIMPLE_CACHE_HH__
32#define __LEARNING_GEM5_SIMPLE_CACHE_SIMPLE_CACHE_HH__
33
34#include <unordered_map>
35
36#include "mem/mem_object.hh"
36#include "base/statistics.hh"
37#include "mem/port.hh"
37#include "params/SimpleCache.hh"
38#include "params/SimpleCache.hh"
39#include "sim/clocked_object.hh"
38
39/**
40 * A very simple cache object. Has a fully-associative data store with random
41 * replacement.
42 * This cache is fully blocking (not non-blocking). Only a single request can
43 * be outstanding at a time.
44 * This cache is a writeback cache.
45 */
40
41/**
42 * A very simple cache object. Has a fully-associative data store with random
43 * replacement.
44 * This cache is fully blocking (not non-blocking). Only a single request can
45 * be outstanding at a time.
46 * This cache is a writeback cache.
47 */
46class SimpleCache : public MemObject
48class SimpleCache : public ClockedObject
47{
48 private:
49
50 /**
51 * Port on the CPU-side that receives requests.
52 * Mostly just forwards requests to the cache (owner)
53 */
54 class CPUSidePort : public SlavePort

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50 private:
51
52 /**
53 * Port on the CPU-side that receives requests.
54 * Mostly just forwards requests to the cache (owner)
55 */
56 class CPUSidePort : public SlavePort

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