simple_cache.cc (13841:8772d37d4bf6) simple_cache.cc (14252:1659a606447f)
1/*
2 * Copyright (c) 2017 Jason Lowe-Power
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30
31#include "learning_gem5/part2/simple_cache.hh"
32
33#include "base/random.hh"
34#include "debug/SimpleCache.hh"
35#include "sim/system.hh"
36
37SimpleCache::SimpleCache(SimpleCacheParams *params) :
1/*
2 * Copyright (c) 2017 Jason Lowe-Power
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30
31#include "learning_gem5/part2/simple_cache.hh"
32
33#include "base/random.hh"
34#include "debug/SimpleCache.hh"
35#include "sim/system.hh"
36
37SimpleCache::SimpleCache(SimpleCacheParams *params) :
38 MemObject(params),
38 ClockedObject(params),
39 latency(params->latency),
40 blockSize(params->system->cacheLineSize()),
41 capacity(params->size / blockSize),
42 memPort(params->name + ".mem_side", this),
43 blocked(false), originalPacket(nullptr), waitingPortId(-1)
44{
45 // Since the CPU side ports are a vector of ports, create an instance of
46 // the CPUSidePort for each connection. This member of params is

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59 panic_if(idx != InvalidPortID,
60 "Mem side of simple cache not a vector port");
61 return memPort;
62 } else if (if_name == "cpu_side" && idx < cpuPorts.size()) {
63 // We should have already created all of the ports in the constructor
64 return cpuPorts[idx];
65 } else {
66 // pass it along to our super class
39 latency(params->latency),
40 blockSize(params->system->cacheLineSize()),
41 capacity(params->size / blockSize),
42 memPort(params->name + ".mem_side", this),
43 blocked(false), originalPacket(nullptr), waitingPortId(-1)
44{
45 // Since the CPU side ports are a vector of ports, create an instance of
46 // the CPUSidePort for each connection. This member of params is

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59 panic_if(idx != InvalidPortID,
60 "Mem side of simple cache not a vector port");
61 return memPort;
62 } else if (if_name == "cpu_side" && idx < cpuPorts.size()) {
63 // We should have already created all of the ports in the constructor
64 return cpuPorts[idx];
65 } else {
66 // pass it along to our super class
67 return MemObject::getPort(if_name, idx);
67 return ClockedObject::getPort(if_name, idx);
68 }
69}
70
71void
72SimpleCache::CPUSidePort::sendPacket(PacketPtr pkt)
73{
74 // Note: This flow control is very simple since the cache is blocking.
75

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422 port.sendRangeChange();
423 }
424}
425
426void
427SimpleCache::regStats()
428{
429 // If you don't do this you get errors about uninitialized stats.
68 }
69}
70
71void
72SimpleCache::CPUSidePort::sendPacket(PacketPtr pkt)
73{
74 // Note: This flow control is very simple since the cache is blocking.
75

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422 port.sendRangeChange();
423 }
424}
425
426void
427SimpleCache::regStats()
428{
429 // If you don't do this you get errors about uninitialized stats.
430 MemObject::regStats();
430 ClockedObject::regStats();
431
432 hits.name(name() + ".hits")
433 .desc("Number of hits")
434 ;
435
436 misses.name(name() + ".misses")
437 .desc("Number of misses")
438 ;

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432 hits.name(name() + ".hits")
433 .desc("Number of hits")
434 ;
435
436 misses.name(name() + ".misses")
437 .desc("Number of misses")
438 ;

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