simple_cache.cc (12749:223c83ed9979) simple_cache.cc (13784:1941dc118243)
1/*
2 * Copyright (c) 2017 Jason Lowe-Power
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 37 unchanged lines hidden (view full) ---

46 // the CPUSidePort for each connection. This member of params is
47 // automatically created depending on the name of the vector port and
48 // holds the number of connections to this port name
49 for (int i = 0; i < params->port_cpu_side_connection_count; ++i) {
50 cpuPorts.emplace_back(name() + csprintf(".cpu_side[%d]", i), i, this);
51 }
52}
53
1/*
2 * Copyright (c) 2017 Jason Lowe-Power
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 37 unchanged lines hidden (view full) ---

46 // the CPUSidePort for each connection. This member of params is
47 // automatically created depending on the name of the vector port and
48 // holds the number of connections to this port name
49 for (int i = 0; i < params->port_cpu_side_connection_count; ++i) {
50 cpuPorts.emplace_back(name() + csprintf(".cpu_side[%d]", i), i, this);
51 }
52}
53
54BaseMasterPort&
55SimpleCache::getMasterPort(const std::string& if_name, PortID idx)
54Port &
55SimpleCache::getPort(const std::string &if_name, PortID idx)
56{
57 panic_if(idx != InvalidPortID, "This object doesn't support vector ports");
58
59 // This is the name from the Python SimObject declaration in SimpleCache.py
60 if (if_name == "mem_side") {
61 return memPort;
56{
57 panic_if(idx != InvalidPortID, "This object doesn't support vector ports");
58
59 // This is the name from the Python SimObject declaration in SimpleCache.py
60 if (if_name == "mem_side") {
61 return memPort;
62 } else {
63 // pass it along to our super class
64 return MemObject::getMasterPort(if_name, idx);
65 }
66}
67
68BaseSlavePort&
69SimpleCache::getSlavePort(const std::string& if_name, PortID idx)
70{
71 // This is the name from the Python SimObject declaration (SimpleMemobj.py)
72 if (if_name == "cpu_side" && idx < cpuPorts.size()) {
62 } else if (if_name == "cpu_side" && idx < cpuPorts.size()) {
73 // We should have already created all of the ports in the constructor
74 return cpuPorts[idx];
75 } else {
76 // pass it along to our super class
63 // We should have already created all of the ports in the constructor
64 return cpuPorts[idx];
65 } else {
66 // pass it along to our super class
77 return MemObject::getSlavePort(if_name, idx);
67 return MemObject::getPort(if_name, idx);
78 }
79}
80
81void
82SimpleCache::CPUSidePort::sendPacket(PacketPtr pkt)
83{
84 // Note: This flow control is very simple since the cache is blocking.
85

--- 383 unchanged lines hidden --- 		68 }
69}
70
71void
72SimpleCache::CPUSidePort::sendPacket(PacketPtr pkt)
73{
74 // Note: This flow control is very simple since the cache is blocking.
75

--- 383 unchanged lines hidden ---