54,55c54,55
< BaseMasterPort&
< SimpleCache::getMasterPort(const std::string& if_name, PortID idx)
---
> Port &
> SimpleCache::getPort(const std::string &if_name, PortID idx)
62,72c62
< } else {
< // pass it along to our super class
< return MemObject::getMasterPort(if_name, idx);
< }
< }
<
< BaseSlavePort&
< SimpleCache::getSlavePort(const std::string& if_name, PortID idx)
< {
< // This is the name from the Python SimObject declaration (SimpleMemobj.py)
< if (if_name == "cpu_side" && idx < cpuPorts.size()) {
---
> } else if (if_name == "cpu_side" && idx < cpuPorts.size()) {
77c67
< return MemObject::getSlavePort(if_name, idx);
---
> return MemObject::getPort(if_name, idx);