Cross Reference: /gem5/src/learning_gem5/part2/SimpleMemobj.py

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SimpleMemobj.py (13665:9c7fe3811b88)	SimpleMemobj.py (14252:1659a606447f)
1# -- coding: utf-8 -- 2# Copyright (c) 2017 Jason Lowe-Power 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 14 unchanged lines hidden (view full) --- 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Jason Lowe-Power 29 30from m5.params import *	1# -- coding: utf-8 -- 2# Copyright (c) 2017 Jason Lowe-Power 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 14 unchanged lines hidden (view full) --- 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Jason Lowe-Power 29 30from m5.params import *
31from m5.objects.MemObject import MemObject	31from m5.SimObject import SimObject
32	32
33class SimpleMemobj(MemObject):	33class SimpleMemobj(SimObject):
34 type = 'SimpleMemobj' 35 cxx_header = "learning_gem5/part2/simple_memobj.hh" 36 37 inst_port = SlavePort("CPU side port, receives requests") 38 data_port = SlavePort("CPU side port, receives requests") 39 mem_side = MasterPort("Memory side port, sends requests")	34 type = 'SimpleMemobj' 35 cxx_header = "learning_gem5/part2/simple_memobj.hh" 36 37 inst_port = SlavePort("CPU side port, receives requests") 38 data_port = SlavePort("CPU side port, receives requests") 39 mem_side = MasterPort("Memory side port, sends requests")