Cross Reference: /gem5/src/learning_gem5/part2/SimpleCache.py

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SimpleCache.py (13665:9c7fe3811b88)	SimpleCache.py (14252:1659a606447f)
1# -- coding: utf-8 -- 2# Copyright (c) 2017 Jason Lowe-Power 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Jason Lowe-Power 29 30from m5.params import * 31from m5.proxy import *	1# -- coding: utf-8 -- 2# Copyright (c) 2017 Jason Lowe-Power 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Jason Lowe-Power 29 30from m5.params import * 31from m5.proxy import *
32from m5.objects.MemObject import MemObject	32from m5.objects.ClockedObject import ClockedObject
33	33
34class SimpleCache(MemObject):	34class SimpleCache(ClockedObject):
35 type = 'SimpleCache' 36 cxx_header = "learning_gem5/part2/simple_cache.hh" 37 38 # Vector port example. Both the instruction and data ports connect to this 39 # port which is automatically split out into two ports. 40 cpu_side = VectorSlavePort("CPU side port, receives requests") 41 mem_side = MasterPort("Memory side port, sends requests") 42 43 latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss") 44 45 size = Param.MemorySize('16kB', "The size of the cache") 46 47 system = Param.System(Parent.any, "The system this cache is part of")	35 type = 'SimpleCache' 36 cxx_header = "learning_gem5/part2/simple_cache.hh" 37 38 # Vector port example. Both the instruction and data ports connect to this 39 # port which is automatically split out into two ports. 40 cpu_side = VectorSlavePort("CPU side port, receives requests") 41 mem_side = MasterPort("Memory side port, sends requests") 42 43 latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss") 44 45 size = Param.MemorySize('16kB', "The size of the cache") 46 47 system = Param.System(Parent.any, "The system this cache is part of")