1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Lisa Hsu
29 * Nathan Binkert
30 */
31
32#include "cpu/base.hh"
33#include "cpu/cpu_exec_context.hh"
34#include "kern/kernel_stats.hh"
35#include "kern/system_events.hh"
36#include "sim/system.hh"
37
38using namespace TheISA;
39
40void
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Lisa Hsu
29 * Nathan Binkert
30 */
31
32#include "cpu/base.hh"
33#include "cpu/cpu_exec_context.hh"
34#include "kern/kernel_stats.hh"
35#include "kern/system_events.hh"
36#include "sim/system.hh"
37
38using namespace TheISA;
39
40void
|
41SkipFuncEvent::process(ExecContext *xc)
| 41SkipFuncEvent::process(ThreadContext *tc)
|
42{
| 42{
|
43 Addr newpc = xc->readIntReg(ReturnAddressReg);
| 43 Addr newpc = tc->readIntReg(ReturnAddressReg);
|
44
45 DPRINTF(PCEvent, "skipping %s: pc=%x, newpc=%x\n", description,
| 44
45 DPRINTF(PCEvent, "skipping %s: pc=%x, newpc=%x\n", description,
|
46 xc->readPC(), newpc);
| 46 tc->readPC(), newpc);
|
47
| 47
|
48 xc->setPC(newpc);
49 xc->setNextPC(xc->readPC() + sizeof(TheISA::MachInst));
| 48 tc->setPC(newpc);
49 tc->setNextPC(tc->readPC() + sizeof(TheISA::MachInst));
|
50/*
| 50/*
|
51 BranchPred *bp = xc->getCpuPtr()->getBranchPred();
| 51 BranchPred *bp = tc->getCpuPtr()->getBranchPred();
|
52 if (bp != NULL) {
| 52 if (bp != NULL) {
|
53 bp->popRAS(xc->getThreadNum());
| 53 bp->popRAS(tc->getThreadNum());
|
54 }
55*/
56}
57
58
59FnEvent::FnEvent(PCEventQueue *q, const std::string &desc, Addr addr,
60 Stats::MainBin *bin)
61 : PCEvent(q, desc, addr), _name(desc), mybin(bin)
62{
63}
64
65void
| 54 }
55*/
56}
57
58
59FnEvent::FnEvent(PCEventQueue *q, const std::string &desc, Addr addr,
60 Stats::MainBin *bin)
61 : PCEvent(q, desc, addr), _name(desc), mybin(bin)
62{
63}
64
65void
|
66FnEvent::process(ExecContext *xc)
| 66FnEvent::process(ThreadContext *tc)
|
67{
| 67{
|
68 if (xc->misspeculating())
| 68 if (tc->misspeculating())
|
69 return;
70
| 69 return;
70
|
71 xc->getSystemPtr()->kernelBinning->call(xc, mybin);
| 71 tc->getSystemPtr()->kernelBinning->call(tc, mybin);
|
72}
73
74void
| 72}
73
74void
|
75IdleStartEvent::process(ExecContext *xc)
| 75IdleStartEvent::process(ThreadContext *tc)
|
76{
| 76{
|
77 if (xc->getKernelStats())
78 xc->getKernelStats()->setIdleProcess(
79 xc->readMiscReg(AlphaISA::IPR_PALtemp23), xc);
| 77 if (tc->getKernelStats())
78 tc->getKernelStats()->setIdleProcess(
79 tc->readMiscReg(AlphaISA::IPR_PALtemp23), tc);
|
80 remove();
81}
82
83void
| 80 remove();
81}
82
83void
|
84InterruptStartEvent::process(ExecContext *xc)
| 84InterruptStartEvent::process(ThreadContext *tc)
|
85{
| 85{
|
86 if (xc->getKernelStats())
87 xc->getKernelStats()->mode(Kernel::interrupt, xc);
| 86 if (tc->getKernelStats())
87 tc->getKernelStats()->mode(Kernel::interrupt, tc);
|
88}
89
90void
| 88}
89
90void
|
91InterruptEndEvent::process(ExecContext *xc)
| 91InterruptEndEvent::process(ThreadContext *tc)
|
92{
93 // We go back to kernel, if we are user, inside the rti
94 // pal code we will get switched to user because of the ICM write
| 92{
93 // We go back to kernel, if we are user, inside the rti
94 // pal code we will get switched to user because of the ICM write
|
95 if (xc->getKernelStats())
96 xc->getKernelStats()->mode(Kernel::kernel, xc);
| 95 if (tc->getKernelStats())
96 tc->getKernelStats()->mode(Kernel::kernel, tc);
|
97}
| 97}
|