1/*
2 * Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

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42#include <stack>
43#include <vector>
44
45#include "base/misc.hh"
46#include "base/types.hh"
47#include "gpu-compute/condition_register_state.hh"
48#include "gpu-compute/lds_state.hh"
49#include "gpu-compute/misc.hh"
50#include "params/Wavefront.hh"
51#include "sim/sim_object.hh"
52
53static const int MAX_NUM_INSTS_PER_WF = 12;
54
55/**
56 * A reconvergence stack entry conveys the necessary state to implement
57 * control flow divergence.

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184 bool isOldestInstPrivMem();
185 bool isOldestInstFlatMem();
186 bool isOldestInstALU();
187 bool isOldestInstBarrier();
188 // used for passing spill address to DDInstGPU
189 std::vector<Addr> lastAddr;
190 std::vector<uint32_t> workItemId[3];
191 std::vector<uint32_t> workItemFlatId;
192 uint32_t workGroupId[3];
193 uint32_t workGroupSz[3];
194 uint32_t gridSz[3];
195 uint32_t wgId;
196 uint32_t wgSz;
197 // wavefront id within a workgroup
198 uint32_t wfId;
199 uint32_t maxDynWaveId;
200 uint32_t dispatchId;
201 // outstanding global+local memory requests
202 uint32_t outstandingReqs;
203 // memory requests between scoreboard
204 // and execute stage not yet executed

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