wavefront.cc (11534:7106f550afad) wavefront.cc (11639:2e8d4bd8108d)
1/*
2 * Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

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47WavefrontParams::create()
48{
49 return new Wavefront(this);
50}
51
52Wavefront::Wavefront(const Params *p)
53 : SimObject(p), callArgMem(nullptr)
54{
1/*
2 * Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

--- 38 unchanged lines hidden (view full) ---

47WavefrontParams::create()
48{
49 return new Wavefront(this);
50}
51
52Wavefront::Wavefront(const Params *p)
53 : SimObject(p), callArgMem(nullptr)
54{
55 last_trace = 0;
55 lastTrace = 0;
56 simdId = p->simdId;
57 wfSlotId = p->wf_slot_id;
58 status = S_STOPPED;
59 reservedVectorRegs = 0;
60 startVgprIndex = 0;
56 simdId = p->simdId;
57 wfSlotId = p->wf_slot_id;
58 status = S_STOPPED;
59 reservedVectorRegs = 0;
60 startVgprIndex = 0;
61 outstanding_reqs = 0;
62 mem_reqs_in_pipe = 0;
63 outstanding_reqs_wr_gm = 0;
64 outstanding_reqs_wr_lm = 0;
65 outstanding_reqs_rd_gm = 0;
66 outstanding_reqs_rd_lm = 0;
67 rd_lm_reqs_in_pipe = 0;
68 rd_gm_reqs_in_pipe = 0;
69 wr_lm_reqs_in_pipe = 0;
70 wr_gm_reqs_in_pipe = 0;
61 outstandingReqs = 0;
62 memReqsInPipe = 0;
63 outstandingReqsWrGm = 0;
64 outstandingReqsWrLm = 0;
65 outstandingReqsRdGm = 0;
66 outstandingReqsRdLm = 0;
67 rdLmReqsInPipe = 0;
68 rdGmReqsInPipe = 0;
69 wrLmReqsInPipe = 0;
70 wrGmReqsInPipe = 0;
71
71
72 barrier_cnt = 0;
73 old_barrier_cnt = 0;
72 barrierCnt = 0;
73 oldBarrierCnt = 0;
74 stalledAtBarrier = false;
75
74 stalledAtBarrier = false;
75
76 mem_trace_busy = 0;
77 old_vgpr_tcnt = 0xffffffffffffffffll;
78 old_dgpr_tcnt = 0xffffffffffffffffll;
79 old_vgpr.resize(p->wfSize);
76 memTraceBusy = 0;
77 oldVgprTcnt = 0xffffffffffffffffll;
78 oldDgprTcnt = 0xffffffffffffffffll;
79 oldVgpr.resize(p->wfSize);
80
81 pendingFetch = false;
82 dropFetch = false;
83 condRegState = new ConditionRegisterState();
84 maxSpVgprs = 0;
85 maxDpVgprs = 0;
80
81 pendingFetch = false;
82 dropFetch = false;
83 condRegState = new ConditionRegisterState();
84 maxSpVgprs = 0;
85 maxDpVgprs = 0;
86 last_addr.resize(p->wfSize);
87 workitemFlatId.resize(p->wfSize);
88 old_dgpr.resize(p->wfSize);
89 bar_cnt.resize(p->wfSize);
86 lastAddr.resize(p->wfSize);
87 workItemFlatId.resize(p->wfSize);
88 oldDgpr.resize(p->wfSize);
89 barCnt.resize(p->wfSize);
90 for (int i = 0; i < 3; ++i) {
90 for (int i = 0; i < 3; ++i) {
91 workitemid[i].resize(p->wfSize);
91 workItemId[i].resize(p->wfSize);
92 }
93}
94
95void
96Wavefront::regStats()
97{
98 SimObject::regStats();
99

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153 delete callArgMem;
154 delete condRegState;
155}
156
157void
158Wavefront::start(uint64_t _wfDynId,uint64_t _base_ptr)
159{
160 wfDynId = _wfDynId;
92 }
93}
94
95void
96Wavefront::regStats()
97{
98 SimObject::regStats();
99

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153 delete callArgMem;
154 delete condRegState;
155}
156
157void
158Wavefront::start(uint64_t _wfDynId,uint64_t _base_ptr)
159{
160 wfDynId = _wfDynId;
161 base_ptr = _base_ptr;
161 basePtr = _base_ptr;
162 status = S_RUNNING;
163}
164
165bool
166Wavefront::isGmInstruction(GPUDynInstPtr ii)
167{
168 if (IS_OT_READ_PM(ii->opType()) || IS_OT_WRITE_PM(ii->opType()) ||
169 IS_OT_ATOMIC_PM(ii->opType())) {

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328 // Check to make sure wave is running
329 if (status == S_STOPPED || status == S_RETURNING ||
330 instructionBuffer.empty()) {
331 return 0;
332 }
333
334 // Is the wave waiting at a barrier
335 if (stalledAtBarrier) {
162 status = S_RUNNING;
163}
164
165bool
166Wavefront::isGmInstruction(GPUDynInstPtr ii)
167{
168 if (IS_OT_READ_PM(ii->opType()) || IS_OT_WRITE_PM(ii->opType()) ||
169 IS_OT_ATOMIC_PM(ii->opType())) {

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328 // Check to make sure wave is running
329 if (status == S_STOPPED || status == S_RETURNING ||
330 instructionBuffer.empty()) {
331 return 0;
332 }
333
334 // Is the wave waiting at a barrier
335 if (stalledAtBarrier) {
336 if (!computeUnit->AllAtBarrier(barrier_id,barrier_cnt,
337 computeUnit->getRefCounter(dispatchid, wg_id))) {
336 if (!computeUnit->AllAtBarrier(barrierId,barrierCnt,
337 computeUnit->getRefCounter(dispatchId, wgId))) {
338 // Are all threads at barrier?
339 return 0;
340 }
338 // Are all threads at barrier?
339 return 0;
340 }
341 old_barrier_cnt = barrier_cnt;
341 oldBarrierCnt = barrierCnt;
342 stalledAtBarrier = false;
343 }
344
345 // Read instruction
346 GPUDynInstPtr ii = instructionBuffer.front();
347
348 bool ready_inst M5_VAR_USED = false;
349 bool glbMemBusRdy = false;

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390 if (type == I_ALU && ii->opType() == Enums::OT_BARRIER) {
391 // Here for ALU instruction (barrier)
392 if (!computeUnit->wfWait[simdId].prerdy()) {
393 // Is wave slot free?
394 return 0;
395 }
396
397 // Are there in pipe or outstanding memory requests?
342 stalledAtBarrier = false;
343 }
344
345 // Read instruction
346 GPUDynInstPtr ii = instructionBuffer.front();
347
348 bool ready_inst M5_VAR_USED = false;
349 bool glbMemBusRdy = false;

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390 if (type == I_ALU && ii->opType() == Enums::OT_BARRIER) {
391 // Here for ALU instruction (barrier)
392 if (!computeUnit->wfWait[simdId].prerdy()) {
393 // Is wave slot free?
394 return 0;
395 }
396
397 // Are there in pipe or outstanding memory requests?
398 if ((outstanding_reqs + mem_reqs_in_pipe) > 0) {
398 if ((outstandingReqs + memReqsInPipe) > 0) {
399 return 0;
400 }
401
402 ready_inst = true;
403 } else if (type == I_ALU && ii->opType() == Enums::OT_NOP) {
404 // Here for ALU instruction (nop)
405 if (!computeUnit->wfWait[simdId].prerdy()) {
406 // Is wave slot free?

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411 } else if (type == I_ALU && ii->opType() == Enums::OT_RET) {
412 // Here for ALU instruction (return)
413 if (!computeUnit->wfWait[simdId].prerdy()) {
414 // Is wave slot free?
415 return 0;
416 }
417
418 // Are there in pipe or outstanding memory requests?
399 return 0;
400 }
401
402 ready_inst = true;
403 } else if (type == I_ALU && ii->opType() == Enums::OT_NOP) {
404 // Here for ALU instruction (nop)
405 if (!computeUnit->wfWait[simdId].prerdy()) {
406 // Is wave slot free?

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411 } else if (type == I_ALU && ii->opType() == Enums::OT_RET) {
412 // Here for ALU instruction (return)
413 if (!computeUnit->wfWait[simdId].prerdy()) {
414 // Is wave slot free?
415 return 0;
416 }
417
418 // Are there in pipe or outstanding memory requests?
419 if ((outstanding_reqs + mem_reqs_in_pipe) > 0) {
419 if ((outstandingReqs + memReqsInPipe) > 0) {
420 return 0;
421 }
422
423 ready_inst = true;
424 } else if (type == I_ALU && (ii->opType() == Enums::OT_BRANCH ||
425 ii->opType() == Enums::OT_ALU || IS_OT_LDAS(ii->opType()) ||
426 ii->opType() == Enums::OT_KERN_READ ||
427 ii->opType() == Enums::OT_ARG)) {

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439 return 0;
440 }
441 ready_inst = true;
442 } else if (type == I_GLOBAL && (IS_OT_READ_GM(ii->opType()) ||
443 IS_OT_WRITE_GM(ii->opType()) || IS_OT_ATOMIC_GM(ii->opType()))) {
444 // Here Global memory instruction
445 if (IS_OT_READ_GM(ii->opType()) || IS_OT_ATOMIC_GM(ii->opType())) {
446 // Are there in pipe or outstanding global memory write requests?
420 return 0;
421 }
422
423 ready_inst = true;
424 } else if (type == I_ALU && (ii->opType() == Enums::OT_BRANCH ||
425 ii->opType() == Enums::OT_ALU || IS_OT_LDAS(ii->opType()) ||
426 ii->opType() == Enums::OT_KERN_READ ||
427 ii->opType() == Enums::OT_ARG)) {

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439 return 0;
440 }
441 ready_inst = true;
442 } else if (type == I_GLOBAL && (IS_OT_READ_GM(ii->opType()) ||
443 IS_OT_WRITE_GM(ii->opType()) || IS_OT_ATOMIC_GM(ii->opType()))) {
444 // Here Global memory instruction
445 if (IS_OT_READ_GM(ii->opType()) || IS_OT_ATOMIC_GM(ii->opType())) {
446 // Are there in pipe or outstanding global memory write requests?
447 if ((outstanding_reqs_wr_gm + wr_gm_reqs_in_pipe) > 0) {
447 if ((outstandingReqsWrGm + wrGmReqsInPipe) > 0) {
448 return 0;
449 }
450 }
451
452 if (IS_OT_WRITE_GM(ii->opType()) || IS_OT_ATOMIC_GM(ii->opType()) ||
453 IS_OT_HIST_GM(ii->opType())) {
454 // Are there in pipe or outstanding global memory read requests?
448 return 0;
449 }
450 }
451
452 if (IS_OT_WRITE_GM(ii->opType()) || IS_OT_ATOMIC_GM(ii->opType()) ||
453 IS_OT_HIST_GM(ii->opType())) {
454 // Are there in pipe or outstanding global memory read requests?
455 if ((outstanding_reqs_rd_gm + rd_gm_reqs_in_pipe) > 0)
455 if ((outstandingReqsRdGm + rdGmReqsInPipe) > 0)
456 return 0;
457 }
458
459 if (!glbMemIssueRdy) {
460 // Is WV issue slot free?
461 return 0;
462 }
463
464 if (!glbMemBusRdy) {
465 // Is there an available VRF->Global memory read bus?
466 return 0;
467 }
468
469 if (!computeUnit->globalMemoryPipe.
456 return 0;
457 }
458
459 if (!glbMemIssueRdy) {
460 // Is WV issue slot free?
461 return 0;
462 }
463
464 if (!glbMemBusRdy) {
465 // Is there an available VRF->Global memory read bus?
466 return 0;
467 }
468
469 if (!computeUnit->globalMemoryPipe.
470 isGMReqFIFOWrRdy(rd_gm_reqs_in_pipe + wr_gm_reqs_in_pipe)) {
470 isGMReqFIFOWrRdy(rdGmReqsInPipe + wrGmReqsInPipe)) {
471 // Can we insert a new request to the Global Mem Request FIFO?
472 return 0;
473 }
474 // can we schedule source & destination operands on the VRF?
475 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii,
476 VrfAccessType::RD_WR)) {
477 return 0;
478 }
479 if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) {
480 return 0;
481 }
482 ready_inst = true;
483 } else if (type == I_SHARED && (IS_OT_READ_LM(ii->opType()) ||
484 IS_OT_WRITE_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType()))) {
485 // Here for Shared memory instruction
486 if (IS_OT_READ_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType())) {
471 // Can we insert a new request to the Global Mem Request FIFO?
472 return 0;
473 }
474 // can we schedule source & destination operands on the VRF?
475 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii,
476 VrfAccessType::RD_WR)) {
477 return 0;
478 }
479 if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) {
480 return 0;
481 }
482 ready_inst = true;
483 } else if (type == I_SHARED && (IS_OT_READ_LM(ii->opType()) ||
484 IS_OT_WRITE_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType()))) {
485 // Here for Shared memory instruction
486 if (IS_OT_READ_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType())) {
487 if ((outstanding_reqs_wr_lm + wr_lm_reqs_in_pipe) > 0) {
487 if ((outstandingReqsWrLm + wrLmReqsInPipe) > 0) {
488 return 0;
489 }
490 }
491
492 if (IS_OT_WRITE_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType()) ||
493 IS_OT_HIST_LM(ii->opType())) {
488 return 0;
489 }
490 }
491
492 if (IS_OT_WRITE_LM(ii->opType()) || IS_OT_ATOMIC_LM(ii->opType()) ||
493 IS_OT_HIST_LM(ii->opType())) {
494 if ((outstanding_reqs_rd_lm + rd_lm_reqs_in_pipe) > 0) {
494 if ((outstandingReqsRdLm + rdLmReqsInPipe) > 0) {
495 return 0;
496 }
497 }
498
499 if (!locMemBusRdy) {
500 // Is there an available VRF->LDS read bus?
501 return 0;
502 }
503 if (!locMemIssueRdy) {
504 // Is wave slot free?
505 return 0;
506 }
507
508 if (!computeUnit->localMemoryPipe.
495 return 0;
496 }
497 }
498
499 if (!locMemBusRdy) {
500 // Is there an available VRF->LDS read bus?
501 return 0;
502 }
503 if (!locMemIssueRdy) {
504 // Is wave slot free?
505 return 0;
506 }
507
508 if (!computeUnit->localMemoryPipe.
509 isLMReqFIFOWrRdy(rd_lm_reqs_in_pipe + wr_lm_reqs_in_pipe)) {
509 isLMReqFIFOWrRdy(rdLmReqsInPipe + wrLmReqsInPipe)) {
510 // Can we insert a new request to the LDS Request FIFO?
511 return 0;
512 }
513 // can we schedule source & destination operands on the VRF?
514 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii,
515 VrfAccessType::RD_WR)) {
516 return 0;
517 }
518 if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) {
519 return 0;
520 }
521 ready_inst = true;
522 } else if (type == I_PRIVATE && (IS_OT_READ_PM(ii->opType()) ||
523 IS_OT_WRITE_PM(ii->opType()) || IS_OT_ATOMIC_PM(ii->opType()))) {
524 // Here for Private memory instruction ------------------------ //
525 if (IS_OT_READ_PM(ii->opType()) || IS_OT_ATOMIC_PM(ii->opType())) {
510 // Can we insert a new request to the LDS Request FIFO?
511 return 0;
512 }
513 // can we schedule source & destination operands on the VRF?
514 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii,
515 VrfAccessType::RD_WR)) {
516 return 0;
517 }
518 if (!computeUnit->vrf[simdId]->operandsReady(this, ii)) {
519 return 0;
520 }
521 ready_inst = true;
522 } else if (type == I_PRIVATE && (IS_OT_READ_PM(ii->opType()) ||
523 IS_OT_WRITE_PM(ii->opType()) || IS_OT_ATOMIC_PM(ii->opType()))) {
524 // Here for Private memory instruction ------------------------ //
525 if (IS_OT_READ_PM(ii->opType()) || IS_OT_ATOMIC_PM(ii->opType())) {
526 if ((outstanding_reqs_wr_gm + wr_gm_reqs_in_pipe) > 0) {
526 if ((outstandingReqsWrGm + wrGmReqsInPipe) > 0) {
527 return 0;
528 }
529 }
530
531 if (IS_OT_WRITE_PM(ii->opType()) || IS_OT_ATOMIC_PM(ii->opType()) ||
532 IS_OT_HIST_PM(ii->opType())) {
527 return 0;
528 }
529 }
530
531 if (IS_OT_WRITE_PM(ii->opType()) || IS_OT_ATOMIC_PM(ii->opType()) ||
532 IS_OT_HIST_PM(ii->opType())) {
533 if ((outstanding_reqs_rd_gm + rd_gm_reqs_in_pipe) > 0) {
533 if ((outstandingReqsRdGm + rdGmReqsInPipe) > 0) {
534 return 0;
535 }
536 }
537
538 if (!glbMemBusRdy) {
539 // Is there an available VRF->Global memory read bus?
540 return 0;
541 }
542
543 if (!glbMemIssueRdy) {
544 // Is wave slot free?
545 return 0;
546 }
547
548 if (!computeUnit->globalMemoryPipe.
534 return 0;
535 }
536 }
537
538 if (!glbMemBusRdy) {
539 // Is there an available VRF->Global memory read bus?
540 return 0;
541 }
542
543 if (!glbMemIssueRdy) {
544 // Is wave slot free?
545 return 0;
546 }
547
548 if (!computeUnit->globalMemoryPipe.
549 isGMReqFIFOWrRdy(rd_gm_reqs_in_pipe + wr_gm_reqs_in_pipe)) {
549 isGMReqFIFOWrRdy(rdGmReqsInPipe + wrGmReqsInPipe)) {
550 // Can we insert a new request to the Global Mem Request FIFO?
551 return 0;
552 }
553 // can we schedule source & destination operands on the VRF?
554 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii,
555 VrfAccessType::RD_WR)) {
556 return 0;
557 }

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574 // Is wave slot free?
575 return 0;
576 }
577
578 if (!locMemIssueRdy) {
579 return 0;
580 }
581 if (!computeUnit->globalMemoryPipe.
550 // Can we insert a new request to the Global Mem Request FIFO?
551 return 0;
552 }
553 // can we schedule source & destination operands on the VRF?
554 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii,
555 VrfAccessType::RD_WR)) {
556 return 0;
557 }

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574 // Is wave slot free?
575 return 0;
576 }
577
578 if (!locMemIssueRdy) {
579 return 0;
580 }
581 if (!computeUnit->globalMemoryPipe.
582 isGMReqFIFOWrRdy(rd_gm_reqs_in_pipe + wr_gm_reqs_in_pipe)) {
582 isGMReqFIFOWrRdy(rdGmReqsInPipe + wrGmReqsInPipe)) {
583 // Can we insert a new request to the Global Mem Request FIFO?
584 return 0;
585 }
586
587 if (!computeUnit->localMemoryPipe.
583 // Can we insert a new request to the Global Mem Request FIFO?
584 return 0;
585 }
586
587 if (!computeUnit->localMemoryPipe.
588 isLMReqFIFOWrRdy(rd_lm_reqs_in_pipe + wr_lm_reqs_in_pipe)) {
588 isLMReqFIFOWrRdy(rdLmReqsInPipe + wrLmReqsInPipe)) {
589 // Can we insert a new request to the LDS Request FIFO?
590 return 0;
591 }
592 // can we schedule source & destination operands on the VRF?
593 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii,
594 VrfAccessType::RD_WR)) {
595 return 0;
596 }

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631 // this is to enforce a fixed number of cycles per issue slot per SIMD
632 computeUnit->wfWait[simdId].preset(computeUnit->shader->
633 ticks(computeUnit->issuePeriod));
634 } else if (ii->opType() == Enums::OT_BARRIER) {
635 computeUnit->wfWait[simdId].preset(computeUnit->shader->
636 ticks(computeUnit->issuePeriod));
637 } else if (ii->opType() == Enums::OT_FLAT_READ) {
638 assert(Enums::SC_NONE != ii->executedAs());
589 // Can we insert a new request to the LDS Request FIFO?
590 return 0;
591 }
592 // can we schedule source & destination operands on the VRF?
593 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii,
594 VrfAccessType::RD_WR)) {
595 return 0;
596 }

--- 34 unchanged lines hidden (view full) ---

631 // this is to enforce a fixed number of cycles per issue slot per SIMD
632 computeUnit->wfWait[simdId].preset(computeUnit->shader->
633 ticks(computeUnit->issuePeriod));
634 } else if (ii->opType() == Enums::OT_BARRIER) {
635 computeUnit->wfWait[simdId].preset(computeUnit->shader->
636 ticks(computeUnit->issuePeriod));
637 } else if (ii->opType() == Enums::OT_FLAT_READ) {
638 assert(Enums::SC_NONE != ii->executedAs());
639 mem_reqs_in_pipe++;
640 rd_gm_reqs_in_pipe++;
639 memReqsInPipe++;
640 rdGmReqsInPipe++;
641 if ( Enums::SC_SHARED == ii->executedAs() ) {
642 computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()].
643 preset(computeUnit->shader->ticks(4));
644 computeUnit->wfWait[computeUnit->ShrMemUnitId()].
645 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
646 } else {
647 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
648 preset(computeUnit->shader->ticks(4));
649 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
650 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
651 }
652 } else if (ii->opType() == Enums::OT_FLAT_WRITE) {
653 assert(Enums::SC_NONE != ii->executedAs());
641 if ( Enums::SC_SHARED == ii->executedAs() ) {
642 computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()].
643 preset(computeUnit->shader->ticks(4));
644 computeUnit->wfWait[computeUnit->ShrMemUnitId()].
645 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
646 } else {
647 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
648 preset(computeUnit->shader->ticks(4));
649 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
650 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
651 }
652 } else if (ii->opType() == Enums::OT_FLAT_WRITE) {
653 assert(Enums::SC_NONE != ii->executedAs());
654 mem_reqs_in_pipe++;
655 wr_gm_reqs_in_pipe++;
654 memReqsInPipe++;
655 wrGmReqsInPipe++;
656 if (Enums::SC_SHARED == ii->executedAs()) {
657 computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()].
658 preset(computeUnit->shader->ticks(8));
659 computeUnit->wfWait[computeUnit->ShrMemUnitId()].
660 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
661 } else {
662 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
663 preset(computeUnit->shader->ticks(8));
664 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
665 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
666 }
667 } else if (IS_OT_READ_GM(ii->opType())) {
656 if (Enums::SC_SHARED == ii->executedAs()) {
657 computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()].
658 preset(computeUnit->shader->ticks(8));
659 computeUnit->wfWait[computeUnit->ShrMemUnitId()].
660 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
661 } else {
662 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
663 preset(computeUnit->shader->ticks(8));
664 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
665 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
666 }
667 } else if (IS_OT_READ_GM(ii->opType())) {
668 mem_reqs_in_pipe++;
669 rd_gm_reqs_in_pipe++;
668 memReqsInPipe++;
669 rdGmReqsInPipe++;
670 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
671 preset(computeUnit->shader->ticks(4));
672 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
673 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
674 } else if (IS_OT_WRITE_GM(ii->opType())) {
670 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
671 preset(computeUnit->shader->ticks(4));
672 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
673 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
674 } else if (IS_OT_WRITE_GM(ii->opType())) {
675 mem_reqs_in_pipe++;
676 wr_gm_reqs_in_pipe++;
675 memReqsInPipe++;
676 wrGmReqsInPipe++;
677 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
678 preset(computeUnit->shader->ticks(8));
679 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
680 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
681 } else if (IS_OT_ATOMIC_GM(ii->opType())) {
677 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
678 preset(computeUnit->shader->ticks(8));
679 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
680 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
681 } else if (IS_OT_ATOMIC_GM(ii->opType())) {
682 mem_reqs_in_pipe++;
683 wr_gm_reqs_in_pipe++;
684 rd_gm_reqs_in_pipe++;
682 memReqsInPipe++;
683 wrGmReqsInPipe++;
684 rdGmReqsInPipe++;
685 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
686 preset(computeUnit->shader->ticks(8));
687 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
688 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
689 } else if (IS_OT_READ_LM(ii->opType())) {
685 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
686 preset(computeUnit->shader->ticks(8));
687 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
688 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
689 } else if (IS_OT_READ_LM(ii->opType())) {
690 mem_reqs_in_pipe++;
691 rd_lm_reqs_in_pipe++;
690 memReqsInPipe++;
691 rdLmReqsInPipe++;
692 computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()].
693 preset(computeUnit->shader->ticks(4));
694 computeUnit->wfWait[computeUnit->ShrMemUnitId()].
695 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
696 } else if (IS_OT_WRITE_LM(ii->opType())) {
692 computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()].
693 preset(computeUnit->shader->ticks(4));
694 computeUnit->wfWait[computeUnit->ShrMemUnitId()].
695 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
696 } else if (IS_OT_WRITE_LM(ii->opType())) {
697 mem_reqs_in_pipe++;
698 wr_lm_reqs_in_pipe++;
697 memReqsInPipe++;
698 wrLmReqsInPipe++;
699 computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()].
700 preset(computeUnit->shader->ticks(8));
701 computeUnit->wfWait[computeUnit->ShrMemUnitId()].
702 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
703 } else if (IS_OT_ATOMIC_LM(ii->opType())) {
699 computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()].
700 preset(computeUnit->shader->ticks(8));
701 computeUnit->wfWait[computeUnit->ShrMemUnitId()].
702 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
703 } else if (IS_OT_ATOMIC_LM(ii->opType())) {
704 mem_reqs_in_pipe++;
705 wr_lm_reqs_in_pipe++;
706 rd_lm_reqs_in_pipe++;
704 memReqsInPipe++;
705 wrLmReqsInPipe++;
706 rdLmReqsInPipe++;
707 computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()].
708 preset(computeUnit->shader->ticks(8));
709 computeUnit->wfWait[computeUnit->ShrMemUnitId()].
710 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
711 } else if (IS_OT_READ_PM(ii->opType())) {
707 computeUnit->vrfToLocalMemPipeBus[computeUnit->nextLocRdBus()].
708 preset(computeUnit->shader->ticks(8));
709 computeUnit->wfWait[computeUnit->ShrMemUnitId()].
710 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
711 } else if (IS_OT_READ_PM(ii->opType())) {
712 mem_reqs_in_pipe++;
713 rd_gm_reqs_in_pipe++;
712 memReqsInPipe++;
713 rdGmReqsInPipe++;
714 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
715 preset(computeUnit->shader->ticks(4));
716 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
717 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
718 } else if (IS_OT_WRITE_PM(ii->opType())) {
714 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
715 preset(computeUnit->shader->ticks(4));
716 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
717 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
718 } else if (IS_OT_WRITE_PM(ii->opType())) {
719 mem_reqs_in_pipe++;
720 wr_gm_reqs_in_pipe++;
719 memReqsInPipe++;
720 wrGmReqsInPipe++;
721 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
722 preset(computeUnit->shader->ticks(8));
723 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
724 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
725 } else if (IS_OT_ATOMIC_PM(ii->opType())) {
721 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
722 preset(computeUnit->shader->ticks(8));
723 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
724 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
725 } else if (IS_OT_ATOMIC_PM(ii->opType())) {
726 mem_reqs_in_pipe++;
727 wr_gm_reqs_in_pipe++;
728 rd_gm_reqs_in_pipe++;
726 memReqsInPipe++;
727 wrGmReqsInPipe++;
728 rdGmReqsInPipe++;
729 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
730 preset(computeUnit->shader->ticks(8));
731 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
732 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
733 }
734}
735
736void

--- 123 unchanged lines hidden (view full) ---

860 computeUnit->wfWait[computeUnit->ShrMemUnitId()].
861 set(computeUnit->shader->ticks(computeUnit->issuePeriod));
862 }
863}
864
865bool
866Wavefront::waitingAtBarrier(int lane)
867{
729 computeUnit->vrfToGlobalMemPipeBus[computeUnit->nextGlbRdBus()].
730 preset(computeUnit->shader->ticks(8));
731 computeUnit->wfWait[computeUnit->GlbMemUnitId()].
732 preset(computeUnit->shader->ticks(computeUnit->issuePeriod));
733 }
734}
735
736void

--- 123 unchanged lines hidden (view full) ---

860 computeUnit->wfWait[computeUnit->ShrMemUnitId()].
861 set(computeUnit->shader->ticks(computeUnit->issuePeriod));
862 }
863}
864
865bool
866Wavefront::waitingAtBarrier(int lane)
867{
868 return bar_cnt[lane] < max_bar_cnt;
868 return barCnt[lane] < maxBarCnt;
869}
870
871void
872Wavefront::pushToReconvergenceStack(uint32_t pc, uint32_t rpc,
873 const VectorMask& mask)
874{
875 assert(mask.count());
876 reconvergenceStack.emplace(new ReconvergenceStackEntry(pc, rpc, mask));

--- 57 unchanged lines hidden --- 		869}
870
871void
872Wavefront::pushToReconvergenceStack(uint32_t pc, uint32_t rpc,
873 const VectorMask& mask)
874{
875 assert(mask.count());
876 reconvergenceStack.emplace(new ReconvergenceStackEntry(pc, rpc, mask));

--- 57 unchanged lines hidden ---