vector_register_file.hh (11308:7d8836fd043d) vector_register_file.hh (11642:46cffde5d8a6)
1/*
2 * Copyright (c) 2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

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35
36#ifndef __VECTOR_REGISTER_FILE_HH__
37#define __VECTOR_REGISTER_FILE_HH__
38
39#include <list>
40
41#include "base/statistics.hh"
42#include "base/types.hh"
1/*
2 * Copyright (c) 2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

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35
36#ifndef __VECTOR_REGISTER_FILE_HH__
37#define __VECTOR_REGISTER_FILE_HH__
38
39#include <list>
40
41#include "base/statistics.hh"
42#include "base/types.hh"
43#include "debug/GPUVRF.hh"
43#include "gpu-compute/vector_register_state.hh"
44#include "sim/sim_object.hh"
45
46class ComputeUnit;
47class Shader;
48class SimplePoolManager;
49class Wavefront;
50

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66 void setParent(ComputeUnit *_computeUnit);
67
68 // Read a register
69 template<typename T>
70 T
71 read(int regIdx, int threadId=0)
72 {
73 T p0 = vgprState->read<T>(regIdx, threadId);
44#include "gpu-compute/vector_register_state.hh"
45#include "sim/sim_object.hh"
46
47class ComputeUnit;
48class Shader;
49class SimplePoolManager;
50class Wavefront;
51

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67 void setParent(ComputeUnit *_computeUnit);
68
69 // Read a register
70 template<typename T>
71 T
72 read(int regIdx, int threadId=0)
73 {
74 T p0 = vgprState->read<T>(regIdx, threadId);
75 DPRINTF(GPUVRF, "reading vreg[%d][%d] = %u\n", regIdx, threadId, (uint64_t)p0);
74
75 return p0;
76 }
77
78 // Write a register
79 template<typename T>
80 void
81 write(int regIdx, T value, int threadId=0)
82 {
76
77 return p0;
78 }
79
80 // Write a register
81 template<typename T>
82 void
83 write(int regIdx, T value, int threadId=0)
84 {
85 DPRINTF(GPUVRF, "writing vreg[%d][%d] = %u\n", regIdx, threadId, (uint64_t)value);
83 vgprState->write<T>(regIdx, value, threadId);
84 }
85
86 uint8_t regBusy(int idx, uint32_t operandSize) const;
87 uint8_t regNxtBusy(int idx, uint32_t operandSize) const;
88
89 int numRegs() const { return numRegsPerSimd; }
90

--- 52 unchanged lines hidden --- 		86 vgprState->write<T>(regIdx, value, threadId);
87 }
88
89 uint8_t regBusy(int idx, uint32_t operandSize) const;
90 uint8_t regNxtBusy(int idx, uint32_t operandSize) const;
91
92 int numRegs() const { return numRegsPerSimd; }
93

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