tlb_coalescer.hh (13784:1941dc118243) | tlb_coalescer.hh (13892:0182a0601f66) |
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1/* 2 * Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * For use for simulation and test purposes only 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: --- 35 unchanged lines hidden (view full) --- 44#include "arch/generic/tlb.hh" 45#include "arch/isa.hh" 46#include "arch/isa_traits.hh" 47#include "arch/x86/pagetable.hh" 48#include "arch/x86/regs/segment.hh" 49#include "base/logging.hh" 50#include "base/statistics.hh" 51#include "gpu-compute/gpu_tlb.hh" | 1/* 2 * Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * For use for simulation and test purposes only 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: --- 35 unchanged lines hidden (view full) --- 44#include "arch/generic/tlb.hh" 45#include "arch/isa.hh" 46#include "arch/isa_traits.hh" 47#include "arch/x86/pagetable.hh" 48#include "arch/x86/regs/segment.hh" 49#include "base/logging.hh" 50#include "base/statistics.hh" 51#include "gpu-compute/gpu_tlb.hh" |
52#include "mem/mem_object.hh" | |
53#include "mem/port.hh" 54#include "mem/request.hh" 55#include "params/TLBCoalescer.hh" | 52#include "mem/port.hh" 53#include "mem/request.hh" 54#include "params/TLBCoalescer.hh" |
55#include "sim/clocked_object.hh" |
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56 57class BaseTLB; 58class Packet; 59class ThreadContext; 60 61/** | 56 57class BaseTLB; 58class Packet; 59class ThreadContext; 60 61/** |
62 * The TLBCoalescer is a MemObject sitting on the front side (CPUSide) of | 62 * The TLBCoalescer is a ClockedObject sitting on the front side (CPUSide) of |
63 * each TLB. It receives packets and issues coalesced requests to the 64 * TLB below it. It controls how requests are coalesced (the rules) 65 * and the permitted number of TLB probes per cycle (i.e., how many 66 * coalesced requests it feeds the TLB per cycle). 67 */ | 63 * each TLB. It receives packets and issues coalesced requests to the 64 * TLB below it. It controls how requests are coalesced (the rules) 65 * and the permitted number of TLB probes per cycle (i.e., how many 66 * coalesced requests it feeds the TLB per cycle). 67 */ |
68class TLBCoalescer : public MemObject | 68class TLBCoalescer : public ClockedObject |
69{ 70 protected: 71 // TLB clock: will inherit clock from shader's clock period in terms 72 // of nuber of ticks of curTime (aka global simulation clock) 73 // The assignment of TLB clock from shader clock is done in the 74 // python config files. 75 int clock; 76 --- 155 unchanged lines hidden --- | 69{ 70 protected: 71 // TLB clock: will inherit clock from shader's clock period in terms 72 // of nuber of ticks of curTime (aka global simulation clock) 73 // The assignment of TLB clock from shader clock is done in the 74 // python config files. 75 int clock; 76 --- 155 unchanged lines hidden --- |