tlb_coalescer.cc (12697:cd71b966be1e) tlb_coalescer.cc (12717:2e2c211644d2)
1/*
2 * Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

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33 * Authors: Lisa Hsu
34 */
35
36#include "gpu-compute/tlb_coalescer.hh"
37
38#include <cstring>
39
40#include "debug/GPUTLB.hh"
1/*
2 * Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

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33 * Authors: Lisa Hsu
34 */
35
36#include "gpu-compute/tlb_coalescer.hh"
37
38#include <cstring>
39
40#include "debug/GPUTLB.hh"
41#include "sim/process.hh"
41
42TLBCoalescer::TLBCoalescer(const Params *p)
43 : MemObject(p),
44 clock(p->clk_domain->clockPeriod()),
45 TLBProbesPerCycle(p->probesPerCycle),
46 coalescingWindow(p->coalescingWindow),
47 disableCoalescing(p->disableCoalescing),
48 probeTLBEvent([this]{ processProbeTLBEvent(); },

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150 Addr virt_page_addr = roundDown(pkt->req->getVaddr(), TheISA::PageBytes);
151
152 DPRINTF(GPUTLB, "Update phys. addr. for %d coalesced reqs for page %#x\n",
153 issuedTranslationsTable[virt_page_addr].size(), virt_page_addr);
154
155 TheISA::GpuTLB::TranslationState *sender_state =
156 safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
157
42
43TLBCoalescer::TLBCoalescer(const Params *p)
44 : MemObject(p),
45 clock(p->clk_domain->clockPeriod()),
46 TLBProbesPerCycle(p->probesPerCycle),
47 coalescingWindow(p->coalescingWindow),
48 disableCoalescing(p->disableCoalescing),
49 probeTLBEvent([this]{ processProbeTLBEvent(); },

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151 Addr virt_page_addr = roundDown(pkt->req->getVaddr(), TheISA::PageBytes);
152
153 DPRINTF(GPUTLB, "Update phys. addr. for %d coalesced reqs for page %#x\n",
154 issuedTranslationsTable[virt_page_addr].size(), virt_page_addr);
155
156 TheISA::GpuTLB::TranslationState *sender_state =
157 safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
158
158 TheISA::GpuTlbEntry *tlb_entry = sender_state->tlbEntry;
159 TheISA::TlbEntry *tlb_entry = sender_state->tlbEntry;
159 assert(tlb_entry);
160 Addr first_entry_vaddr = tlb_entry->vaddr;
161 Addr first_entry_paddr = tlb_entry->paddr;
162 int page_size = tlb_entry->size();
163 bool uncacheable = tlb_entry->uncacheable;
164 int first_hit_level = sender_state->hitLevel;
160 assert(tlb_entry);
161 Addr first_entry_vaddr = tlb_entry->vaddr;
162 Addr first_entry_paddr = tlb_entry->paddr;
163 int page_size = tlb_entry->size();
164 bool uncacheable = tlb_entry->uncacheable;
165 int first_hit_level = sender_state->hitLevel;
165 bool valid = tlb_entry->valid;
166
167 // Get the physical page address of the translated request
168 // Using the page_size specified in the TLBEntry allows us
169 // to support different page sizes.
170 Addr phys_page_paddr = pkt->req->getPaddr();
171 phys_page_paddr &= ~(page_size - 1);
172
173 for (int i = 0; i < issuedTranslationsTable[virt_page_addr].size(); ++i) {

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192 paddr |= (local_pkt->req->getVaddr() & (page_size - 1));
193 local_pkt->req->setPaddr(paddr);
194
195 if (uncacheable)
196 local_pkt->req->setFlags(Request::UNCACHEABLE);
197
198 // update senderState->tlbEntry, so we can insert
199 // the correct TLBEentry in the TLBs above.
166
167 // Get the physical page address of the translated request
168 // Using the page_size specified in the TLBEntry allows us
169 // to support different page sizes.
170 Addr phys_page_paddr = pkt->req->getPaddr();
171 phys_page_paddr &= ~(page_size - 1);
172
173 for (int i = 0; i < issuedTranslationsTable[virt_page_addr].size(); ++i) {

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192 paddr |= (local_pkt->req->getVaddr() & (page_size - 1));
193 local_pkt->req->setPaddr(paddr);
194
195 if (uncacheable)
196 local_pkt->req->setFlags(Request::UNCACHEABLE);
197
198 // update senderState->tlbEntry, so we can insert
199 // the correct TLBEentry in the TLBs above.
200 auto p = sender_state->tc->getProcessPtr();
200 sender_state->tlbEntry =
201 sender_state->tlbEntry =
201 new TheISA::GpuTlbEntry(0, first_entry_vaddr, first_entry_paddr,
202 valid);
202 new TheISA::TlbEntry(p->pid(), first_entry_vaddr,
203 first_entry_paddr, false, false);
203
204 // update the hitLevel for all uncoalesced reqs
205 // so that each packet knows where it hit
206 // (used for statistics in the CUs)
207 sender_state->hitLevel = first_hit_level;
208 }
209
210 SlavePort *return_port = sender_state->ports.back();

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205 // update the hitLevel for all uncoalesced reqs
206 // so that each packet knows where it hit
207 // (used for statistics in the CUs)
208 sender_state->hitLevel = first_hit_level;
209 }
210
211 SlavePort *return_port = sender_state->ports.back();

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