1/*
2 * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
--- 64 unchanged lines hidden (view full) ---
73 void regStats();
74
75 private:
76 void collectStatistics(Wavefront *curWave, int unitId);
77 void initStatistics();
78 ComputeUnit *computeUnit;
79 uint32_t numSIMDs;
80 uint32_t numMemUnits;
81 uint32_t numGlbMemPipes;
82 uint32_t numShrMemPipes;
83
84 // flag per vector SIMD unit that is set when there is at least one
85 // WF that has a vector ALU instruction as the oldest in its
86 // Instruction Buffer
87 std::vector<bool> *vectorAluInstAvail;
88 int lastGlbMemSimd;
89 int lastShrMemSimd;
--- 17 unchanged lines hidden ---
2 * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
--- 64 unchanged lines hidden (view full) ---
73 void regStats();
74
75 private:
76 void collectStatistics(Wavefront *curWave, int unitId);
77 void initStatistics();
78 ComputeUnit *computeUnit;
79 uint32_t numSIMDs;
80 uint32_t numMemUnits;
81 uint32_t numGlbMemPipes;
82 uint32_t numShrMemPipes;
83
84 // flag per vector SIMD unit that is set when there is at least one
85 // WF that has a vector ALU instruction as the oldest in its
86 // Instruction Buffer
87 std::vector<bool> *vectorAluInstAvail;
88 int lastGlbMemSimd;
89 int lastShrMemSimd;
--- 17 unchanged lines hidden ---