local_memory_pipeline.cc (11534:7106f550afad) local_memory_pipeline.cc (11639:2e8d4bd8108d)
1/*
2 * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

--- 156 unchanged lines hidden (view full) ---

165 // models the timing aspect of the VRF write operation. It does not
166 // modify the physical VGPR.
167 loadVrfBankConflictCycles +=
168 w->computeUnit->vrf[w->simdId]->exec(m->seqNum(), w,
169 regVec, sizeof(c0), m->time);
170 }
171
172 // Decrement outstanding request count
1/*
2 * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

--- 156 unchanged lines hidden (view full) ---

165 // models the timing aspect of the VRF write operation. It does not
166 // modify the physical VGPR.
167 loadVrfBankConflictCycles +=
168 w->computeUnit->vrf[w->simdId]->exec(m->seqNum(), w,
169 regVec, sizeof(c0), m->time);
170 }
171
172 // Decrement outstanding request count
173 computeUnit->shader->ScheduleAdd(&w->outstanding_reqs, m->time, -1);
173 computeUnit->shader->ScheduleAdd(&w->outstandingReqs, m->time, -1);
174
175 if (m->m_op == Enums::MO_ST || MO_A(m->m_op) || MO_ANR(m->m_op)
176 || MO_H(m->m_op)) {
174
175 if (m->m_op == Enums::MO_ST || MO_A(m->m_op) || MO_ANR(m->m_op)
176 || MO_H(m->m_op)) {
177 computeUnit->shader->ScheduleAdd(&w->outstanding_reqs_wr_lm,
177 computeUnit->shader->ScheduleAdd(&w->outstandingReqsWrLm,
178 m->time, -1);
179 }
180
181 if (m->m_op == Enums::MO_LD || MO_A(m->m_op) || MO_ANR(m->m_op)) {
178 m->time, -1);
179 }
180
181 if (m->m_op == Enums::MO_LD || MO_A(m->m_op) || MO_ANR(m->m_op)) {
182 computeUnit->shader->ScheduleAdd(&w->outstanding_reqs_rd_lm,
182 computeUnit->shader->ScheduleAdd(&w->outstandingReqsRdLm,
183 m->time, -1);
184 }
185
186 // Mark write bus busy for appropriate amount of time
187 computeUnit->locMemToVrfBus.set(m->time);
188 if (computeUnit->shader->coissue_return == 0)
189 w->computeUnit->wfWait.at(m->pipeId).set(m->time);
190}
191
192void
193LocalMemPipeline::regStats()
194{
195 loadVrfBankConflictCycles
196 .name(name() + ".load_vrf_bank_conflict_cycles")
197 .desc("total number of cycles LDS data are delayed before updating "
198 "the VRF")
199 ;
200}
183 m->time, -1);
184 }
185
186 // Mark write bus busy for appropriate amount of time
187 computeUnit->locMemToVrfBus.set(m->time);
188 if (computeUnit->shader->coissue_return == 0)
189 w->computeUnit->wfWait.at(m->pipeId).set(m->time);
190}
191
192void
193LocalMemPipeline::regStats()
194{
195 loadVrfBankConflictCycles
196 .name(name() + ".load_vrf_bank_conflict_cycles")
197 .desc("total number of cycles LDS data are delayed before updating "
198 "the VRF")
199 ;
200}