gpu_tlb.cc (12749:223c83ed9979) gpu_tlb.cc (13449:2f7efa89c58b)
1/*
2 * Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

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40
41#include "arch/x86/faults.hh"
42#include "arch/x86/insts/microldstop.hh"
43#include "arch/x86/pagetable.hh"
44#include "arch/x86/pagetable_walker.hh"
45#include "arch/x86/regs/misc.hh"
46#include "arch/x86/x86_traits.hh"
47#include "base/bitfield.hh"
1/*
2 * Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

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40
41#include "arch/x86/faults.hh"
42#include "arch/x86/insts/microldstop.hh"
43#include "arch/x86/pagetable.hh"
44#include "arch/x86/pagetable_walker.hh"
45#include "arch/x86/regs/misc.hh"
46#include "arch/x86/x86_traits.hh"
47#include "base/bitfield.hh"
48#include "base/logging.hh"
48#include "base/output.hh"
49#include "base/trace.hh"
50#include "cpu/base.hh"
51#include "cpu/thread_context.hh"
52#include "debug/GPUPrefetch.hh"
53#include "debug/GPUTLB.hh"
54#include "mem/packet_access.hh"
55#include "mem/page_table.hh"

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1145 // Do paging protection checks.
1146 bool inUser = (m5Reg.cpl == 3 && !(flags & (CPL0FlagBit << FlagShift)));
1147 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
1148
1149 bool badWrite = (!tlb_entry->writable && (inUser || cr0.wp));
1150
1151 if ((inUser && !tlb_entry->user) ||
1152 (mode == BaseTLB::Write && badWrite)) {
49#include "base/output.hh"
50#include "base/trace.hh"
51#include "cpu/base.hh"
52#include "cpu/thread_context.hh"
53#include "debug/GPUPrefetch.hh"
54#include "debug/GPUTLB.hh"
55#include "mem/packet_access.hh"
56#include "mem/page_table.hh"

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1146 // Do paging protection checks.
1147 bool inUser = (m5Reg.cpl == 3 && !(flags & (CPL0FlagBit << FlagShift)));
1148 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
1149
1150 bool badWrite = (!tlb_entry->writable && (inUser || cr0.wp));
1151
1152 if ((inUser && !tlb_entry->user) ||
1153 (mode == BaseTLB::Write && badWrite)) {
1153 // The page must have been present to get into the TLB in
1154 // the first place. We'll assume the reserved bits are
1155 // fine even though we're not checking them.
1156 assert(false);
1154 // The page must have been present to get into the TLB in
1155 // the first place. We'll assume the reserved bits are
1156 // fine even though we're not checking them.
1157 panic("Page fault detected");
1157 }
1158
1159 if (storeCheck && badWrite) {
1158 }
1159
1160 if (storeCheck && badWrite) {
1160 // This would fault if this were a write, so return a page
1161 // fault that reflects that happening.
1162 assert(false);
1161 // This would fault if this were a write, so return a page
1162 // fault that reflects that happening.
1163 panic("Page fault detected");
1163 }
1164 }
1165
1166 /**
1167 * handleTranslationReturn is called on a TLB hit,
1168 * when a TLB miss returns or when a page fault returns.
1169 * The latter calls handelHit with TLB miss as tlbOutcome.
1170 */

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1357
1358 handleTranslationReturn(virtPageAddr, TLB_MISS, pkt);
1359 } else if (outcome == MISS_RETURN) {
1360 /** we add an extra cycle in the return path of the translation
1361 * requests in between the various TLB levels.
1362 */
1363 handleTranslationReturn(virtPageAddr, TLB_MISS, pkt);
1364 } else {
1164 }
1165 }
1166
1167 /**
1168 * handleTranslationReturn is called on a TLB hit,
1169 * when a TLB miss returns or when a page fault returns.
1170 * The latter calls handelHit with TLB miss as tlbOutcome.
1171 */

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1358
1359 handleTranslationReturn(virtPageAddr, TLB_MISS, pkt);
1360 } else if (outcome == MISS_RETURN) {
1361 /** we add an extra cycle in the return path of the translation
1362 * requests in between the various TLB levels.
1363 */
1364 handleTranslationReturn(virtPageAddr, TLB_MISS, pkt);
1365 } else {
1365 assert(false);
1366 panic("Unexpected TLB outcome %d", outcome);
1366 }
1367 }
1368
1369 void
1370 GpuTLB::TLBEvent::process()
1371 {
1372 tlb->translationReturn(virtPageAddr, outcome, pkt);
1373 }

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1602 tlb->handleFuncTranslationReturn(pkt, tlb_outcome);
1603 }
1604
1605 void
1606 GpuTLB::CpuSidePort::recvReqRetry()
1607 {
1608 // The CPUSidePort never sends anything but replies. No retries
1609 // expected.
1367 }
1368 }
1369
1370 void
1371 GpuTLB::TLBEvent::process()
1372 {
1373 tlb->translationReturn(virtPageAddr, outcome, pkt);
1374 }

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1603 tlb->handleFuncTranslationReturn(pkt, tlb_outcome);
1604 }
1605
1606 void
1607 GpuTLB::CpuSidePort::recvReqRetry()
1608 {
1609 // The CPUSidePort never sends anything but replies. No retries
1610 // expected.
1610 assert(false);
1611 panic("recvReqRetry called");
1611 }
1612
1613 AddrRangeList
1614 GpuTLB::CpuSidePort::getAddrRanges() const
1615 {
1616 // currently not checked by the master
1617 AddrRangeList ranges;
1618

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1643 return true;
1644 }
1645
1646 void
1647 GpuTLB::MemSidePort::recvReqRetry()
1648 {
1649 // No retries should reach the TLB. The retries
1650 // should only reach the TLBCoalescer.
1612 }
1613
1614 AddrRangeList
1615 GpuTLB::CpuSidePort::getAddrRanges() const
1616 {
1617 // currently not checked by the master
1618 AddrRangeList ranges;
1619

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1644 return true;
1645 }
1646
1647 void
1648 GpuTLB::MemSidePort::recvReqRetry()
1649 {
1650 // No retries should reach the TLB. The retries
1651 // should only reach the TLBCoalescer.
1651 assert(false);
1652 panic("recvReqRetry called");
1652 }
1653
1654 void
1655 GpuTLB::cleanup()
1656 {
1657 while (!cleanupQueue.empty()) {
1658 Addr cleanup_addr = cleanupQueue.front();
1659 cleanupQueue.pop();

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1654
1655 void
1656 GpuTLB::cleanup()
1657 {
1658 while (!cleanupQueue.empty()) {
1659 Addr cleanup_addr = cleanupQueue.front();
1660 cleanupQueue.pop();

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