1/* 2 * Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * For use for simulation and test purposes only 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: --- 794 unchanged lines hidden (view full) --- 803 804 if (FullSystem) { 805 fatal("GpuTLB doesn't support full-system mode\n"); 806 } else { 807 DPRINTF(GPUTLB, "Handling a TLB miss for address %#x " 808 "at pc %#x.\n", vaddr, tc->instAddr()); 809 810 Process *p = tc->getProcessPtr(); |
811 TlbEntry *newEntry = p->pTable->lookup(vaddr); |
812 |
813 if (!newEntry && mode != BaseTLB::Execute) { |
814 // penalize a "page fault" more |
815 if (timing) |
816 latency += missLatency2; |
817 818 if (p->fixupStackFault(vaddr)) |
819 newEntry = p->pTable->lookup(vaddr); |
820 } 821 |
822 if (!newEntry) { |
823 return std::make_shared<PageFault>(vaddr, true, 824 mode, true, 825 false); 826 } else { |
827 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 828 829 DPRINTF(GPUTLB, "Mapping %#x to %#x\n", |
830 alignedVaddr, newEntry->pageStart()); |
831 |
832 GpuTlbEntry gpuEntry; 833 *(TlbEntry *)&gpuEntry = *newEntry; 834 gpuEntry.valid = true; 835 entry = insert(alignedVaddr, gpuEntry); |
836 } 837 838 DPRINTF(GPUTLB, "Miss was serviced.\n"); 839 } 840 } else { 841 localNumTLBHits++; 842 843 if (timing) { --- 481 unchanged lines hidden (view full) --- 1325 // Need to access the page table and update the TLB 1326 DPRINTF(GPUTLB, "Doing a page walk for address %#x\n", 1327 virtPageAddr); 1328 1329 TranslationState *sender_state = 1330 safe_cast<TranslationState*>(pkt->senderState); 1331 1332 Process *p = sender_state->tc->getProcessPtr(); |
1333 Addr vaddr = pkt->req->getVaddr(); 1334 #ifndef NDEBUG 1335 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 1336 assert(alignedVaddr == virtPageAddr); 1337 #endif |
1338 TlbEntry *newEntry = p->pTable->lookup(vaddr); 1339 if (!newEntry && sender_state->tlbMode != BaseTLB::Execute && 1340 p->fixupStackFault(vaddr)) { 1341 newEntry = p->pTable->lookup(vaddr); |
1342 } 1343 |
1344 if (newEntry) { 1345 DPRINTF(GPUTLB, "Mapping %#x to %#x\n", alignedVaddr, 1346 newEntry->pageStart()); |
1347 |
1348 sender_state->tlbEntry = 1349 new GpuTlbEntry(0, newEntry->vaddr, newEntry->paddr, true); 1350 } else { 1351 sender_state->tlbEntry = 1352 new GpuTlbEntry(0, 0, 0, false); 1353 } |
1354 1355 handleTranslationReturn(virtPageAddr, TLB_MISS, pkt); 1356 } else if (outcome == MISS_RETURN) { 1357 /** we add an extra cycle in the return path of the translation 1358 * requests in between the various TLB levels. 1359 */ 1360 handleTranslationReturn(virtPageAddr, TLB_MISS, pkt); 1361 } else { --- 159 unchanged lines hidden (view full) --- 1521 if (sender_state->prefetch && !pkt->req->hasPaddr()) 1522 return; 1523 } else { 1524 // Need to access the page table and update the TLB 1525 DPRINTF(GPUTLB, "Doing a page walk for address %#x\n", 1526 virt_page_addr); 1527 1528 Process *p = tc->getProcessPtr(); |
1529 1530 Addr vaddr = pkt->req->getVaddr(); 1531 #ifndef NDEBUG 1532 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 1533 assert(alignedVaddr == virt_page_addr); 1534 #endif 1535 |
1536 TlbEntry *newEntry = p->pTable->lookup(vaddr); 1537 if (!newEntry && sender_state->tlbMode != BaseTLB::Execute && 1538 p->fixupStackFault(vaddr)) { 1539 newEntry = p->pTable->lookup(vaddr); |
1540 } 1541 1542 if (!sender_state->prefetch) { 1543 // no PageFaults are permitted after 1544 // the second page table lookup 1545 assert(success); 1546 1547 DPRINTF(GPUTLB, "Mapping %#x to %#x\n", alignedVaddr, |
1548 newEntry->pageStart()); |
1549 |
1550 sender_state->tlbEntry = 1551 new GpuTlbEntry(0, newEntry->vaddr, 1552 newEntry->paddr, success); |
1553 } else { 1554 // If this was a prefetch, then do the normal thing if it 1555 // was a successful translation. Otherwise, send an empty 1556 // TLB entry back so that it can be figured out as empty and 1557 // handled accordingly. |
1558 if (newEntry) { |
1559 DPRINTF(GPUTLB, "Mapping %#x to %#x\n", alignedVaddr, |
1560 newEntry->pageStart()); |
1561 |
1562 sender_state->tlbEntry = 1563 new GpuTlbEntry(0, newEntry->vaddr, 1564 newEntry->paddr, success); |
1565 } else { 1566 DPRINTF(GPUPrefetch, "Prefetch failed %#x\n", 1567 alignedVaddr); 1568 1569 sender_state->tlbEntry = new GpuTlbEntry(); 1570 1571 return; 1572 } --- 229 unchanged lines hidden --- |