gpu_static_inst.hh (11697:c63431b7bbeb) gpu_static_inst.hh (11699:c7453f485a5f)
1/*
2 * Copyright (c) 2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

--- 69 unchanged lines hidden (view full) ---

78 const std::string& disassemble();
79 virtual int getNumOperands() = 0;
80 virtual bool isCondRegister(int operandIndex) = 0;
81 virtual bool isScalarRegister(int operandIndex) = 0;
82 virtual bool isVectorRegister(int operandIndex) = 0;
83 virtual bool isSrcOperand(int operandIndex) = 0;
84 virtual bool isDstOperand(int operandIndex) = 0;
85 virtual int getOperandSize(int operandIndex) = 0;
1/*
2 * Copyright (c) 2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

--- 69 unchanged lines hidden (view full) ---

78 const std::string& disassemble();
79 virtual int getNumOperands() = 0;
80 virtual bool isCondRegister(int operandIndex) = 0;
81 virtual bool isScalarRegister(int operandIndex) = 0;
82 virtual bool isVectorRegister(int operandIndex) = 0;
83 virtual bool isSrcOperand(int operandIndex) = 0;
84 virtual bool isDstOperand(int operandIndex) = 0;
85 virtual int getOperandSize(int operandIndex) = 0;
86 virtual int getRegisterIndex(int operandIndex) = 0;
86
87 virtual int getRegisterIndex(int operandIndex,
88 GPUDynInstPtr gpuDynInst) = 0;
89
87 virtual int numDstRegOperands() = 0;
88 virtual int numSrcRegOperands() = 0;
89
90 virtual bool isValid() const = 0;
91
92 bool isALU() const { return _flags[ALU]; }
93 bool isBranch() const { return _flags[Branch]; }
94 bool isNop() const { return _flags[Nop]; }

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281
282 int getNumOperands() { return 0; }
283 bool isCondRegister(int operandIndex) { return false; }
284 bool isScalarRegister(int operandIndex) { return false; }
285 bool isVectorRegister(int operandIndex) { return false; }
286 bool isSrcOperand(int operandIndex) { return false; }
287 bool isDstOperand(int operandIndex) { return false; }
288 int getOperandSize(int operandIndex) { return 0; }
90 virtual int numDstRegOperands() = 0;
91 virtual int numSrcRegOperands() = 0;
92
93 virtual bool isValid() const = 0;
94
95 bool isALU() const { return _flags[ALU]; }
96 bool isBranch() const { return _flags[Branch]; }
97 bool isNop() const { return _flags[Nop]; }

--- 186 unchanged lines hidden (view full) ---

284
285 int getNumOperands() { return 0; }
286 bool isCondRegister(int operandIndex) { return false; }
287 bool isScalarRegister(int operandIndex) { return false; }
288 bool isVectorRegister(int operandIndex) { return false; }
289 bool isSrcOperand(int operandIndex) { return false; }
290 bool isDstOperand(int operandIndex) { return false; }
291 int getOperandSize(int operandIndex) { return 0; }
289 int getRegisterIndex(int operandIndex) { return 0; }
292
293 int
294 getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
295 {
296 return 0;
297 }
298
290 int numDstRegOperands() { return 0; }
291 int numSrcRegOperands() { return 0; }
292 bool isValid() const { return true; }
293 int instSize() const override { return 0; }
294};
295
296#endif // __GPU_STATIC_INST_HH__
299 int numDstRegOperands() { return 0; }
300 int numSrcRegOperands() { return 0; }
301 bool isValid() const { return true; }
302 int instSize() const override { return 0; }
303};
304
305#endif // __GPU_STATIC_INST_HH__