1/* 2 * Copyright (c) 2015 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * For use for simulation and test purposes only 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: --- 70 unchanged lines hidden (view full) --- 79 virtual bool isVectorRegister(int operandIndex) = 0; 80 virtual bool isSrcOperand(int operandIndex) = 0; 81 virtual bool isDstOperand(int operandIndex) = 0; 82 virtual int getOperandSize(int operandIndex) = 0; 83 virtual int getRegisterIndex(int operandIndex) = 0; 84 virtual int numDstRegOperands() = 0; 85 virtual int numSrcRegOperands() = 0; 86 |
87 virtual bool isValid() const = 0; 88 |
89 /* 90 * Most instructions (including all HSAIL instructions) 91 * are vector ops, so _scalarOp will be false by default. 92 * Derived instruction objects that are scalar ops must 93 * set _scalarOp to true in their constructors. 94 */ 95 bool scalarOp() const { return _scalarOp; } 96 --- 9 unchanged lines hidden (view full) --- 106 107 // only used for memory instructions 108 virtual void 109 initiateAcc(GPUDynInstPtr gpuDynInst) 110 { 111 fatal("calling initiateAcc() on a non-memory instruction.\n"); 112 } 113 |
114 // only used for memory instructions 115 virtual void 116 completeAcc(GPUDynInstPtr gpuDynInst) 117 { 118 fatal("calling completeAcc() on a non-memory instruction.\n"); 119 } 120 |
121 virtual uint32_t getTargetPc() { return 0; } 122 123 /** 124 * Query whether the instruction is an unconditional jump i.e., the jump 125 * is always executed because there is no condition to be evaluated. 126 * 127 * If the instruction is not of branch type, the result is always false. 128 * --- 47 unchanged lines hidden --- |