gpu_exec_context.cc (12697:cd71b966be1e) | gpu_exec_context.cc (13557:fc33e6048b25) |
---|---|
1/* 2 * Copyright (c) 2015 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * For use for simulation and test purposes only 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: --- 39 unchanged lines hidden (view full) --- 48} 49 50Wavefront* 51GPUExecContext::wavefront() 52{ 53 return wf; 54} 55 | 1/* 2 * Copyright (c) 2015 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * For use for simulation and test purposes only 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: --- 39 unchanged lines hidden (view full) --- 48} 49 50Wavefront* 51GPUExecContext::wavefront() 52{ 53 return wf; 54} 55 |
56TheGpuISA::MiscReg | 56RegVal |
57GPUExecContext::readMiscReg(int opIdx) const 58{ 59 assert(gpuISA); 60 return gpuISA->readMiscReg(opIdx); 61} 62 63void | 57GPUExecContext::readMiscReg(int opIdx) const 58{ 59 assert(gpuISA); 60 return gpuISA->readMiscReg(opIdx); 61} 62 63void |
64GPUExecContext::writeMiscReg(int opIdx, TheGpuISA::MiscReg operandVal) | 64GPUExecContext::writeMiscReg(int opIdx, RegVal operandVal) |
65{ 66 assert(gpuISA); 67 gpuISA->writeMiscReg(opIdx, operandVal); 68} | 65{ 66 assert(gpuISA); 67 gpuISA->writeMiscReg(opIdx, operandVal); 68} |