global_memory_pipeline.cc (11534:7106f550afad) global_memory_pipeline.cc (11639:2e8d4bd8108d)
1/*
2 * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

--- 198 unchanged lines hidden (view full) ---

207 }
208 } else {
209 gmReturnedStores.pop();
210 assert(inflightStores > 0);
211 --inflightStores;
212 }
213
214 // Decrement outstanding register count
1/*
2 * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

--- 198 unchanged lines hidden (view full) ---

207 }
208 } else {
209 gmReturnedStores.pop();
210 assert(inflightStores > 0);
211 --inflightStores;
212 }
213
214 // Decrement outstanding register count
215 computeUnit->shader->ScheduleAdd(&w->outstanding_reqs, m->time, -1);
215 computeUnit->shader->ScheduleAdd(&w->outstandingReqs, m->time, -1);
216
217 if (m->m_op == Enums::MO_ST || MO_A(m->m_op) || MO_ANR(m->m_op) ||
218 MO_H(m->m_op)) {
216
217 if (m->m_op == Enums::MO_ST || MO_A(m->m_op) || MO_ANR(m->m_op) ||
218 MO_H(m->m_op)) {
219 computeUnit->shader->ScheduleAdd(&w->outstanding_reqs_wr_gm, m->time,
219 computeUnit->shader->ScheduleAdd(&w->outstandingReqsWrGm, m->time,
220 -1);
221 }
222
223 if (m->m_op == Enums::MO_LD || MO_A(m->m_op) || MO_ANR(m->m_op)) {
220 -1);
221 }
222
223 if (m->m_op == Enums::MO_LD || MO_A(m->m_op) || MO_ANR(m->m_op)) {
224 computeUnit->shader->ScheduleAdd(&w->outstanding_reqs_rd_gm, m->time,
224 computeUnit->shader->ScheduleAdd(&w->outstandingReqsRdGm, m->time,
225 -1);
226 }
227
228 // Mark write bus busy for appropriate amount of time
229 computeUnit->glbMemToVrfBus.set(m->time);
230 if (!computeUnit->shader->coissue_return)
231 w->computeUnit->wfWait.at(m->pipeId).set(m->time);
232}
233
234void
235GlobalMemPipeline::regStats()
236{
237 loadVrfBankConflictCycles
238 .name(name() + ".load_vrf_bank_conflict_cycles")
239 .desc("total number of cycles GM data are delayed before updating "
240 "the VRF")
241 ;
242}
225 -1);
226 }
227
228 // Mark write bus busy for appropriate amount of time
229 computeUnit->glbMemToVrfBus.set(m->time);
230 if (!computeUnit->shader->coissue_return)
231 w->computeUnit->wfWait.at(m->pipeId).set(m->time);
232}
233
234void
235GlobalMemPipeline::regStats()
236{
237 loadVrfBankConflictCycles
238 .name(name() + ".load_vrf_bank_conflict_cycles")
239 .desc("total number of cycles GM data are delayed before updating "
240 "the VRF")
241 ;
242}