1/*
2 * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

--- 51 unchanged lines hidden (view full) ---

60void
61GlobalMemPipeline::exec()
62{
63 // apply any returned global memory operations
64 GPUDynInstPtr m = !gmReturnedLoads.empty() ? gmReturnedLoads.front() :
65 !gmReturnedStores.empty() ? gmReturnedStores.front() : nullptr;
66
67 bool accessVrf = true;
68 Wavefront *w = nullptr;
69
70 // check the VRF to see if the operands of a load (or load component
71 // of an atomic) are accessible
72 if ((m) && (m->isLoad() || m->isAtomicRet())) {
73 w = m->wavefront();
74
75 accessVrf =
76 w->computeUnit->vrf[w->simdId]->
77 vrfOperandAccessReady(m->seqNum(), w, m,
78 VrfAccessType::WRITE);
79 }
80
81 if ((!gmReturnedStores.empty() || !gmReturnedLoads.empty()) &&
82 m->latency.rdy() && computeUnit->glbMemToVrfBus.rdy() &&
83 accessVrf && m->statusBitVector == VectorMask(0) &&
84 (computeUnit->shader->coissue_return ||
85 computeUnit->wfWait.at(m->pipeId).rdy())) {
86
87 w = m->wavefront();
88
89 m->completeAcc(m);
90
91 if (m->isLoad() || m->isAtomic()) {
92 gmReturnedLoads.pop();
93 assert(inflightLoads > 0);
94 --inflightLoads;
95 } else {
96 assert(m->isStore());
97 gmReturnedStores.pop();
98 assert(inflightStores > 0);
99 --inflightStores;
100 }
101
102 // Decrement outstanding register count
103 computeUnit->shader->ScheduleAdd(&w->outstandingReqs, m->time, -1);
104
105 if (m->isStore() || m->isAtomic()) {
106 computeUnit->shader->ScheduleAdd(&w->outstandingReqsWrGm,
107 m->time, -1);
108 }
109
110 if (m->isLoad() || m->isAtomic()) {
111 computeUnit->shader->ScheduleAdd(&w->outstandingReqsRdGm,
112 m->time, -1);
113 }
114
115 // Mark write bus busy for appropriate amount of time
116 computeUnit->glbMemToVrfBus.set(m->time);
117 if (!computeUnit->shader->coissue_return)
118 w->computeUnit->wfWait.at(m->pipeId).set(m->time);
119 }
120
121 // If pipeline has executed a global memory instruction
122 // execute global memory packets and issue global
123 // memory packets to DTLB
124 if (!gmIssuedRequests.empty()) {
125 GPUDynInstPtr mp = gmIssuedRequests.front();
126 if (mp->isLoad() || mp->isAtomic()) {

--- 13 unchanged lines hidden (view full) ---

140 mp->initiateAcc(mp);
141 gmIssuedRequests.pop();
142
143 DPRINTF(GPUMem, "CU%d: WF[%d][%d] Popping 0 mem_op = \n",
144 computeUnit->cu_id, mp->simdId, mp->wfSlotId);
145 }
146}
147
148void
149GlobalMemPipeline::regStats()
150{
151 loadVrfBankConflictCycles
152 .name(name() + ".load_vrf_bank_conflict_cycles")
153 .desc("total number of cycles GM data are delayed before updating "
154 "the VRF")
155 ;
156}