1/*
2 * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
16 *
| 1/*
2 * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
16 *
|
17 * 3. Neither the name of the copyright holder nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
| 17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
|
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
| 20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
|
33 * Author: John Kalamatianos, Sooraj Puthoor
| 33 * Authors: John Kalamatianos,
34 * Sooraj Puthoor
|
34 */
35
36#ifndef __EXEC_STAGE_HH__
37#define __EXEC_STAGE_HH__
38
39#include <string>
40#include <utility>
41#include <vector>
42
43#include "sim/stats.hh"
44
45class ComputeUnit;
46class Wavefront;
47struct ComputeUnitParams;
48
49enum STAT_STATUS
50{
51 IdleExec,
52 BusyExec,
53 PostExec
54};
55
56enum DISPATCH_STATUS
57{
58 EMPTY = 0,
59 FILLED
60};
61
62// Execution stage.
63// Each execution resource executes the
64// wave which is in its dispatch list.
65// The schedule stage is responsible for
66// adding a wave into each execution resource's
67// dispatch list.
68
69class ExecStage
70{
71 public:
72 ExecStage(const ComputeUnitParams* params);
73 ~ExecStage() { }
74 void init(ComputeUnit *cu);
75 void exec();
76
77 std::string name() { return _name; }
78 void regStats();
79 // number of idle cycles
80 Stats::Scalar numCyclesWithNoIssue;
81 // number of busy cycles
82 Stats::Scalar numCyclesWithInstrIssued;
83 // number of cycles (per execution unit) during which at least one
84 // instruction was issued to that unit
85 Stats::Vector numCyclesWithInstrTypeIssued;
86 // number of idle cycles (per execution unit) during which the unit issued
87 // no instruction targeting that unit, even though there is at least one
88 // Wavefront with such an instruction as the oldest
89 Stats::Vector numCyclesWithNoInstrTypeIssued;
90 // SIMDs active per cycle
91 Stats::Distribution spc;
92
93 private:
94 void collectStatistics(enum STAT_STATUS stage, int unitId);
95 void initStatistics();
96 ComputeUnit *computeUnit;
97 uint32_t numSIMDs;
98
99 // Number of memory execution resources;
100 // both global and local memory execution resources in CU
101 uint32_t numMemUnits;
102
103 // List of waves which will be dispatched to
104 // each execution resource. A FILLED implies
105 // dispatch list is non-empty and
106 // execution unit has something to execute
107 // this cycle. Currently, the dispatch list of
108 // an execution resource can hold only one wave because
109 // an execution resource can execute only one wave in a cycle.
110 // dispatchList is used to communicate between schedule
111 // and exec stage
112 std::vector<std::pair<Wavefront*, DISPATCH_STATUS>> *dispatchList;
113 // flag per vector SIMD unit that is set when there is at least one
114 // WV that has a vector ALU instruction as the oldest in its
115 // Instruction Buffer
116 std::vector<bool> *vectorAluInstAvail;
117 int *glbMemInstAvail;
118 int *shrMemInstAvail;
119 bool lastTimeInstExecuted;
120 bool thisTimeInstExecuted;
121 bool instrExecuted;
122 Stats::Scalar numTransActiveIdle;
123 Stats::Distribution idleDur;
124 uint32_t executionResourcesUsed;
125 uint64_t idle_dur;
126 std::string _name;
127};
128
129#endif // __EXEC_STAGE_HH__
| 35 */
36
37#ifndef __EXEC_STAGE_HH__
38#define __EXEC_STAGE_HH__
39
40#include <string>
41#include <utility>
42#include <vector>
43
44#include "sim/stats.hh"
45
46class ComputeUnit;
47class Wavefront;
48struct ComputeUnitParams;
49
50enum STAT_STATUS
51{
52 IdleExec,
53 BusyExec,
54 PostExec
55};
56
57enum DISPATCH_STATUS
58{
59 EMPTY = 0,
60 FILLED
61};
62
63// Execution stage.
64// Each execution resource executes the
65// wave which is in its dispatch list.
66// The schedule stage is responsible for
67// adding a wave into each execution resource's
68// dispatch list.
69
70class ExecStage
71{
72 public:
73 ExecStage(const ComputeUnitParams* params);
74 ~ExecStage() { }
75 void init(ComputeUnit *cu);
76 void exec();
77
78 std::string name() { return _name; }
79 void regStats();
80 // number of idle cycles
81 Stats::Scalar numCyclesWithNoIssue;
82 // number of busy cycles
83 Stats::Scalar numCyclesWithInstrIssued;
84 // number of cycles (per execution unit) during which at least one
85 // instruction was issued to that unit
86 Stats::Vector numCyclesWithInstrTypeIssued;
87 // number of idle cycles (per execution unit) during which the unit issued
88 // no instruction targeting that unit, even though there is at least one
89 // Wavefront with such an instruction as the oldest
90 Stats::Vector numCyclesWithNoInstrTypeIssued;
91 // SIMDs active per cycle
92 Stats::Distribution spc;
93
94 private:
95 void collectStatistics(enum STAT_STATUS stage, int unitId);
96 void initStatistics();
97 ComputeUnit *computeUnit;
98 uint32_t numSIMDs;
99
100 // Number of memory execution resources;
101 // both global and local memory execution resources in CU
102 uint32_t numMemUnits;
103
104 // List of waves which will be dispatched to
105 // each execution resource. A FILLED implies
106 // dispatch list is non-empty and
107 // execution unit has something to execute
108 // this cycle. Currently, the dispatch list of
109 // an execution resource can hold only one wave because
110 // an execution resource can execute only one wave in a cycle.
111 // dispatchList is used to communicate between schedule
112 // and exec stage
113 std::vector<std::pair<Wavefront*, DISPATCH_STATUS>> *dispatchList;
114 // flag per vector SIMD unit that is set when there is at least one
115 // WV that has a vector ALU instruction as the oldest in its
116 // Instruction Buffer
117 std::vector<bool> *vectorAluInstAvail;
118 int *glbMemInstAvail;
119 int *shrMemInstAvail;
120 bool lastTimeInstExecuted;
121 bool thisTimeInstExecuted;
122 bool instrExecuted;
123 Stats::Scalar numTransActiveIdle;
124 Stats::Distribution idleDur;
125 uint32_t executionResourcesUsed;
126 uint64_t idle_dur;
127 std::string _name;
128};
129
130#endif // __EXEC_STAGE_HH__
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