1/* 2 * Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * For use for simulation and test purposes only 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: --- 39 unchanged lines hidden (view full) --- 48#include "enums/PrefetchType.hh" 49#include "gpu-compute/exec_stage.hh" 50#include "gpu-compute/fetch_stage.hh" 51#include "gpu-compute/global_memory_pipeline.hh" 52#include "gpu-compute/local_memory_pipeline.hh" 53#include "gpu-compute/qstruct.hh" 54#include "gpu-compute/schedule_stage.hh" 55#include "gpu-compute/scoreboard_check_stage.hh" |
56#include "mem/port.hh" |
57#include "sim/clocked_object.hh" |
58 59static const int MAX_REGS_FOR_NON_VEC_MEM_INST = 1; 60static const int MAX_WIDTH_FOR_MEM_INST = 32; 61 62class NDRange; 63class Shader; 64class VectorRegisterFile; 65 --- 20 unchanged lines hidden (view full) --- 86enum TLB_CACHE 87{ 88 TLB_MISS_CACHE_MISS = 0, 89 TLB_MISS_CACHE_HIT, 90 TLB_HIT_CACHE_MISS, 91 TLB_HIT_CACHE_HIT 92}; 93 |
94class ComputeUnit : public ClockedObject |
95{ 96 public: 97 FetchStage fetchStage; 98 ScoreboardCheckStage scoreboardCheckStage; 99 ScheduleStage scheduleStage; 100 ExecStage execStage; 101 GlobalMemPipeline globalMemoryPipe; 102 LocalMemPipeline localMemoryPipe; --- 649 unchanged lines hidden --- |