1/*
2 * Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

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296 bool isSimdDone(uint32_t) const;
297
298 protected:
299 MasterID _masterId;
300
301 LdsState &lds;
302
303 public:
304 // the following stats compute the avg. TLB accesslatency per
305 // uncoalesced request (only for data)
306 Stats::Scalar tlbRequests;
307 Stats::Scalar tlbCycles;
308 Stats::Formula tlbLatency;
309 // hitsPerTLBLevel[x] are the hits in Level x TLB. x = 0 is the page table.
310 Stats::Vector hitsPerTLBLevel;
311

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