357 ++wave_id;
358 }
359 }
360 ++barrier_id;
361}
362
363int
364ComputeUnit::ReadyWorkgroup(NDRange *ndr)
365{
366 // Get true size of workgroup (after clamping to grid size)
367 int trueWgSize[3];
368 int trueWgSizeTotal = 1;
369
370 for (int d = 0; d < 3; ++d) {
371 trueWgSize[d] = std::min(ndr->q.wgSize[d], ndr->q.gdSize[d] -
372 ndr->wgId[d] * ndr->q.wgSize[d]);
373
374 trueWgSizeTotal *= trueWgSize[d];
375 DPRINTF(GPUDisp, "trueWgSize[%d] = %d\n", d, trueWgSize[d]);
376 }
377
378 DPRINTF(GPUDisp, "trueWgSizeTotal = %d\n", trueWgSizeTotal);
379
380 // calculate the number of 32-bit vector registers required by each
381 // work item of the work group
382 int vregDemandPerWI = ndr->q.sRegCount + (2 * ndr->q.dRegCount);
383 bool vregAvail = true;
384 int numWfs = (trueWgSizeTotal + wfSize() - 1) / wfSize();
385 int freeWfSlots = 0;
386 // check if the total number of VGPRs required by all WFs of the WG
387 // fit in the VRFs of all SIMD units
388 assert((numWfs * vregDemandPerWI) <= (numSIMDs * numVecRegsPerSimd));
389 int numMappedWfs = 0;
390 std::vector<int> numWfsPerSimd;
391 numWfsPerSimd.resize(numSIMDs, 0);
392 // find how many free WF slots we have across all SIMDs
393 for (int j = 0; j < shader->n_wf; ++j) {
394 for (int i = 0; i < numSIMDs; ++i) {
395 if (wfList[i][j]->status == Wavefront::S_STOPPED) {
396 // count the number of free WF slots
397 ++freeWfSlots;
398 if (numMappedWfs < numWfs) {
399 // count the WFs to be assigned per SIMD
400 numWfsPerSimd[i]++;
401 }
402 numMappedWfs++;
403 }
404 }
405 }
406
407 // if there are enough free WF slots then find if there are enough
408 // free VGPRs per SIMD based on the WF->SIMD mapping
409 if (freeWfSlots >= numWfs) {
410 for (int j = 0; j < numSIMDs; ++j) {
411 // find if there are enough free VGPR regions in the SIMD's VRF
412 // to accommodate the WFs of the new WG that would be mapped to
413 // this SIMD unit
414 vregAvail = vrf[j]->manager->canAllocate(numWfsPerSimd[j],
415 vregDemandPerWI);
416
417 // stop searching if there is at least one SIMD
418 // whose VRF does not have enough free VGPR pools.
419 // This is because a WG is scheduled only if ALL
420 // of its WFs can be scheduled
421 if (!vregAvail)
422 break;
423 }
424 }
425
426 DPRINTF(GPUDisp, "Free WF slots = %d, VGPR Availability = %d\n",
427 freeWfSlots, vregAvail);
428
429 if (!vregAvail) {
430 ++numTimesWgBlockedDueVgprAlloc;
431 }
432
433 // Return true if enough WF slots to submit workgroup and if there are
434 // enough VGPRs to schedule all WFs to their SIMD units
435 if (!lds.canReserve(ndr->q.ldsSize)) {
436 wgBlockedDueLdsAllocation++;
437 }
438
439 // Return true if (a) there are enough free WF slots to submit
440 // workgrounp and (b) if there are enough VGPRs to schedule all WFs to their
441 // SIMD units and (c) if there is enough space in LDS
442 return freeWfSlots >= numWfs && vregAvail && lds.canReserve(ndr->q.ldsSize);
443}
444
445int
446ComputeUnit::AllAtBarrier(uint32_t _barrier_id, uint32_t bcnt, uint32_t bslots)
447{
448 DPRINTF(GPUSync, "CU%d: Checking for All At Barrier\n", cu_id);
449 int ccnt = 0;
450
451 for (int i_simd = 0; i_simd < numSIMDs; ++i_simd) {
452 for (int i_wf = 0; i_wf < shader->n_wf; ++i_wf) {
453 Wavefront *w = wfList[i_simd][i_wf];
454
455 if (w->status == Wavefront::S_RUNNING) {
456 DPRINTF(GPUSync, "Checking WF[%d][%d]\n", i_simd, i_wf);
457
458 DPRINTF(GPUSync, "wf->barrier_id = %d, _barrier_id = %d\n",
459 w->barrierId, _barrier_id);
460
461 DPRINTF(GPUSync, "wf->barrier_cnt %d, bcnt = %d\n",
462 w->barrierCnt, bcnt);
463 }
464
465 if (w->status == Wavefront::S_RUNNING &&
466 w->barrierId == _barrier_id && w->barrierCnt == bcnt &&
467 !w->outstandingReqs) {
468 ++ccnt;
469
470 DPRINTF(GPUSync, "WF[%d][%d] at barrier, increment ccnt to "
471 "%d\n", i_simd, i_wf, ccnt);
472 }
473 }
474 }
475
476 DPRINTF(GPUSync, "CU%d: returning allAtBarrier ccnt = %d, bslots = %d\n",
477 cu_id, ccnt, bslots);
478
479 return ccnt == bslots;
480}
481
482// Check if the current wavefront is blocked on additional resources.
483bool
484ComputeUnit::cedeSIMD(int simdId, int wfSlotId)
485{
486 bool cede = false;
487
488 // If --xact-cas-mode option is enabled in run.py, then xact_cas_ld
489 // magic instructions will impact the scheduling of wavefronts
490 if (xact_cas_mode) {
491 /*
492 * When a wavefront calls xact_cas_ld, it adds itself to a per address
493 * queue. All per address queues are managed by the xactCasLoadMap.
494 *
495 * A wavefront is not blocked if: it is not in ANY per address queue or
496 * if it is at the head of a per address queue.
497 */
498 for (auto itMap : xactCasLoadMap) {
499 std::list<waveIdentifier> curWaveIDQueue = itMap.second.waveIDQueue;
500
501 if (!curWaveIDQueue.empty()) {
502 for (auto it : curWaveIDQueue) {
503 waveIdentifier cur_wave = it;
504
505 if (cur_wave.simdId == simdId &&
506 cur_wave.wfSlotId == wfSlotId) {
507 // 2 possibilities
508 // 1: this WF has a green light
509 // 2: another WF has a green light
510 waveIdentifier owner_wave = curWaveIDQueue.front();
511
512 if (owner_wave.simdId != cur_wave.simdId ||
513 owner_wave.wfSlotId != cur_wave.wfSlotId) {
514 // possibility 2
515 cede = true;
516 break;
517 } else {
518 // possibility 1
519 break;
520 }
521 }
522 }
523 }
524 }
525 }
526
527 return cede;
528}
529
530// Execute one clock worth of work on the ComputeUnit.
531void
532ComputeUnit::exec()
533{
534 updateEvents();
535 // Execute pipeline stages in reverse order to simulate
536 // the pipeline latency
537 globalMemoryPipe.exec();
538 localMemoryPipe.exec();
539 execStage.exec();
540 scheduleStage.exec();
541 scoreboardCheckStage.exec();
542 fetchStage.exec();
543
544 totalCycles++;
545}
546
547void
548ComputeUnit::init()
549{
550 // Initialize CU Bus models
551 glbMemToVrfBus.init(&shader->tick_cnt, shader->ticks(1));
552 locMemToVrfBus.init(&shader->tick_cnt, shader->ticks(1));
553 nextGlbMemBus = 0;
554 nextLocMemBus = 0;
555 fatal_if(numGlbMemUnits > 1,
556 "No support for multiple Global Memory Pipelines exists!!!");
557 vrfToGlobalMemPipeBus.resize(numGlbMemUnits);
558 for (int j = 0; j < numGlbMemUnits; ++j) {
559 vrfToGlobalMemPipeBus[j] = WaitClass();
560 vrfToGlobalMemPipeBus[j].init(&shader->tick_cnt, shader->ticks(1));
561 }
562
563 fatal_if(numLocMemUnits > 1,
564 "No support for multiple Local Memory Pipelines exists!!!");
565 vrfToLocalMemPipeBus.resize(numLocMemUnits);
566 for (int j = 0; j < numLocMemUnits; ++j) {
567 vrfToLocalMemPipeBus[j] = WaitClass();
568 vrfToLocalMemPipeBus[j].init(&shader->tick_cnt, shader->ticks(1));
569 }
570 vectorRegsReserved.resize(numSIMDs, 0);
571 aluPipe.resize(numSIMDs);
572 wfWait.resize(numSIMDs + numLocMemUnits + numGlbMemUnits);
573
574 for (int i = 0; i < numSIMDs + numLocMemUnits + numGlbMemUnits; ++i) {
575 wfWait[i] = WaitClass();
576 wfWait[i].init(&shader->tick_cnt, shader->ticks(1));
577 }
578
579 for (int i = 0; i < numSIMDs; ++i) {
580 aluPipe[i] = WaitClass();
581 aluPipe[i].init(&shader->tick_cnt, shader->ticks(1));
582 }
583
584 // Setup space for call args
585 for (int j = 0; j < numSIMDs; ++j) {
586 for (int i = 0; i < shader->n_wf; ++i) {
587 wfList[j][i]->initCallArgMem(shader->funcargs_size, wavefrontSize);
588 }
589 }
590
591 // Initializing pipeline resources
592 readyList.resize(numSIMDs + numGlbMemUnits + numLocMemUnits);
593 waveStatusList.resize(numSIMDs);
594
595 for (int j = 0; j < numSIMDs; ++j) {
596 for (int i = 0; i < shader->n_wf; ++i) {
597 waveStatusList[j].push_back(
598 std::make_pair(wfList[j][i], BLOCKED));
599 }
600 }
601
602 for (int j = 0; j < (numSIMDs + numGlbMemUnits + numLocMemUnits); ++j) {
603 dispatchList.push_back(std::make_pair((Wavefront*)nullptr, EMPTY));
604 }
605
606 fetchStage.init(this);
607 scoreboardCheckStage.init(this);
608 scheduleStage.init(this);
609 execStage.init(this);
610 globalMemoryPipe.init(this);
611 localMemoryPipe.init(this);
612 // initialize state for statistics calculation
613 vectorAluInstAvail.resize(numSIMDs, false);
614 shrMemInstAvail = 0;
615 glbMemInstAvail = 0;
616}
617
618bool
619ComputeUnit::DataPort::recvTimingResp(PacketPtr pkt)
620{
621 // Ruby has completed the memory op. Schedule the mem_resp_event at the
622 // appropriate cycle to process the timing memory response
623 // This delay represents the pipeline delay
624 SenderState *sender_state = safe_cast<SenderState*>(pkt->senderState);
625 int index = sender_state->port_index;
626 GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst;
627
628 // Is the packet returned a Kernel End or Barrier
629 if (pkt->req->isKernel() && pkt->req->isRelease()) {
630 Wavefront *w =
631 computeUnit->wfList[gpuDynInst->simdId][gpuDynInst->wfSlotId];
632
633 // Check if we are waiting on Kernel End Release
634 if (w->status == Wavefront::S_RETURNING) {
635 DPRINTF(GPUDisp, "CU%d: WF[%d][%d][wv=%d]: WG id completed %d\n",
636 computeUnit->cu_id, w->simdId, w->wfSlotId,
637 w->wfDynId, w->kernId);
638
639 computeUnit->shader->dispatcher->notifyWgCompl(w);
640 w->status = Wavefront::S_STOPPED;
641 } else {
642 w->outstandingReqs--;
643 }
644
645 DPRINTF(GPUSync, "CU%d: WF[%d][%d]: barrier_cnt = %d\n",
646 computeUnit->cu_id, gpuDynInst->simdId,
647 gpuDynInst->wfSlotId, w->barrierCnt);
648
649 if (gpuDynInst->useContinuation) {
650 assert(gpuDynInst->scope != Enums::MEMORY_SCOPE_NONE);
651 gpuDynInst->execContinuation(gpuDynInst->staticInstruction(),
652 gpuDynInst);
653 }
654
655 delete pkt->senderState;
656 delete pkt->req;
657 delete pkt;
658 return true;
659 } else if (pkt->req->isKernel() && pkt->req->isAcquire()) {
660 if (gpuDynInst->useContinuation) {
661 assert(gpuDynInst->scope != Enums::MEMORY_SCOPE_NONE);
662 gpuDynInst->execContinuation(gpuDynInst->staticInstruction(),
663 gpuDynInst);
664 }
665
666 delete pkt->senderState;
667 delete pkt->req;
668 delete pkt;
669 return true;
670 }
671
672 ComputeUnit::DataPort::MemRespEvent *mem_resp_event =
673 new ComputeUnit::DataPort::MemRespEvent(computeUnit->memPort[index],
674 pkt);
675
676 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x received!\n",
677 computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
678 index, pkt->req->getPaddr());
679
680 computeUnit->schedule(mem_resp_event,
681 curTick() + computeUnit->resp_tick_latency);
682 return true;
683}
684
685void
686ComputeUnit::DataPort::recvReqRetry()
687{
688 int len = retries.size();
689
690 assert(len > 0);
691
692 for (int i = 0; i < len; ++i) {
693 PacketPtr pkt = retries.front().first;
694 GPUDynInstPtr gpuDynInst M5_VAR_USED = retries.front().second;
695 DPRINTF(GPUMem, "CU%d: WF[%d][%d]: retry mem inst addr %#x\n",
696 computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
697 pkt->req->getPaddr());
698
699 /** Currently Ruby can return false due to conflicts for the particular
700 * cache block or address. Thus other requests should be allowed to
701 * pass and the data port should expect multiple retries. */
702 if (!sendTimingReq(pkt)) {
703 DPRINTF(GPUMem, "failed again!\n");
704 break;
705 } else {
706 DPRINTF(GPUMem, "successful!\n");
707 retries.pop_front();
708 }
709 }
710}
711
712bool
713ComputeUnit::SQCPort::recvTimingResp(PacketPtr pkt)
714{
715 computeUnit->fetchStage.processFetchReturn(pkt);
716
717 return true;
718}
719
720void
721ComputeUnit::SQCPort::recvReqRetry()
722{
723 int len = retries.size();
724
725 assert(len > 0);
726
727 for (int i = 0; i < len; ++i) {
728 PacketPtr pkt = retries.front().first;
729 Wavefront *wavefront M5_VAR_USED = retries.front().second;
730 DPRINTF(GPUFetch, "CU%d: WF[%d][%d]: retrying FETCH addr %#x\n",
731 computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId,
732 pkt->req->getPaddr());
733 if (!sendTimingReq(pkt)) {
734 DPRINTF(GPUFetch, "failed again!\n");
735 break;
736 } else {
737 DPRINTF(GPUFetch, "successful!\n");
738 retries.pop_front();
739 }
740 }
741}
742
743void
744ComputeUnit::sendRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt)
745{
746 // There must be a way around this check to do the globalMemStart...
747 Addr tmp_vaddr = pkt->req->getVaddr();
748
749 updatePageDivergenceDist(tmp_vaddr);
750
751 pkt->req->setVirt(pkt->req->getAsid(), tmp_vaddr, pkt->req->getSize(),
752 pkt->req->getFlags(), pkt->req->masterId(),
753 pkt->req->getPC());
754
755 // figure out the type of the request to set read/write
756 BaseTLB::Mode TLB_mode;
757 assert(pkt->isRead() || pkt->isWrite());
758
759 // Check write before read for atomic operations
760 // since atomic operations should use BaseTLB::Write
761 if (pkt->isWrite()){
762 TLB_mode = BaseTLB::Write;
763 } else if (pkt->isRead()) {
764 TLB_mode = BaseTLB::Read;
765 } else {
766 fatal("pkt is not a read nor a write\n");
767 }
768
769 tlbCycles -= curTick();
770 ++tlbRequests;
771
772 int tlbPort_index = perLaneTLB ? index : 0;
773
774 if (shader->timingSim) {
775 if (debugSegFault) {
776 Process *p = shader->gpuTc->getProcessPtr();
777 Addr vaddr = pkt->req->getVaddr();
778 unsigned size = pkt->getSize();
779
780 if ((vaddr + size - 1) % 64 < vaddr % 64) {
781 panic("CU%d: WF[%d][%d]: Access to addr %#x is unaligned!\n",
782 cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, vaddr);
783 }
784
785 Addr paddr;
786
787 if (!p->pTable->translate(vaddr, paddr)) {
788 if (!p->fixupStackFault(vaddr)) {
789 panic("CU%d: WF[%d][%d]: Fault on addr %#x!\n",
790 cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
791 vaddr);
792 }
793 }
794 }
795
796 // This is the SenderState needed upon return
797 pkt->senderState = new DTLBPort::SenderState(gpuDynInst, index);
798
799 // This is the senderState needed by the TLB hierarchy to function
800 TheISA::GpuTLB::TranslationState *translation_state =
801 new TheISA::GpuTLB::TranslationState(TLB_mode, shader->gpuTc, false,
802 pkt->senderState);
803
804 pkt->senderState = translation_state;
805
806 if (functionalTLB) {
807 tlbPort[tlbPort_index]->sendFunctional(pkt);
808
809 // update the hitLevel distribution
810 int hit_level = translation_state->hitLevel;
811 assert(hit_level != -1);
812 hitsPerTLBLevel[hit_level]++;
813
814 // New SenderState for the memory access
815 X86ISA::GpuTLB::TranslationState *sender_state =
816 safe_cast<X86ISA::GpuTLB::TranslationState*>(pkt->senderState);
817
818 delete sender_state->tlbEntry;
819 delete sender_state->saved;
820 delete sender_state;
821
822 assert(pkt->req->hasPaddr());
823 assert(pkt->req->hasSize());
824
825 uint8_t *tmpData = pkt->getPtr<uint8_t>();
826
827 // this is necessary because the GPU TLB receives packets instead
828 // of requests. when the translation is complete, all relevent
829 // fields in the request will be populated, but not in the packet.
830 // here we create the new packet so we can set the size, addr,
831 // and proper flags.
832 PacketPtr oldPkt = pkt;
833 pkt = new Packet(oldPkt->req, oldPkt->cmd);
834 delete oldPkt;
835 pkt->dataStatic(tmpData);
836
837
838 // New SenderState for the memory access
839 pkt->senderState = new ComputeUnit::DataPort::SenderState(gpuDynInst,
840 index, nullptr);
841
842 gpuDynInst->memStatusVector[pkt->getAddr()].push_back(index);
843 gpuDynInst->tlbHitLevel[index] = hit_level;
844
845
846 // translation is done. Schedule the mem_req_event at the
847 // appropriate cycle to send the timing memory request to ruby
848 ComputeUnit::DataPort::MemReqEvent *mem_req_event =
849 new ComputeUnit::DataPort::MemReqEvent(memPort[index], pkt);
850
851 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x data "
852 "scheduled\n", cu_id, gpuDynInst->simdId,
853 gpuDynInst->wfSlotId, index, pkt->req->getPaddr());
854
855 schedule(mem_req_event, curTick() + req_tick_latency);
856 } else if (tlbPort[tlbPort_index]->isStalled()) {
857 assert(tlbPort[tlbPort_index]->retries.size() > 0);
858
859 DPRINTF(GPUTLB, "CU%d: WF[%d][%d]: Translation for addr %#x "
860 "failed!\n", cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
861 tmp_vaddr);
862
863 tlbPort[tlbPort_index]->retries.push_back(pkt);
864 } else if (!tlbPort[tlbPort_index]->sendTimingReq(pkt)) {
865 // Stall the data port;
866 // No more packet will be issued till
867 // ruby indicates resources are freed by
868 // a recvReqRetry() call back on this port.
869 tlbPort[tlbPort_index]->stallPort();
870
871 DPRINTF(GPUTLB, "CU%d: WF[%d][%d]: Translation for addr %#x "
872 "failed!\n", cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
873 tmp_vaddr);
874
875 tlbPort[tlbPort_index]->retries.push_back(pkt);
876 } else {
877 DPRINTF(GPUTLB,
878 "CU%d: WF[%d][%d]: Translation for addr %#x sent!\n",
879 cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, tmp_vaddr);
880 }
881 } else {
882 if (pkt->cmd == MemCmd::MemFenceReq) {
883 gpuDynInst->statusBitVector = VectorMask(0);
884 } else {
885 gpuDynInst->statusBitVector &= (~(1ll << index));
886 }
887
888 // New SenderState for the memory access
889 delete pkt->senderState;
890
891 // Because it's atomic operation, only need TLB translation state
892 pkt->senderState = new TheISA::GpuTLB::TranslationState(TLB_mode,
893 shader->gpuTc);
894
895 tlbPort[tlbPort_index]->sendFunctional(pkt);
896
897 // the addr of the packet is not modified, so we need to create a new
898 // packet, or otherwise the memory access will have the old virtual
899 // address sent in the translation packet, instead of the physical
900 // address returned by the translation.
901 PacketPtr new_pkt = new Packet(pkt->req, pkt->cmd);
902 new_pkt->dataStatic(pkt->getPtr<uint8_t>());
903
904 // Translation is done. It is safe to send the packet to memory.
905 memPort[0]->sendFunctional(new_pkt);
906
907 DPRINTF(GPUMem, "CU%d: WF[%d][%d]: index %d: addr %#x\n", cu_id,
908 gpuDynInst->simdId, gpuDynInst->wfSlotId, index,
909 new_pkt->req->getPaddr());
910
911 // safe_cast the senderState
912 TheISA::GpuTLB::TranslationState *sender_state =
913 safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
914
915 delete sender_state->tlbEntry;
916 delete new_pkt;
917 delete pkt->senderState;
918 delete pkt->req;
919 delete pkt;
920 }
921}
922
923void
924ComputeUnit::sendSyncRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt)
925{
926 ComputeUnit::DataPort::MemReqEvent *mem_req_event =
927 new ComputeUnit::DataPort::MemReqEvent(memPort[index], pkt);
928
929
930 // New SenderState for the memory access
931 pkt->senderState = new ComputeUnit::DataPort::SenderState(gpuDynInst, index,
932 nullptr);
933
934 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x sync scheduled\n",
935 cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, index,
936 pkt->req->getPaddr());
937
938 schedule(mem_req_event, curTick() + req_tick_latency);
939}
940
941void
942ComputeUnit::injectGlobalMemFence(GPUDynInstPtr gpuDynInst, bool kernelLaunch,
943 Request* req)
944{
945 if (!req) {
946 req = new Request(0, 0, 0, 0, masterId(), 0, gpuDynInst->wfDynId);
947 }
948 req->setPaddr(0);
949 if (kernelLaunch) {
950 req->setFlags(Request::KERNEL);
951 }
952
953 gpuDynInst->s_type = SEG_GLOBAL;
954
955 // for non-kernel MemFence operations, memorder flags are set depending
956 // on which type of request is currently being sent, so this
957 // should be set by the caller (e.g. if an inst has acq-rel
958 // semantics, it will send one acquire req an one release req)
959 gpuDynInst->setRequestFlags(req, kernelLaunch);
960
961 // a mem fence must correspond to an acquire/release request
962 assert(req->isAcquire() || req->isRelease());
963
964 // create packet
965 PacketPtr pkt = new Packet(req, MemCmd::MemFenceReq);
966
967 // set packet's sender state
968 pkt->senderState =
969 new ComputeUnit::DataPort::SenderState(gpuDynInst, 0, nullptr);
970
971 // send the packet
972 sendSyncRequest(gpuDynInst, 0, pkt);
973}
974
975const char*
976ComputeUnit::DataPort::MemRespEvent::description() const
977{
978 return "ComputeUnit memory response event";
979}
980
981void
982ComputeUnit::DataPort::MemRespEvent::process()
983{
984 DataPort::SenderState *sender_state =
985 safe_cast<DataPort::SenderState*>(pkt->senderState);
986
987 GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst;
988 ComputeUnit *compute_unit = dataPort->computeUnit;
989
990 assert(gpuDynInst);
991
992 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: Response for addr %#x, index %d\n",
993 compute_unit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
994 pkt->req->getPaddr(), dataPort->index);
995
996 Addr paddr = pkt->req->getPaddr();
997
998 if (pkt->cmd != MemCmd::MemFenceResp) {
999 int index = gpuDynInst->memStatusVector[paddr].back();
1000
1001 DPRINTF(GPUMem, "Response for addr %#x, index %d\n",
1002 pkt->req->getPaddr(), index);
1003
1004 gpuDynInst->memStatusVector[paddr].pop_back();
1005 gpuDynInst->pAddr = pkt->req->getPaddr();
1006
1007 if (pkt->isRead() || pkt->isWrite()) {
1008
1009 if (gpuDynInst->n_reg <= MAX_REGS_FOR_NON_VEC_MEM_INST) {
1010 gpuDynInst->statusBitVector &= (~(1ULL << index));
1011 } else {
1012 assert(gpuDynInst->statusVector[index] > 0);
1013 gpuDynInst->statusVector[index]--;
1014
1015 if (!gpuDynInst->statusVector[index])
1016 gpuDynInst->statusBitVector &= (~(1ULL << index));
1017 }
1018
1019 DPRINTF(GPUMem, "bitvector is now %#x\n",
1020 gpuDynInst->statusBitVector);
1021
1022 if (gpuDynInst->statusBitVector == VectorMask(0)) {
1023 auto iter = gpuDynInst->memStatusVector.begin();
1024 auto end = gpuDynInst->memStatusVector.end();
1025
1026 while (iter != end) {
1027 assert(iter->second.empty());
1028 ++iter;
1029 }
1030
1031 gpuDynInst->memStatusVector.clear();
1032
1033 if (gpuDynInst->n_reg > MAX_REGS_FOR_NON_VEC_MEM_INST)
1034 gpuDynInst->statusVector.clear();
1035
1036 if (gpuDynInst->m_op == Enums::MO_LD || MO_A(gpuDynInst->m_op)
1037 || MO_ANR(gpuDynInst->m_op)) {
1038 assert(compute_unit->globalMemoryPipe.isGMLdRespFIFOWrRdy());
1039
1040 compute_unit->globalMemoryPipe.getGMLdRespFIFO()
1041 .push(gpuDynInst);
1042 } else {
1043 assert(compute_unit->globalMemoryPipe.isGMStRespFIFOWrRdy());
1044
1045 compute_unit->globalMemoryPipe.getGMStRespFIFO()
1046 .push(gpuDynInst);
1047 }
1048
1049 DPRINTF(GPUMem, "CU%d: WF[%d][%d]: packet totally complete\n",
1050 compute_unit->cu_id, gpuDynInst->simdId,
1051 gpuDynInst->wfSlotId);
1052
1053 // after clearing the status vectors,
1054 // see if there is a continuation to perform
1055 // the continuation may generate more work for
1056 // this memory request
1057 if (gpuDynInst->useContinuation) {
1058 assert(gpuDynInst->scope != Enums::MEMORY_SCOPE_NONE);
1059 gpuDynInst->execContinuation(gpuDynInst->staticInstruction(),
1060 gpuDynInst);
1061 }
1062 }
1063 }
1064 } else {
1065 gpuDynInst->statusBitVector = VectorMask(0);
1066
1067 if (gpuDynInst->useContinuation) {
1068 assert(gpuDynInst->scope != Enums::MEMORY_SCOPE_NONE);
1069 gpuDynInst->execContinuation(gpuDynInst->staticInstruction(),
1070 gpuDynInst);
1071 }
1072 }
1073
1074 delete pkt->senderState;
1075 delete pkt->req;
1076 delete pkt;
1077}
1078
1079ComputeUnit*
1080ComputeUnitParams::create()
1081{
1082 return new ComputeUnit(this);
1083}
1084
1085bool
1086ComputeUnit::DTLBPort::recvTimingResp(PacketPtr pkt)
1087{
1088 Addr line = pkt->req->getPaddr();
1089
1090 DPRINTF(GPUTLB, "CU%d: DTLBPort received %#x->%#x\n", computeUnit->cu_id,
1091 pkt->req->getVaddr(), line);
1092
1093 assert(pkt->senderState);
1094 computeUnit->tlbCycles += curTick();
1095
1096 // pop off the TLB translation state
1097 TheISA::GpuTLB::TranslationState *translation_state =
1098 safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
1099
1100 // no PageFaults are permitted for data accesses
1101 if (!translation_state->tlbEntry->valid) {
1102 DTLBPort::SenderState *sender_state =
1103 safe_cast<DTLBPort::SenderState*>(translation_state->saved);
1104
1105 Wavefront *w M5_VAR_USED =
1106 computeUnit->wfList[sender_state->_gpuDynInst->simdId]
1107 [sender_state->_gpuDynInst->wfSlotId];
1108
1109 DPRINTFN("Wave %d couldn't tranlate vaddr %#x\n", w->wfDynId,
1110 pkt->req->getVaddr());
1111 }
1112
1113 assert(translation_state->tlbEntry->valid);
1114
1115 // update the hitLevel distribution
1116 int hit_level = translation_state->hitLevel;
1117 computeUnit->hitsPerTLBLevel[hit_level]++;
1118
1119 delete translation_state->tlbEntry;
1120 assert(!translation_state->ports.size());
1121 pkt->senderState = translation_state->saved;
1122
1123 // for prefetch pkt
1124 BaseTLB::Mode TLB_mode = translation_state->tlbMode;
1125
1126 delete translation_state;
1127
1128 // use the original sender state to know how to close this transaction
1129 DTLBPort::SenderState *sender_state =
1130 safe_cast<DTLBPort::SenderState*>(pkt->senderState);
1131
1132 GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst;
1133 int mp_index = sender_state->portIndex;
1134 Addr vaddr = pkt->req->getVaddr();
1135 gpuDynInst->memStatusVector[line].push_back(mp_index);
1136 gpuDynInst->tlbHitLevel[mp_index] = hit_level;
1137
1138 MemCmd requestCmd;
1139
1140 if (pkt->cmd == MemCmd::ReadResp) {
1141 requestCmd = MemCmd::ReadReq;
1142 } else if (pkt->cmd == MemCmd::WriteResp) {
1143 requestCmd = MemCmd::WriteReq;
1144 } else if (pkt->cmd == MemCmd::SwapResp) {
1145 requestCmd = MemCmd::SwapReq;
1146 } else {
1147 panic("unsupported response to request conversion %s\n",
1148 pkt->cmd.toString());
1149 }
1150
1151 if (computeUnit->prefetchDepth) {
1152 int simdId = gpuDynInst->simdId;
1153 int wfSlotId = gpuDynInst->wfSlotId;
1154 Addr last = 0;
1155
1156 switch(computeUnit->prefetchType) {
1157 case Enums::PF_CU:
1158 last = computeUnit->lastVaddrCU[mp_index];
1159 break;
1160 case Enums::PF_PHASE:
1161 last = computeUnit->lastVaddrSimd[simdId][mp_index];
1162 break;
1163 case Enums::PF_WF:
1164 last = computeUnit->lastVaddrWF[simdId][wfSlotId][mp_index];
1165 default:
1166 break;
1167 }
1168
1169 DPRINTF(GPUPrefetch, "CU[%d][%d][%d][%d]: %#x was last\n",
1170 computeUnit->cu_id, simdId, wfSlotId, mp_index, last);
1171
1172 int stride = last ? (roundDown(vaddr, TheISA::PageBytes) -
1173 roundDown(last, TheISA::PageBytes)) >> TheISA::PageShift
1174 : 0;
1175
1176 DPRINTF(GPUPrefetch, "Stride is %d\n", stride);
1177
1178 computeUnit->lastVaddrCU[mp_index] = vaddr;
1179 computeUnit->lastVaddrSimd[simdId][mp_index] = vaddr;
1180 computeUnit->lastVaddrWF[simdId][wfSlotId][mp_index] = vaddr;
1181
1182 stride = (computeUnit->prefetchType == Enums::PF_STRIDE) ?
1183 computeUnit->prefetchStride: stride;
1184
1185 DPRINTF(GPUPrefetch, "%#x to: CU[%d][%d][%d][%d]\n", vaddr,
1186 computeUnit->cu_id, simdId, wfSlotId, mp_index);
1187
1188 DPRINTF(GPUPrefetch, "Prefetching from %#x:", vaddr);
1189
1190 // Prefetch Next few pages atomically
1191 for (int pf = 1; pf <= computeUnit->prefetchDepth; ++pf) {
1192 DPRINTF(GPUPrefetch, "%d * %d: %#x\n", pf, stride,
1193 vaddr+stride*pf*TheISA::PageBytes);
1194
1195 if (!stride)
1196 break;
1197
1198 Request *prefetch_req = new Request(0, vaddr + stride * pf *
1199 TheISA::PageBytes,
1200 sizeof(uint8_t), 0,
1201 computeUnit->masterId(),
1202 0, 0, 0);
1203
1204 PacketPtr prefetch_pkt = new Packet(prefetch_req, requestCmd);
1205 uint8_t foo = 0;
1206 prefetch_pkt->dataStatic(&foo);
1207
1208 // Because it's atomic operation, only need TLB translation state
1209 prefetch_pkt->senderState =
1210 new TheISA::GpuTLB::TranslationState(TLB_mode,
1211 computeUnit->shader->gpuTc,
1212 true);
1213
1214 // Currently prefetches are zero-latency, hence the sendFunctional
1215 sendFunctional(prefetch_pkt);
1216
1217 /* safe_cast the senderState */
1218 TheISA::GpuTLB::TranslationState *tlb_state =
1219 safe_cast<TheISA::GpuTLB::TranslationState*>(
1220 prefetch_pkt->senderState);
1221
1222
1223 delete tlb_state->tlbEntry;
1224 delete tlb_state;
1225 delete prefetch_pkt->req;
1226 delete prefetch_pkt;
1227 }
1228 }
1229
1230 // First we must convert the response cmd back to a request cmd so that
1231 // the request can be sent through the cu's master port
1232 PacketPtr new_pkt = new Packet(pkt->req, requestCmd);
1233 new_pkt->dataStatic(pkt->getPtr<uint8_t>());
1234 delete pkt->senderState;
1235 delete pkt;
1236
1237 // New SenderState for the memory access
1238 new_pkt->senderState =
1239 new ComputeUnit::DataPort::SenderState(gpuDynInst, mp_index,
1240 nullptr);
1241
1242 // translation is done. Schedule the mem_req_event at the appropriate
1243 // cycle to send the timing memory request to ruby
1244 ComputeUnit::DataPort::MemReqEvent *mem_req_event =
1245 new ComputeUnit::DataPort::MemReqEvent(computeUnit->memPort[mp_index],
1246 new_pkt);
1247
1248 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x data scheduled\n",
1249 computeUnit->cu_id, gpuDynInst->simdId,
1250 gpuDynInst->wfSlotId, mp_index, new_pkt->req->getPaddr());
1251
1252 computeUnit->schedule(mem_req_event, curTick() +
1253 computeUnit->req_tick_latency);
1254
1255 return true;
1256}
1257
1258const char*
1259ComputeUnit::DataPort::MemReqEvent::description() const
1260{
1261 return "ComputeUnit memory request event";
1262}
1263
1264void
1265ComputeUnit::DataPort::MemReqEvent::process()
1266{
1267 SenderState *sender_state = safe_cast<SenderState*>(pkt->senderState);
1268 GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst;
1269 ComputeUnit *compute_unit M5_VAR_USED = dataPort->computeUnit;
1270
1271 if (!(dataPort->sendTimingReq(pkt))) {
1272 dataPort->retries.push_back(std::make_pair(pkt, gpuDynInst));
1273
1274 DPRINTF(GPUPort,
1275 "CU%d: WF[%d][%d]: index %d, addr %#x data req failed!\n",
1276 compute_unit->cu_id, gpuDynInst->simdId,
1277 gpuDynInst->wfSlotId, dataPort->index,
1278 pkt->req->getPaddr());
1279 } else {
1280 DPRINTF(GPUPort,
1281 "CU%d: WF[%d][%d]: index %d, addr %#x data req sent!\n",
1282 compute_unit->cu_id, gpuDynInst->simdId,
1283 gpuDynInst->wfSlotId, dataPort->index,
1284 pkt->req->getPaddr());
1285 }
1286}
1287
1288/*
1289 * The initial translation request could have been rejected,
1290 * if <retries> queue is not Retry sending the translation
1291 * request. sendRetry() is called from the peer port whenever
1292 * a translation completes.
1293 */
1294void
1295ComputeUnit::DTLBPort::recvReqRetry()
1296{
1297 int len = retries.size();
1298
1299 DPRINTF(GPUTLB, "CU%d: DTLB recvReqRetry - %d pending requests\n",
1300 computeUnit->cu_id, len);
1301
1302 assert(len > 0);
1303 assert(isStalled());
1304 // recvReqRetry is an indication that the resource on which this
1305 // port was stalling on is freed. So, remove the stall first
1306 unstallPort();
1307
1308 for (int i = 0; i < len; ++i) {
1309 PacketPtr pkt = retries.front();
1310 Addr vaddr M5_VAR_USED = pkt->req->getVaddr();
1311 DPRINTF(GPUTLB, "CU%d: retrying D-translaton for address%#x", vaddr);
1312
1313 if (!sendTimingReq(pkt)) {
1314 // Stall port
1315 stallPort();
1316 DPRINTF(GPUTLB, ": failed again\n");
1317 break;
1318 } else {
1319 DPRINTF(GPUTLB, ": successful\n");
1320 retries.pop_front();
1321 }
1322 }
1323}
1324
1325bool
1326ComputeUnit::ITLBPort::recvTimingResp(PacketPtr pkt)
1327{
1328 Addr line M5_VAR_USED = pkt->req->getPaddr();
1329 DPRINTF(GPUTLB, "CU%d: ITLBPort received %#x->%#x\n",
1330 computeUnit->cu_id, pkt->req->getVaddr(), line);
1331
1332 assert(pkt->senderState);
1333
1334 // pop off the TLB translation state
1335 TheISA::GpuTLB::TranslationState *translation_state =
1336 safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
1337
1338 bool success = translation_state->tlbEntry->valid;
1339 delete translation_state->tlbEntry;
1340 assert(!translation_state->ports.size());
1341 pkt->senderState = translation_state->saved;
1342 delete translation_state;
1343
1344 // use the original sender state to know how to close this transaction
1345 ITLBPort::SenderState *sender_state =
1346 safe_cast<ITLBPort::SenderState*>(pkt->senderState);
1347
1348 // get the wavefront associated with this translation request
1349 Wavefront *wavefront = sender_state->wavefront;
1350 delete pkt->senderState;
1351
1352 if (success) {
1353 // pkt is reused in fetch(), don't delete it here. However, we must
1354 // reset the command to be a request so that it can be sent through
1355 // the cu's master port
1356 assert(pkt->cmd == MemCmd::ReadResp);
1357 pkt->cmd = MemCmd::ReadReq;
1358
1359 computeUnit->fetchStage.fetch(pkt, wavefront);
1360 } else {
1361 if (wavefront->dropFetch) {
1362 assert(wavefront->instructionBuffer.empty());
1363 wavefront->dropFetch = false;
1364 }
1365
1366 wavefront->pendingFetch = 0;
1367 }
1368
1369 return true;
1370}
1371
1372/*
1373 * The initial translation request could have been rejected, if
1374 * <retries> queue is not empty. Retry sending the translation
1375 * request. sendRetry() is called from the peer port whenever
1376 * a translation completes.
1377 */
1378void
1379ComputeUnit::ITLBPort::recvReqRetry()
1380{
1381
1382 int len = retries.size();
1383 DPRINTF(GPUTLB, "CU%d: ITLB recvReqRetry - %d pending requests\n", len);
1384
1385 assert(len > 0);
1386 assert(isStalled());
1387
1388 // recvReqRetry is an indication that the resource on which this
1389 // port was stalling on is freed. So, remove the stall first
1390 unstallPort();
1391
1392 for (int i = 0; i < len; ++i) {
1393 PacketPtr pkt = retries.front();
1394 Addr vaddr M5_VAR_USED = pkt->req->getVaddr();
1395 DPRINTF(GPUTLB, "CU%d: retrying I-translaton for address%#x", vaddr);
1396
1397 if (!sendTimingReq(pkt)) {
1398 stallPort(); // Stall port
1399 DPRINTF(GPUTLB, ": failed again\n");
1400 break;
1401 } else {
1402 DPRINTF(GPUTLB, ": successful\n");
1403 retries.pop_front();
1404 }
1405 }
1406}
1407
1408void
1409ComputeUnit::regStats()
1410{
1411 MemObject::regStats();
1412
1413 tlbCycles
1414 .name(name() + ".tlb_cycles")
1415 .desc("total number of cycles for all uncoalesced requests")
1416 ;
1417
1418 tlbRequests
1419 .name(name() + ".tlb_requests")
1420 .desc("number of uncoalesced requests")
1421 ;
1422
1423 tlbLatency
1424 .name(name() + ".avg_translation_latency")
1425 .desc("Avg. translation latency for data translations")
1426 ;
1427
1428 tlbLatency = tlbCycles / tlbRequests;
1429
1430 hitsPerTLBLevel
1431 .init(4)
1432 .name(name() + ".TLB_hits_distribution")
1433 .desc("TLB hits distribution (0 for page table, x for Lx-TLB")
1434 ;
1435
1436 // fixed number of TLB levels
1437 for (int i = 0; i < 4; ++i) {
1438 if (!i)
1439 hitsPerTLBLevel.subname(i,"page_table");
1440 else
1441 hitsPerTLBLevel.subname(i, csprintf("L%d_TLB",i));
1442 }
1443
1444 execRateDist
1445 .init(0, 10, 2)
1446 .name(name() + ".inst_exec_rate")
1447 .desc("Instruction Execution Rate: Number of executed vector "
1448 "instructions per cycle")
1449 ;
1450
1451 ldsBankConflictDist
1452 .init(0, wfSize(), 2)
1453 .name(name() + ".lds_bank_conflicts")
1454 .desc("Number of bank conflicts per LDS memory packet")
1455 ;
1456
1457 ldsBankAccesses
1458 .name(name() + ".lds_bank_access_cnt")
1459 .desc("Total number of LDS bank accesses")
1460 ;
1461
1462 pageDivergenceDist
1463 // A wavefront can touch up to N pages per memory instruction where
1464 // N is equal to the wavefront size
1465 // The number of pages per bin can be configured (here it's 4).
1466 .init(1, wfSize(), 4)
1467 .name(name() + ".page_divergence_dist")
1468 .desc("pages touched per wf (over all mem. instr.)")
1469 ;
1470
1471 controlFlowDivergenceDist
1472 .init(1, wfSize(), 4)
1473 .name(name() + ".warp_execution_dist")
1474 .desc("number of lanes active per instruction (oval all instructions)")
1475 ;
1476
1477 activeLanesPerGMemInstrDist
1478 .init(1, wfSize(), 4)
1479 .name(name() + ".gmem_lanes_execution_dist")
1480 .desc("number of active lanes per global memory instruction")
1481 ;
1482
1483 activeLanesPerLMemInstrDist
1484 .init(1, wfSize(), 4)
1485 .name(name() + ".lmem_lanes_execution_dist")
1486 .desc("number of active lanes per local memory instruction")
1487 ;
1488
1489 numInstrExecuted
1490 .name(name() + ".num_instr_executed")
1491 .desc("number of instructions executed")
1492 ;
1493
1494 numVecOpsExecuted
1495 .name(name() + ".num_vec_ops_executed")
1496 .desc("number of vec ops executed (e.g. WF size/inst)")
1497 ;
1498
1499 totalCycles
1500 .name(name() + ".num_total_cycles")
1501 .desc("number of cycles the CU ran for")
1502 ;
1503
1504 ipc
1505 .name(name() + ".ipc")
1506 .desc("Instructions per cycle (this CU only)")
1507 ;
1508
1509 vpc
1510 .name(name() + ".vpc")
1511 .desc("Vector Operations per cycle (this CU only)")
1512 ;
1513
1514 numALUInstsExecuted
1515 .name(name() + ".num_alu_insts_executed")
1516 .desc("Number of dynamic non-GM memory insts executed")
1517 ;
1518
1519 wgBlockedDueLdsAllocation
1520 .name(name() + ".wg_blocked_due_lds_alloc")
1521 .desc("Workgroup blocked due to LDS capacity")
1522 ;
1523
1524 ipc = numInstrExecuted / totalCycles;
1525 vpc = numVecOpsExecuted / totalCycles;
1526
1527 numTimesWgBlockedDueVgprAlloc
1528 .name(name() + ".times_wg_blocked_due_vgpr_alloc")
1529 .desc("Number of times WGs are blocked due to VGPR allocation per SIMD")
1530 ;
1531
1532 dynamicGMemInstrCnt
1533 .name(name() + ".global_mem_instr_cnt")
1534 .desc("dynamic global memory instructions count")
1535 ;
1536
1537 dynamicLMemInstrCnt
1538 .name(name() + ".local_mem_instr_cnt")
1539 .desc("dynamic local memory intruction count")
1540 ;
1541
1542 numALUInstsExecuted = numInstrExecuted - dynamicGMemInstrCnt -
1543 dynamicLMemInstrCnt;
1544
1545 completedWfs
1546 .name(name() + ".num_completed_wfs")
1547 .desc("number of completed wavefronts")
1548 ;
1549
1550 numCASOps
1551 .name(name() + ".num_CAS_ops")
1552 .desc("number of compare and swap operations")
1553 ;
1554
1555 numFailedCASOps
1556 .name(name() + ".num_failed_CAS_ops")
1557 .desc("number of compare and swap operations that failed")
1558 ;
1559
1560 // register stats of pipeline stages
1561 fetchStage.regStats();
1562 scoreboardCheckStage.regStats();
1563 scheduleStage.regStats();
1564 execStage.regStats();
1565
1566 // register stats of memory pipeline
1567 globalMemoryPipe.regStats();
1568 localMemoryPipe.regStats();
1569}
1570
1571void
1572ComputeUnit::updatePageDivergenceDist(Addr addr)
1573{
1574 Addr virt_page_addr = roundDown(addr, TheISA::PageBytes);
1575
1576 if (!pagesTouched.count(virt_page_addr))
1577 pagesTouched[virt_page_addr] = 1;
1578 else
1579 pagesTouched[virt_page_addr]++;
1580}
1581
1582void
1583ComputeUnit::CUExitCallback::process()
1584{
1585 if (computeUnit->countPages) {
1586 std::ostream *page_stat_file =
1587 simout.create(computeUnit->name().c_str())->stream();
1588
1589 *page_stat_file << "page, wavefront accesses, workitem accesses" <<
1590 std::endl;
1591
1592 for (auto iter : computeUnit->pageAccesses) {
1593 *page_stat_file << std::hex << iter.first << ",";
1594 *page_stat_file << std::dec << iter.second.first << ",";
1595 *page_stat_file << std::dec << iter.second.second << std::endl;
1596 }
1597 }
1598 }
1599
1600bool
1601ComputeUnit::isDone() const
1602{
1603 for (int i = 0; i < numSIMDs; ++i) {
1604 if (!isSimdDone(i)) {
1605 return false;
1606 }
1607 }
1608
1609 bool glbMemBusRdy = true;
1610 for (int j = 0; j < numGlbMemUnits; ++j) {
1611 glbMemBusRdy &= vrfToGlobalMemPipeBus[j].rdy();
1612 }
1613 bool locMemBusRdy = true;
1614 for (int j = 0; j < numLocMemUnits; ++j) {
1615 locMemBusRdy &= vrfToLocalMemPipeBus[j].rdy();
1616 }
1617
1618 if (!globalMemoryPipe.isGMLdRespFIFOWrRdy() ||
1619 !globalMemoryPipe.isGMStRespFIFOWrRdy() ||
1620 !globalMemoryPipe.isGMReqFIFOWrRdy() || !localMemoryPipe.isLMReqFIFOWrRdy()
1621 || !localMemoryPipe.isLMRespFIFOWrRdy() || !locMemToVrfBus.rdy() ||
1622 !glbMemToVrfBus.rdy() || !locMemBusRdy || !glbMemBusRdy) {
1623 return false;
1624 }
1625
1626 return true;
1627}
1628
1629int32_t
1630ComputeUnit::getRefCounter(const uint32_t dispatchId, const uint32_t wgId) const
1631{
1632 return lds.getRefCounter(dispatchId, wgId);
1633}
1634
1635bool
1636ComputeUnit::isSimdDone(uint32_t simdId) const
1637{
1638 assert(simdId < numSIMDs);
1639
1640 for (int i=0; i < numGlbMemUnits; ++i) {
1641 if (!vrfToGlobalMemPipeBus[i].rdy())
1642 return false;
1643 }
1644 for (int i=0; i < numLocMemUnits; ++i) {
1645 if (!vrfToLocalMemPipeBus[i].rdy())
1646 return false;
1647 }
1648 if (!aluPipe[simdId].rdy()) {
1649 return false;
1650 }
1651
1652 for (int i_wf = 0; i_wf < shader->n_wf; ++i_wf){
1653 if (wfList[simdId][i_wf]->status != Wavefront::S_STOPPED) {
1654 return false;
1655 }
1656 }
1657
1658 return true;
1659}
1660
1661/**
1662 * send a general request to the LDS
1663 * make sure to look at the return value here as your request might be
1664 * NACK'd and returning false means that you have to have some backup plan
1665 */
1666bool
1667ComputeUnit::sendToLds(GPUDynInstPtr gpuDynInst)
1668{
1669 // this is just a request to carry the GPUDynInstPtr
1670 // back and forth
1671 Request *newRequest = new Request();
1672 newRequest->setPaddr(0x0);
1673
1674 // ReadReq is not evaluted by the LDS but the Packet ctor requires this
1675 PacketPtr newPacket = new Packet(newRequest, MemCmd::ReadReq);
1676
1677 // This is the SenderState needed upon return
1678 newPacket->senderState = new LDSPort::SenderState(gpuDynInst);
1679
1680 return ldsPort->sendTimingReq(newPacket);
1681}
1682
1683/**
1684 * get the result of packets sent to the LDS when they return
1685 */
1686bool
1687ComputeUnit::LDSPort::recvTimingResp(PacketPtr packet)
1688{
1689 const ComputeUnit::LDSPort::SenderState *senderState =
1690 dynamic_cast<ComputeUnit::LDSPort::SenderState *>(packet->senderState);
1691
1692 fatal_if(!senderState, "did not get the right sort of sender state");
1693
1694 GPUDynInstPtr gpuDynInst = senderState->getMemInst();
1695
1696 delete packet->senderState;
1697 delete packet->req;
1698 delete packet;
1699
1700 computeUnit->localMemoryPipe.getLMRespFIFO().push(gpuDynInst);
1701 return true;
1702}
1703
1704/**
1705 * attempt to send this packet, either the port is already stalled, the request
1706 * is nack'd and must stall or the request goes through
1707 * when a request cannot be sent, add it to the retries queue
1708 */
1709bool
1710ComputeUnit::LDSPort::sendTimingReq(PacketPtr pkt)
1711{
1712 ComputeUnit::LDSPort::SenderState *sender_state =
1713 dynamic_cast<ComputeUnit::LDSPort::SenderState*>(pkt->senderState);
1714 fatal_if(!sender_state, "packet without a valid sender state");
1715
1716 GPUDynInstPtr gpuDynInst M5_VAR_USED = sender_state->getMemInst();
1717
1718 if (isStalled()) {
1719 fatal_if(retries.empty(), "must have retries waiting to be stalled");
1720
1721 retries.push(pkt);
1722
1723 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: LDS send failed!\n",
1724 computeUnit->cu_id, gpuDynInst->simdId,
1725 gpuDynInst->wfSlotId);
1726 return false;
1727 } else if (!MasterPort::sendTimingReq(pkt)) {
1728 // need to stall the LDS port until a recvReqRetry() is received
1729 // this indicates that there is more space
1730 stallPort();
1731 retries.push(pkt);
1732
1733 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: addr %#x lds req failed!\n",
1734 computeUnit->cu_id, gpuDynInst->simdId,
1735 gpuDynInst->wfSlotId, pkt->req->getPaddr());
1736 return false;
1737 } else {
1738 DPRINTF(GPUPort, "CU%d: WF[%d][%d]: addr %#x lds req sent!\n",
1739 computeUnit->cu_id, gpuDynInst->simdId,
1740 gpuDynInst->wfSlotId, pkt->req->getPaddr());
1741 return true;
1742 }
1743}
1744
1745/**
1746 * the bus is telling the port that there is now space so retrying stalled
1747 * requests should work now
1748 * this allows the port to have a request be nack'd and then have the receiver
1749 * say when there is space, rather than simply retrying the send every cycle
1750 */
1751void
1752ComputeUnit::LDSPort::recvReqRetry()
1753{
1754 auto queueSize = retries.size();
1755
1756 DPRINTF(GPUPort, "CU%d: LDSPort recvReqRetry - %d pending requests\n",
1757 computeUnit->cu_id, queueSize);
1758
1759 fatal_if(queueSize < 1,
1760 "why was there a recvReqRetry() with no pending reqs?");
1761 fatal_if(!isStalled(),
1762 "recvReqRetry() happened when the port was not stalled");
1763
1764 unstallPort();
1765
1766 while (!retries.empty()) {
1767 PacketPtr packet = retries.front();
1768
1769 DPRINTF(GPUPort, "CU%d: retrying LDS send\n", computeUnit->cu_id);
1770
1771 if (!MasterPort::sendTimingReq(packet)) {
1772 // Stall port
1773 stallPort();
1774 DPRINTF(GPUPort, ": LDS send failed again\n");
1775 break;
1776 } else {
1777 DPRINTF(GPUTLB, ": LDS send successful\n");
1778 retries.pop();
1779 }
1780 }
1781}
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