1/*
2 * Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

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1403 }
1404}
1405
1406void
1407ComputeUnit::regStats()
1408{
1409 MemObject::regStats();
1410
1411 tlbCycles
1412 .name(name() + ".tlb_cycles")
1413 .desc("total number of cycles for all uncoalesced requests")
1414 ;
1415
1416 tlbRequests
1417 .name(name() + ".tlb_requests")
1418 .desc("number of uncoalesced requests")

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1562 execStage.regStats();
1563
1564 // register stats of memory pipeline
1565 globalMemoryPipe.regStats();
1566 localMemoryPipe.regStats();
1567}
1568
1569void
1570ComputeUnit::updatePageDivergenceDist(Addr addr)
1571{
1572 Addr virt_page_addr = roundDown(addr, TheISA::PageBytes);
1573
1574 if (!pagesTouched.count(virt_page_addr))
1575 pagesTouched[virt_page_addr] = 1;
1576 else
1577 pagesTouched[virt_page_addr]++;

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