X86GPUTLB.py (12697:cd71b966be1e) X86GPUTLB.py (13892:0182a0601f66)
1# Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# For use for simulation and test purposes only
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are met:
8#

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30# POSSIBILITY OF SUCH DAMAGE.
31#
32# Authors: Lisa Hsu
33
34from m5.defines import buildEnv
35from m5.params import *
36from m5.proxy import *
37
1# Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# For use for simulation and test purposes only
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are met:
8#

--- 21 unchanged lines hidden (view full) ---

30# POSSIBILITY OF SUCH DAMAGE.
31#
32# Authors: Lisa Hsu
33
34from m5.defines import buildEnv
35from m5.params import *
36from m5.proxy import *
37
38from m5.objects.MemObject import MemObject
38from m5.objects.ClockedObject import ClockedObject
39from m5.SimObject import SimObject
39
40if buildEnv['FULL_SYSTEM']:
40
41if buildEnv['FULL_SYSTEM']:
41 class X86PagetableWalker(MemObject):
42 class X86PagetableWalker(SimObject):
42 type = 'X86PagetableWalker'
43 cxx_class = 'X86ISA::Walker'
44 port = SlavePort("Port for the hardware table walker")
45 system = Param.System(Parent.any, "system object")
46
43 type = 'X86PagetableWalker'
44 cxx_class = 'X86ISA::Walker'
45 port = SlavePort("Port for the hardware table walker")
46 system = Param.System(Parent.any, "system object")
47
47class X86GPUTLB(MemObject):
48class X86GPUTLB(ClockedObject):
48 type = 'X86GPUTLB'
49 cxx_class = 'X86ISA::GpuTLB'
50 cxx_header = 'gpu-compute/gpu_tlb.hh'
51 size = Param.Int(64, "TLB size (number of entries)")
52 assoc = Param.Int(64, "TLB associativity")
53
54 if buildEnv['FULL_SYSTEM']:
55 walker = Param.X86PagetableWalker(X86PagetableWalker(),
56 "page table walker")
57
58 hitLatency = Param.Int(2, "Latency of a TLB hit")
59 missLatency1 = Param.Int(5, "Latency #1 of a TLB miss")
60 missLatency2 = Param.Int(100, "Latency #2 of a TLB miss")
61 maxOutstandingReqs = Param.Int(64, "# of maximum outstanding requests")
62 slave = VectorSlavePort("Port on side closer to CPU/CU")
63 master = VectorMasterPort("Port on side closer to memory")
64 allocationPolicy = Param.Bool(True, "Allocate on an access")
65 accessDistance = Param.Bool(False, "print accessDistance stats")
66
49 type = 'X86GPUTLB'
50 cxx_class = 'X86ISA::GpuTLB'
51 cxx_header = 'gpu-compute/gpu_tlb.hh'
52 size = Param.Int(64, "TLB size (number of entries)")
53 assoc = Param.Int(64, "TLB associativity")
54
55 if buildEnv['FULL_SYSTEM']:
56 walker = Param.X86PagetableWalker(X86PagetableWalker(),
57 "page table walker")
58
59 hitLatency = Param.Int(2, "Latency of a TLB hit")
60 missLatency1 = Param.Int(5, "Latency #1 of a TLB miss")
61 missLatency2 = Param.Int(100, "Latency #2 of a TLB miss")
62 maxOutstandingReqs = Param.Int(64, "# of maximum outstanding requests")
63 slave = VectorSlavePort("Port on side closer to CPU/CU")
64 master = VectorMasterPort("Port on side closer to memory")
65 allocationPolicy = Param.Bool(True, "Allocate on an access")
66 accessDistance = Param.Bool(False, "print accessDistance stats")
67
67class TLBCoalescer(MemObject):
68class TLBCoalescer(ClockedObject):
68 type = 'TLBCoalescer'
69 cxx_class = 'TLBCoalescer'
70 cxx_header = 'gpu-compute/tlb_coalescer.hh'
71 probesPerCycle = Param.Int(2, "Number of TLB probes per cycle")
72 coalescingWindow = Param.Int(1, "Permit coalescing across that many ticks")
73 slave = VectorSlavePort("Port on side closer to CPU/CU")
74 master = VectorMasterPort("Port on side closer to memory")
75 disableCoalescing = Param.Bool(False,"Dispable Coalescing")
69 type = 'TLBCoalescer'
70 cxx_class = 'TLBCoalescer'
71 cxx_header = 'gpu-compute/tlb_coalescer.hh'
72 probesPerCycle = Param.Int(2, "Number of TLB probes per cycle")
73 coalescingWindow = Param.Int(1, "Permit coalescing across that many ticks")
74 slave = VectorSlavePort("Port on side closer to CPU/CU")
75 master = VectorMasterPort("Port on side closer to memory")
76 disableCoalescing = Param.Bool(False,"Dispable Coalescing")